Home
last modified time | relevance | path

Searched refs:RIU_WriteRegBit (Results 1 – 25 of 54) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c147 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6292 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6516 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6522 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6555 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6561 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6620 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6826 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6280 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6498 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6504 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6537 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6543 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6584 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6585 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6598 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6804 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c143 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
2934 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
3129 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3135 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3168 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3174 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3215 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3216 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3434 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6278 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6496 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6502 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6535 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6541 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6581 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6582 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6790 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6278 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6496 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6502 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6535 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6541 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6581 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6582 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6790 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c143 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
2934 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
3129 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3135 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3168 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3174 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3215 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3216 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3434 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
2933 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
3128 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3134 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3167 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3173 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3214 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3215 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3431 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3433 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/manhattan/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1343 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1484 RIU_WriteRegBit(0x12840L, 0, _BIT4); // Ref Enable in msVifAdcInitial()
1485 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1529 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1530 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1532 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1534 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1535 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2643 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/mooney/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1362 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1521 RIU_WriteRegBit(0x12000L, 1, _BIT4); in msVifAdcInitial()
1522 RIU_WriteRegBit(0x12004L, 1, _BIT1); in msVifAdcInitial()
1625 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1626 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1629 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1631 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1632 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2735 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/maserati/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1770 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1803 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1804 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1807 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1809 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1810 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2933 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2934 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/M7821/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1770 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1803 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1804 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1807 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1809 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1810 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2933 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2934 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/maxim/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1780 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1813 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1814 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1817 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1819 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1820 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2943 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2944 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/M7621/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1771 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1804 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1805 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1808 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1810 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1811 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2934 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2935 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/macan/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1548 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1766 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1799 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1800 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1803 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1805 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1806 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2921 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2922 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/mustang/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1361 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1579 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1612 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1613 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1616 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1618 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1619 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2731 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2732 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/maldives/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1353 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1481 RIU_WriteRegBit(0x12840L, 0, _BIT4); in msVifAdcInitial()
1482 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1516 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1517 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1519 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1521 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1522 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2622 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/mainz/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1339 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1482 RIU_WriteRegBit(0x12840L, 0, _BIT4); // Ref Enable in msVifAdcInitial()
1483 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1527 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1528 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1530 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1532 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1533 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2633 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/vif/hal/messi/vif/
H A DhalVIF.c162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1339 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1482 RIU_WriteRegBit(0x12840L, 0, _BIT4); // Ref Enable in msVifAdcInitial()
1483 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1527 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1528 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1530 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1532 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1533 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2633 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.c137 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
388 RIU_WriteRegBit(u32Addr, bEnable, u8Mask); in HAL_DMD_RIU_WriteRegBit()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.c137 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
388 RIU_WriteRegBit(u32Addr, bEnable, u8Mask); in HAL_DMD_RIU_WriteRegBit()

123