Lines Matching refs:RIU_WriteRegBit
142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6278 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6496 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6502 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6535 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6541 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6581 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6582 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6790 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6829 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
6839 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6840 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
6841 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6845 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
6846 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
6863 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6865 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6866 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6886 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6946 RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5)); in HAL_AVD_AFEC_SetPatchFlag()
7005 RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6] in HAL_AVD_AFEC_SetInput()
7019 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7024 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7039 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7044 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7061 RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7066 RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C in HAL_AVD_AFEC_SetInput()
7080 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7085 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7099 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD in HAL_AVD_AFEC_SetInput()
7119 RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7123 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7128 RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7129 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7130 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move … in HAL_AVD_AFEC_SetInput()
7131 RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware in HAL_AVD_AFEC_SetInput()
7138 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7139 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7140 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7141 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7150 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7154 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7155 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7156 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7157 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7244 RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7))); in HAL_AVD_AFEC_SetHTotal()
7262 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
7266 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
7301 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7335 RIU_WriteRegBit( BK_AFEC_CE, bEnable, BIT(0)); in HAL_AVD_AFEC_EnableForceMode()
7386 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
7387 RIU_WriteRegBit(BK_AFEC_CF, bEnable, BIT(2)); in HAL_AVD_AFEC_EnableCVBSLPF()
7428 RIU_WriteRegBit(BK_AFEC_D4, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableVBIDPLSpeedup()
7447 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7449 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7468 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7470 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7489 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7491 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7635 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); // BK_COMB_4C[7] COMB memory prote… in HAL_AVD_COMB_SetMemoryProtect()
7655 RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7656 RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7660 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7661 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7682 … RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7694 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7921 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
7928 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
7934 RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
7941 RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
8016 RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8020 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8089 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8091 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8116 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()
8134 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()