Lines Matching refs:RIU_WriteRegBit
162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask); in msWriteBit()
1771 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG in msVifAdcInitial()
1804 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1); in msVifAdcInitial()
1805 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5); in msVifAdcInitial()
1808 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable in msVifAdcInitial()
1810 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable in msVifAdcInitial()
1811 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable in msVifAdcInitial()
2934 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0); in msVifLoad()
2935 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0); in msVifLoad()
2936 RIU_WriteRegBit(DBB2_LOAD , 1 , _BIT0); in msVifLoad()
2937 RIU_WriteRegBit(DBB2_LOAD , 0, _BIT0); in msVifLoad()
3488 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); in msVifExit()
3489 RIU_WriteRegBit(IFAGC_ENABLE, 0, _BIT4); in msVifExit()
4048 RIU_WriteRegBit(0x120A0L, 0, _BIT4); // 0:FIR, 1:IIR in msVifLoadEQCoeff()
4070 RIU_WriteRegBit(0x120A0L, 1, _BIT4); // 0:FIR, 1:IIR in msVifLoadEQCoeff()