1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 #ifndef _HALVIF_C_
95 #define _HALVIF_C_
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #include "MsCommon.h"
102 #include "MsIRQ.h"
103 #include "MsOS.h"
104 #include "MsTypes.h"
105 #include "drvMMIO.h"
106
107 // Internal Definition
108 #include "regVIF.h"
109 #include "drvVIF.h"
110 #include "halVIF.h"
111 #include "halVIF_Customer.h"
112 #include "asmCPU.h"
113 //-------------------------------------------------------------------------------------------------
114 // Driver Compiler Options
115 //-------------------------------------------------------------------------------------------------
116 #define HALVIFDBG(x) //x
117 #define HALVIFDBG_BIT (DBB1_REG_BASE+0x06) // Bit 4~7
118 #define HALVIFDBG1_BIT (DBB1_REG_BASE+0x04) // Bit 1
119 #define HALVIFDBG2_BIT (DBB1_REG_BASE+0xF6) // Bit 0
120 //-------------------------------------------------------------------------------------------------
121 // extern function
122 //-------------------------------------------------------------------------------------------------
123 #define HAL_VIF_Delay1ms(x) MAsm_CPU_DelayMs(x)
124 #define HAL_VIF_Delay1us(x) MAsm_CPU_DelayUs(x)
125 #define HAL_VIF_GetSystemTime() MsOS_GetSystemTime()
126 //-------------------------------------------------------------------------------------------------
127 // Local Defines
128 //-------------------------------------------------------------------------------------------------
129 #define __CHIP_VERSION 0x1ECF
130
131 #ifndef _END_OF_TBL_
132 #define _END_OF_TBL_ 0xFFFF
133 #endif
134
135 #define msRead2Bytes(x) RIU_Read2Byte(x)
136 #define msReadByte(x) RIU_ReadByte(x)
137
138 // Base address should be initial.
139 #if defined (__aeon__) // Non-OS
140 #define BASEADDR_RIU 0xA0000000
141 #else // ecos
142 #define BASEADDR_RIU 0xBF800000
143 #endif
144
145 #define RIU_MACRO_START do {
146 #define RIU_MACRO_END } while (0)
147
148 // Address bus of RIU is 16 bits.
149 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_VIF.u32VIFBaseAddr + (addr) ) )
150 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_VIF.u32VIFBaseAddr + (addr) ) )
151 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_VIF.u32VIFBaseAddr + (addr), val) }
152 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_VIF.u32VIFBaseAddr + (addr), val) }
153
154 // Standard Form
155
156 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
157
158 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
159
160 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
161
162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
163 RIU_MACRO_START \
164 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
165 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
166 RIU_MACRO_END
167
168 #define RIU_WriteByte( u32Reg, u8Val ) \
169 RIU_MACRO_START \
170 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
171 RIU_MACRO_END
172
173 #define RIU_Write2Byte( u32Reg, u16Val ) \
174 RIU_MACRO_START \
175 if ( ((u32Reg) & 0x01) ) \
176 { \
177 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
178 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
179 } \
180 else \
181 { \
182 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
183 } \
184 RIU_MACRO_END
185
186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
187 RIU_MACRO_START \
188 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
189 RIU_MACRO_END
190
191 // Address bus of RIU is 16 bits for PM bank.
192 #define PM_RIU_READ_BYTE(addr) ( READ_BYTE(u32PMBank + (addr) ) )
193 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD( u32PMBank+ (addr) ) )
194 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( u32PMBank + (addr), val) }
195 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( u32PMBank + (addr), val) }
196
197 // Standard Form for PM bank
198 #define PM_RIU_ReadByte( u32Reg ) PM_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
199
200 #define PM_RIU_Read2Byte( u32Reg ) (PM_RIU_READ_2BYTE((u32Reg)<<1))
201
202 #define PM_RIU_ReadRegBit( u32Reg, u8Mask ) (PM_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
203
204 #define PM_RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
205 RIU_MACRO_START \
206 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
207 (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
208 RIU_MACRO_END
209
210 #define PM_RIU_WriteByte( u32Reg, u8Val ) \
211 RIU_MACRO_START \
212 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
213 RIU_MACRO_END
214
215 #define PM_RIU_Write2Byte( u32Reg, u16Val ) \
216 RIU_MACRO_START \
217 if ( ((u32Reg) & 0x01) ) \
218 { \
219 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
220 PM_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
221 } \
222 else \
223 { \
224 PM_RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
225 } \
226 RIU_MACRO_END
227
228 #define PM_RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
229 RIU_MACRO_START \
230 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (PM_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
231 RIU_MACRO_END
232
233 //-------------------------------------------------------------------------------------------------
234 // Local Structures
235 //-------------------------------------------------------------------------------------------------
236 typedef struct
237 {
238 DWORD u32VIFBaseAddr;
239 DWORD bBaseAddrInitialized;
240 } hal_VIF_t;
241
242 //-------------------------------------------------------------------------------------------------
243 // Local Variables
244 //-------------------------------------------------------------------------------------------------
245 static hal_VIF_t _hal_VIF ={BASEADDR_RIU, 0};
246 extern VIFInitialIn VIFInitialIn_inst;
247 extern VIFSOS33 sVIFSOS33;
248 extern BOOL bEnableUsrSteadyAgcK;
249 extern U8 u8UsrSteadyAgcK;
250 extern BOOL bEnableUsrNonSteadyAgcK;
251 extern U8 u8UsrNonSteadyAgcK;
252 /////////////////////////////////////////////////////
253 BOOL AGC_Change_Index; //for Serious ACI Parameter
254 int SeriousACI_Index = 0;
255 BYTE ADC_Index= 0;
256 BYTE ADC_Underflow_Index = 0;
257 BYTE ADC_Overflow_Index= 0;
258 BYTE PGA = 0;
259 WORD VGA = 0;
260 ////////////////////////////////////////////////////
261
262
263 //-------------------------------------------------------------------------------------------------
264 // Local code data
265 //-------------------------------------------------------------------------------------------------
266 MS_VIF_REG_TYPE VIF_GDE_PEAKING_1dB[]=
267 {
268 {SOS21_C0_L,0xc1}, // SOS21 peaking
269 {SOS21_C0_H,0x02},
270 {SOS21_C1_L,0x87},
271 {SOS21_C1_H,0x06},
272 {SOS21_C2_L,0x08},
273 {SOS21_C2_H,0x02},
274 {SOS21_C3_L,0x3f},
275 {SOS21_C3_H,0x05},
276 {SOS21_C4_L,0x70},
277 {SOS21_C4_H,0x01},
278 {_END_OF_TBL_,0x00},
279 };
280 MS_VIF_REG_TYPE VIF_GDE_PEAKING_2dB[]=
281 {
282 {SOS21_C0_L,0xa4}, // SOS21 peaking
283 {SOS21_C0_H,0x02},
284 {SOS21_C1_L,0x8e},
285 {SOS21_C1_H,0x06},
286 {SOS21_C2_L,0x12},
287 {SOS21_C2_H,0x02},
288 {SOS21_C3_L,0x5c},
289 {SOS21_C3_H,0x05},
290 {SOS21_C4_L,0x60},
291 {SOS21_C4_H,0x01},
292 {_END_OF_TBL_,0x00},
293 };
294 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB[]=
295 {
296 {SOS21_C0_L,0xc1}, // SOS21 peaking
297 {SOS21_C0_H,0x02},
298 {SOS21_C1_L,0x87},
299 {SOS21_C1_H,0x06},
300 {SOS21_C2_L,0x1c},
301 {SOS21_C2_H,0x02},
302 {SOS21_C3_L,0x3f},
303 {SOS21_C3_H,0x05},
304 {SOS21_C4_L,0x5d},
305 {SOS21_C4_H,0x01},
306 {_END_OF_TBL_,0x00},
307 };
308 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB[]=
309 {
310 {SOS21_C0_L,0xc1}, // SOS21 peaking
311 {SOS21_C0_H,0x02},
312 {SOS21_C1_L,0x87},
313 {SOS21_C1_H,0x06},
314 {SOS21_C2_L,0x28},
315 {SOS21_C2_H,0x02},
316 {SOS21_C3_L,0x3f},
317 {SOS21_C3_H,0x05},
318 {SOS21_C4_L,0x51},
319 {SOS21_C4_H,0x01},
320 {_END_OF_TBL_,0x00},
321 };
322 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB_VSB[]=
323 {
324 {SOS21_C0_L,0xf5}, // SOS21 peaking
325 {SOS21_C0_H,0x02},
326 {SOS21_C1_L,0x23},
327 {SOS21_C1_H,0x06},
328 {SOS21_C2_L,0x07},
329 {SOS21_C2_H,0x02},
330 {SOS21_C3_L,0x0b},
331 {SOS21_C3_H,0x05},
332 {SOS21_C4_L,0xd5},
333 {SOS21_C4_H,0x01},
334 {_END_OF_TBL_,0x00},
335 };
336 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB_VSB[]=
337 {
338 {SOS21_C0_L,0xf5}, // SOS21 peaking
339 {SOS21_C0_H,0x02},
340 {SOS21_C1_L,0x23},
341 {SOS21_C1_H,0x06},
342 {SOS21_C2_L,0x0a},
343 {SOS21_C2_H,0x02},
344 {SOS21_C3_L,0x0b},
345 {SOS21_C3_H,0x05},
346 {SOS21_C4_L,0xd2},
347 {SOS21_C4_H,0x01},
348 {_END_OF_TBL_,0x00},
349 };
350 MS_VIF_REG_TYPE VIF_GDE_PEAKING_5dB_VSB[]=
351 {
352 {SOS21_C0_L,0xf5}, // SOS21 peaking
353 {SOS21_C0_H,0x02},
354 {SOS21_C1_L,0x23},
355 {SOS21_C1_H,0x06},
356 {SOS21_C2_L,0x0e},
357 {SOS21_C2_H,0x02},
358 {SOS21_C3_L,0x0b},
359 {SOS21_C3_H,0x05},
360 {SOS21_C4_L,0xcf},
361 {SOS21_C4_H,0x01},
362 {_END_OF_TBL_,0x00},
363 };
364 MS_VIF_REG_TYPE VIF_GDE_PEAKING_NULL[]=
365 {
366 {SOS21_C0_L,0x00}, // SOS21
367 {SOS21_C0_H,0x00},
368 {SOS21_C1_L,0x00},
369 {SOS21_C1_H,0x00},
370 {SOS21_C2_L,0x00},
371 {SOS21_C2_H,0x00},
372 {SOS21_C3_L,0x00},
373 {SOS21_C3_H,0x00},
374 {SOS21_C4_L,0x00},
375 {SOS21_C4_H,0x02},
376 {_END_OF_TBL_,0x00},
377 };
378 MS_VIF_REG_TYPE VIF_GDE_YCDelay_VSB[]=
379 {
380 {SOS22_C0_L,0x15}, // SOS22 Y/C delay
381 {SOS22_C0_H,0x02},
382 {SOS22_C1_L,0x84},
383 {SOS22_C1_H,0x06},
384 {SOS22_C2_L,0x7c},
385 {SOS22_C2_H,0x01},
386 {SOS22_C3_L,0xeb},
387 {SOS22_C3_H,0x05},
388 {SOS22_C4_L,0x00},
389 {SOS22_C4_H,0x02},
390 {_END_OF_TBL_,0x00},
391 };
392 MS_VIF_REG_TYPE VIF_GDE_YCDelay_NULL[]=
393 {
394 {SOS22_C0_L,0x00}, // SOS22
395 {SOS22_C0_H,0x00},
396 {SOS22_C1_L,0x00},
397 {SOS22_C1_H,0x00},
398 {SOS22_C2_L,0x00},
399 {SOS22_C2_H,0x00},
400 {SOS22_C3_L,0x00},
401 {SOS22_C3_H,0x00},
402 {SOS22_C4_L,0x00},
403 {SOS22_C4_H,0x02},
404 {_END_OF_TBL_,0x00},
405 };
406 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_R[]=
407 {
408 {SOS31_C0_L,0xcc}, // SOS31
409 {SOS31_C0_H,0x00},
410 {SOS31_C1_L,0x6c},
411 {SOS31_C1_H,0x07},
412 {SOS31_C2_L,0x94},
413 {SOS31_C2_H,0x00},
414 {SOS31_C3_L,0x34},
415 {SOS31_C3_H,0x07},
416 {SOS31_C4_L,0x00},
417 {SOS31_C4_H,0x02},
418 {SOS32_C0_L,0xb4}, // SOS32
419 {SOS32_C0_H,0x02},
420 {SOS32_C1_L,0xf8},
421 {SOS32_C1_H,0x06},
422 {SOS32_C2_L,0x08},
423 {SOS32_C2_H,0x01},
424 {SOS32_C3_L,0x4c},
425 {SOS32_C3_H,0x05},
426 {SOS32_C4_L,0x00},
427 {SOS32_C4_H,0x02},
428 {_END_OF_TBL_,0x00},
429 };
430 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_L[]=
431 {
432 {SOS31_C0_L,0x3c}, // SOS31
433 {SOS31_C0_H,0x02},
434 {SOS31_C1_L,0xb8},
435 {SOS31_C1_H,0x06},
436 {SOS31_C2_L,0x48},
437 {SOS31_C2_H,0x01},
438 {SOS31_C3_L,0xc4},
439 {SOS31_C3_H,0x05},
440 {SOS31_C4_L,0x00},
441 {SOS31_C4_H,0x02},
442 {SOS32_C0_L,0xd9}, // SOS32
443 {SOS32_C0_H,0x02},
444 {SOS32_C1_L,0xf7},
445 {SOS32_C1_H,0x06},
446 {SOS32_C2_L,0x0a},
447 {SOS32_C2_H,0x01},
448 {SOS32_C3_L,0x28},
449 {SOS32_C3_H,0x05},
450 {SOS32_C4_L,0x00},
451 {SOS32_C4_H,0x02},
452 {_END_OF_TBL_,0x00},
453 };
454 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_R[]=
455 {
456 {SOS31_C0_L,0xcc}, // SOS31
457 {SOS31_C0_H,0x00},
458 {SOS31_C1_L,0x6c},
459 {SOS31_C1_H,0x07},
460 {SOS31_C2_L,0x94},
461 {SOS31_C2_H,0x00},
462 {SOS31_C3_L,0x34},
463 {SOS31_C3_H,0x07},
464 {SOS31_C4_L,0x00},
465 {SOS31_C4_H,0x02},
466 {SOS32_C0_L,0xc7}, // SOS32
467 {SOS32_C0_H,0x02},
468 {SOS32_C1_L,0xd8},
469 {SOS32_C1_H,0x06},
470 {SOS32_C2_L,0x28},
471 {SOS32_C2_H,0x01},
472 {SOS32_C3_L,0x39},
473 {SOS32_C3_H,0x05},
474 {SOS32_C4_L,0x00},
475 {SOS32_C4_H,0x02},
476 {_END_OF_TBL_,0x00},
477 };
478 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_L[]=
479 {
480 {SOS31_C0_L,0xcc}, // SOS31
481 {SOS31_C0_H,0x00},
482 {SOS31_C1_L,0x6c},
483 {SOS31_C1_H,0x07},
484 {SOS31_C2_L,0x94},
485 {SOS31_C2_H,0x00},
486 {SOS31_C3_L,0x34},
487 {SOS31_C3_H,0x07},
488 {SOS31_C4_L,0x00},
489 {SOS31_C4_H,0x02},
490 {SOS32_C0_L,0xb0}, // SOS32
491 {SOS32_C0_H,0x02},
492 {SOS32_C1_L,0x13},
493 {SOS32_C1_H,0x07},
494 {SOS32_C2_L,0xed},
495 {SOS32_C2_H,0x00},
496 {SOS32_C3_L,0x50},
497 {SOS32_C3_H,0x05},
498 {SOS32_C4_L,0x00},
499 {SOS32_C4_H,0x02},
500 {_END_OF_TBL_,0x00},
501 };
502 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_LG[]=
503 {
504 {SOS31_C0_L,0xab}, // SOS31
505 {SOS31_C0_H,0x02},
506 {SOS31_C1_L,0x9b},
507 {SOS31_C1_H,0x06},
508 {SOS31_C2_L,0x65},
509 {SOS31_C2_H,0x01},
510 {SOS31_C3_L,0x55},
511 {SOS31_C3_H,0x05},
512 {SOS31_C4_L,0x00},
513 {SOS31_C4_H,0x02},
514 {SOS32_C0_L,0xe1}, // SOS32
515 {SOS32_C0_H,0x02},
516 {SOS32_C1_L,0xf7},
517 {SOS32_C1_H,0x06},
518 {SOS32_C2_L,0x0a},
519 {SOS32_C2_H,0x01},
520 {SOS32_C3_L,0x1f},
521 {SOS32_C3_H,0x05},
522 {SOS32_C4_L,0x00},
523 {SOS32_C4_H,0x02},
524 {_END_OF_TBL_,0x00},
525 };
526 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_Philips[]=
527 {
528 {SOS31_C0_L,0x9f}, // SOS31
529 {SOS31_C0_H,0x02},
530 {SOS31_C1_L,0xa8},
531 {SOS31_C1_H,0x06},
532 {SOS31_C2_L,0x58},
533 {SOS31_C2_H,0x01},
534 {SOS31_C3_L,0x62},
535 {SOS31_C3_H,0x05},
536 {SOS31_C4_L,0x00},
537 {SOS31_C4_H,0x02},
538 {SOS32_C0_L,0xcd}, // SOS32
539 {SOS32_C0_H,0x02},
540 {SOS32_C1_L,0x05},
541 {SOS32_C1_H,0x07},
542 {SOS32_C2_L,0xfb},
543 {SOS32_C2_H,0x00},
544 {SOS32_C3_L,0x33},
545 {SOS32_C3_H,0x05},
546 {SOS32_C4_L,0x00},
547 {SOS32_C4_H,0x02},
548 {_END_OF_TBL_,0x00},
549 };
550 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_NULL[]=
551 {
552 {SOS31_C0_L,0x00}, // SOS31
553 {SOS31_C0_H,0x00},
554 {SOS31_C1_L,0x00},
555 {SOS31_C1_H,0x00},
556 {SOS31_C2_L,0x00},
557 {SOS31_C2_H,0x00},
558 {SOS31_C3_L,0x00},
559 {SOS31_C3_H,0x00},
560 {SOS31_C4_L,0x00},
561 {SOS31_C4_H,0x02},
562 {SOS32_C0_L,0x00}, // SOS32
563 {SOS32_C0_H,0x00},
564 {SOS32_C1_L,0x00},
565 {SOS32_C1_H,0x00},
566 {SOS32_C2_L,0x00},
567 {SOS32_C2_H,0x00},
568 {SOS32_C3_L,0x00},
569 {SOS32_C3_H,0x00},
570 {SOS32_C4_L,0x00},
571 {SOS32_C4_H,0x02},
572 {_END_OF_TBL_,0x00},
573 };
574 MS_VIF_REG_TYPE VIF_PAL_B_A2[]=
575 {
576 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
577 {N_A1_C0_H,0x02},
578 {N_A1_C1_L,0x3c},
579 {N_A1_C1_H,0x06},
580 {N_A1_C2_L,0x37},
581 {N_A1_C2_H,0x05},
582 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
583 {N_A2_C0_H,0x02},
584 {N_A2_C1_L,0x3c},
585 {N_A2_C1_H,0x06},
586 {N_A2_C2_L,0x51},
587 {N_A2_C2_H,0x05},
588 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
589 {SOS12_C0_H,0x02},
590 {SOS12_C1_L,0x3c},
591 {SOS12_C1_H,0x06},
592 {SOS12_C2_L,0x00},
593 {SOS12_C2_H,0x02},
594 {SOS12_C3_L,0x37},
595 {SOS12_C3_H,0x05},
596 {SOS12_C4_L,0x00},
597 {SOS12_C4_H,0x02},
598 {_END_OF_TBL_,0x00}, // PAL B/G A2
599 };
600 MS_VIF_REG_TYPE VIF_PAL_B_NICAM[]=
601 {
602 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
603 {N_A1_C0_H,0x02},
604 {N_A1_C1_L,0x3c},
605 {N_A1_C1_H,0x06},
606 {N_A1_C2_L,0x37},
607 {N_A1_C2_H,0x05},
608 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
609 {N_A2_C0_H,0x02},
610 {N_A2_C1_L,0x3c},
611 {N_A2_C1_H,0x06},
612 {N_A2_C2_L,0x5d},
613 {N_A2_C2_H,0x05},
614 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
615 {SOS12_C0_H,0x02},
616 {SOS12_C1_L,0x3c},
617 {SOS12_C1_H,0x06},
618 {SOS12_C2_L,0x00},
619 {SOS12_C2_H,0x02},
620 {SOS12_C3_L,0x37},
621 {SOS12_C3_H,0x05},
622 {SOS12_C4_L,0x00},
623 {SOS12_C4_H,0x02},
624 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
625 };
626 MS_VIF_REG_TYPE VIF_PAL_GH_A2[]=
627 {
628 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
629 {N_A1_C0_H,0x02},
630 {N_A1_C1_L,0x3c},
631 {N_A1_C1_H,0x06},
632 {N_A1_C2_L,0x37},
633 {N_A1_C2_H,0x05},
634 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
635 {N_A2_C0_H,0x02},
636 {N_A2_C1_L,0x3c},
637 {N_A2_C1_H,0x06},
638 {N_A2_C2_L,0x51},
639 {N_A2_C2_H,0x05},
640 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
641 {SOS12_C0_H,0x02},
642 {SOS12_C1_L,0x3c},
643 {SOS12_C1_H,0x06},
644 {SOS12_C2_L,0x00},
645 {SOS12_C2_H,0x02},
646 {SOS12_C3_L,0x37},
647 {SOS12_C3_H,0x05},
648 {SOS12_C4_L,0x00},
649 {SOS12_C4_H,0x02},
650 {_END_OF_TBL_,0x00}, // PAL B/G A2
651 };
652 MS_VIF_REG_TYPE VIF_PAL_GH_NICAM[]=
653 {
654 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
655 {N_A1_C0_H,0x02},
656 {N_A1_C1_L,0x3c},
657 {N_A1_C1_H,0x06},
658 {N_A1_C2_L,0x37},
659 {N_A1_C2_H,0x05},
660 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
661 {N_A2_C0_H,0x02},
662 {N_A2_C1_L,0x3c},
663 {N_A2_C1_H,0x06},
664 {N_A2_C2_L,0x5d},
665 {N_A2_C2_H,0x05},
666 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
667 {SOS12_C0_H,0x02},
668 {SOS12_C1_L,0x3c},
669 {SOS12_C1_H,0x06},
670 {SOS12_C2_L,0x00},
671 {SOS12_C2_H,0x02},
672 {SOS12_C3_L,0x37},
673 {SOS12_C3_H,0x05},
674 {SOS12_C4_L,0x00},
675 {SOS12_C4_H,0x02},
676 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
677 };
678 MS_VIF_REG_TYPE VIF_SECAM_L_NICAM[]=
679 {
680 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
681 {N_A1_C0_H,0x02},
682 {N_A1_C1_L,0x3c},
683 {N_A1_C1_H,0x06},
684 {N_A1_C2_L,0xa9},
685 {N_A1_C2_H,0x05},
686 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
687 {N_A2_C0_H,0x02},
688 {N_A2_C1_L,0x3c},
689 {N_A2_C1_H,0x06},
690 {N_A2_C2_L,0x5d},
691 {N_A2_C2_H,0x05},
692 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
693 {SOS12_C0_H,0x02},
694 {SOS12_C1_L,0x3c},
695 {SOS12_C1_H,0x06},
696 {SOS12_C2_L,0x00},
697 {SOS12_C2_H,0x02},
698 {SOS12_C3_L,0xa9},
699 {SOS12_C3_H,0x05},
700 {SOS12_C4_L,0x00},
701 {SOS12_C4_H,0x02},
702 {_END_OF_TBL_,0x00}, // SECAM L NICAM
703 };
704
705 MS_VIF_REG_TYPE VIF_PAL_I_NICAM[]=
706 {
707 {N_A1_C0_L,0x6b}, // Notch_A1, R = 0.94
708 {N_A1_C0_H,0x02},
709 {N_A1_C1_L,0x3c},
710 {N_A1_C1_H,0x06},
711 {N_A1_C2_L,0x6e},
712 {N_A1_C2_H,0x05},
713 {N_A2_C0_L,0x2e}, // Notch_A2, R = 0.94
714 {N_A2_C0_H,0x02},
715 {N_A2_C1_L,0x3c},
716 {N_A2_C1_H,0x06},
717 {N_A2_C2_L,0xaf},
718 {N_A2_C2_H,0x05},
719 {SOS12_C0_L,0x6b}, // SOS12, R = 0.94
720 {SOS12_C0_H,0x02},
721 {SOS12_C1_L,0x3c},
722 {SOS12_C1_H,0x06},
723 {SOS12_C2_L,0x00},
724 {SOS12_C2_H,0x02},
725 {SOS12_C3_L,0x6e},
726 {SOS12_C3_H,0x05},
727 {SOS12_C4_L,0x00},
728 {SOS12_C4_H,0x02},
729 {_END_OF_TBL_,0x00}, // PAL I NICAM
730 };
731
732 MS_VIF_REG_TYPE VIF_SECAM_DK1_A2[]=
733 {
734 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
735 {N_A1_C0_H,0x02},
736 {N_A1_C1_L,0x3c},
737 {N_A1_C1_H,0x06},
738 {N_A1_C2_L,0xa9},
739 {N_A1_C2_H,0x05},
740 {N_A2_C0_L,0x4f}, // Notch_A2, R = 0.94
741 {N_A2_C0_H,0x02},
742 {N_A2_C1_L,0x3c},
743 {N_A2_C1_H,0x06},
744 {N_A2_C2_L,0x8c},
745 {N_A2_C2_H,0x05},
746 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
747 {SOS12_C0_H,0x02},
748 {SOS12_C1_L,0x3c},
749 {SOS12_C1_H,0x06},
750 {SOS12_C2_L,0x00},
751 {SOS12_C2_H,0x02},
752 {SOS12_C3_L,0xa9},
753 {SOS12_C3_H,0x05},
754 {SOS12_C4_L,0x00},
755 {SOS12_C4_H,0x02},
756 {_END_OF_TBL_,0x00}, // PAL DK1 A2
757 };
758
759 MS_VIF_REG_TYPE VIF_PAL_DK2_A2[]=
760 {
761 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
762 {N_A1_C0_H,0x02},
763 {N_A1_C1_L,0x3c},
764 {N_A1_C1_H,0x06},
765 {N_A1_C2_L,0xa9},
766 {N_A1_C2_H,0x05},
767 {N_A2_C0_L,0x18}, // Notch_A2, R = 0.94
768 {N_A2_C0_H,0x02},
769 {N_A2_C1_L,0x3c},
770 {N_A2_C1_H,0x06},
771 {N_A2_C2_L,0xc6},
772 {N_A2_C2_H,0x05},
773 {SOS12_C0_L,0x34}, // SOS12, R = 0.96
774 {SOS12_C0_H,0x02},
775 {SOS12_C1_L,0x3c},
776 {SOS12_C1_H,0x06},
777 {SOS12_C2_L,0x00},
778 {SOS12_C2_H,0x02},
779 {SOS12_C3_L,0xa9},
780 {SOS12_C3_H,0x05},
781 {SOS12_C4_L,0x00},
782 {SOS12_C4_H,0x02},
783 {_END_OF_TBL_,0x00}, // PAL DK2 A2
784 };
785
786 MS_VIF_REG_TYPE VIF_PAL_DK2_NICAM[]=
787 {
788 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
789 {N_A1_C0_H,0x02},
790 {N_A1_C1_L,0x3c},
791 {N_A1_C1_H,0x06},
792 {N_A1_C2_L,0xa9},
793 {N_A1_C2_H,0x05},
794 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
795 {N_A2_C0_H,0x02},
796 {N_A2_C1_L,0x3c},
797 {N_A2_C1_H,0x06},
798 {N_A2_C2_L,0x5d},
799 {N_A2_C2_H,0x05},
800 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
801 {SOS12_C0_H,0x02},
802 {SOS12_C1_L,0x3c},
803 {SOS12_C1_H,0x06},
804 {SOS12_C2_L,0x00},
805 {SOS12_C2_H,0x02},
806 {SOS12_C3_L,0xa9},
807 {SOS12_C3_H,0x05},
808 {SOS12_C4_L,0x00},
809 {SOS12_C4_H,0x02},
810 {_END_OF_TBL_,0x00}, // PAL DK NICAM
811 };
812
813 MS_VIF_REG_TYPE VIF_SECAM_DK3_A2[]=
814 {
815 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
816 {N_A1_C0_H,0x02},
817 {N_A1_C1_L,0x3c},
818 {N_A1_C1_H,0x06},
819 {N_A1_C2_L,0xa9},
820 {N_A1_C2_H,0x05},
821 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
822 {N_A2_C0_H,0x02},
823 {N_A2_C1_L,0x3c},
824 {N_A2_C1_H,0x06},
825 {N_A2_C2_L,0x51},
826 {N_A2_C2_H,0x05},
827 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
828 {SOS12_C0_H,0x02},
829 {SOS12_C1_L,0x3c},
830 {SOS12_C1_H,0x06},
831 {SOS12_C2_L,0x00},
832 {SOS12_C2_H,0x02},
833 {SOS12_C3_L,0xa9},
834 {SOS12_C3_H,0x05},
835 {SOS12_C4_L,0x00},
836 {SOS12_C4_H,0x02},
837 {_END_OF_TBL_,0x00}, // PAL DK3 A2
838 };
839
840 MS_VIF_REG_TYPE VIF_GDE_BG_A2_NOTCH[]=
841 {
842 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
843 {N_A3_C0_H,0x02},
844 {N_A3_C1_L,0x3c},
845 {N_A3_C1_H,0x06},
846 {N_A3_C2_L,0x37},
847 {N_A3_C2_H,0x05},
848 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
849 {N_A4_C0_H,0x02},
850 {N_A4_C1_L,0x3c},
851 {N_A4_C1_H,0x06},
852 {N_A4_C2_L,0x51},
853 {N_A4_C2_H,0x05},
854 {N_A5_C0_L,0xad}, // Notch_A5, R = 0.96
855 {N_A5_C0_H,0x02},
856 {N_A5_C1_L,0x28},
857 {N_A5_C1_H,0x06},
858 {N_A5_C2_L,0x37},
859 {N_A5_C2_H,0x05},
860 {_END_OF_TBL_,0x00}, // PAL B/G A2
861 };
862
863 MS_VIF_REG_TYPE VIF_GDE_BG_NICAM_NOTCH[]=
864 {
865 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
866 {N_A3_C0_H,0x02},
867 {N_A3_C1_L,0x3c},
868 {N_A3_C1_H,0x06},
869 {N_A3_C2_L,0x37},
870 {N_A3_C2_H,0x05},
871 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
872 {N_A4_C0_H,0x02},
873 {N_A4_C1_L,0x3c},
874 {N_A4_C1_H,0x06},
875 {N_A4_C2_L,0x5d},
876 {N_A4_C2_H,0x05},
877 {N_A5_C0_L,0xad}, // Notch_A5, R = 0.96
878 {N_A5_C0_H,0x02},
879 {N_A5_C1_L,0x28},
880 {N_A5_C1_H,0x06},
881 {N_A5_C2_L,0x37},
882 {N_A5_C2_H,0x05},
883 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
884 };
885
886 MS_VIF_REG_TYPE VIF_GDE_I_NOTCH[]=
887 {
888 {N_A3_C0_L,0x6b}, // Notch_A3, R = 0.94
889 {N_A3_C0_H,0x02},
890 {N_A3_C1_L,0x3c},
891 {N_A3_C1_H,0x06},
892 {N_A3_C2_L,0x6e},
893 {N_A3_C2_H,0x05},
894 {N_A4_C0_L,0x2e}, // Notch_A4, R = 0.94
895 {N_A4_C0_H,0x02},
896 {N_A4_C1_L,0x3c},
897 {N_A4_C1_H,0x06},
898 {N_A4_C2_L,0xaf},
899 {N_A4_C2_H,0x05},
900 {N_A5_C0_L,0x78}, // Notch_A5, R = 0.96
901 {N_A5_C0_H,0x02},
902 {N_A5_C1_L,0x28},
903 {N_A5_C1_H,0x06},
904 {N_A5_C2_L,0x6e},
905 {N_A5_C2_H,0x05},
906 {_END_OF_TBL_,0x00}, // PAL I NICAM
907 };
908
909 MS_VIF_REG_TYPE VIF_GDE_DK1_NOTCH[]=
910 {
911 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
912 {N_A3_C0_H,0x02},
913 {N_A3_C1_L,0x3c},
914 {N_A3_C1_H,0x06},
915 {N_A3_C2_L,0xa9},
916 {N_A3_C2_H,0x05},
917 {N_A4_C0_L,0x4f}, // Notch_A4, R = 0.94
918 {N_A4_C0_H,0x02},
919 {N_A4_C1_L,0x3c},
920 {N_A4_C1_H,0x06},
921 {N_A4_C2_L,0x8c},
922 {N_A4_C2_H,0x05},
923 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
924 {N_A5_C0_H,0x02},
925 {N_A5_C1_L,0x28},
926 {N_A5_C1_H,0x06},
927 {N_A5_C2_L,0xa9},
928 {N_A5_C2_H,0x05},
929 {_END_OF_TBL_,0x00}, // PAL DK1 A2
930 };
931
932 MS_VIF_REG_TYPE VIF_GDE_DK2_NOTCH[]=
933 {
934 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
935 {N_A3_C0_H,0x02},
936 {N_A3_C1_L,0x3c},
937 {N_A3_C1_H,0x06},
938 {N_A3_C2_L,0xa9},
939 {N_A3_C2_H,0x05},
940 {N_A4_C0_L,0x18}, // Notch_A4, R = 0.94
941 {N_A4_C0_H,0x02},
942 {N_A4_C1_L,0x3c},
943 {N_A4_C1_H,0x06},
944 {N_A4_C2_L,0xc6},
945 {N_A4_C2_H,0x05},
946 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
947 {N_A5_C0_H,0x02},
948 {N_A5_C1_L,0x28},
949 {N_A5_C1_H,0x06},
950 {N_A5_C2_L,0xa9},
951 {N_A5_C2_H,0x05},
952 {_END_OF_TBL_,0x00}, // PAL DK2 A2
953 };
954
955 MS_VIF_REG_TYPE VIF_GDE_DK3_NOTCH[]=
956 {
957 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
958 {N_A3_C0_H,0x02},
959 {N_A3_C1_L,0x3c},
960 {N_A3_C1_H,0x06},
961 {N_A3_C2_L,0xa9},
962 {N_A3_C2_H,0x05},
963 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
964 {N_A4_C0_H,0x02},
965 {N_A4_C1_L,0x3c},
966 {N_A4_C1_H,0x06},
967 {N_A4_C2_L,0x51},
968 {N_A4_C2_H,0x05},
969 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
970 {N_A5_C0_H,0x02},
971 {N_A5_C1_L,0x28},
972 {N_A5_C1_H,0x06},
973 {N_A5_C2_L,0xa9},
974 {N_A5_C2_H,0x05},
975 {_END_OF_TBL_,0x00}, // PAL DK3 A2
976 };
977
978 MS_VIF_REG_TYPE VIF_GDE_DK_NICAM_NOTCH[]=
979 {
980 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
981 {N_A3_C0_H,0x02},
982 {N_A3_C1_L,0x3c},
983 {N_A3_C1_H,0x06},
984 {N_A3_C2_L,0xa9},
985 {N_A3_C2_H,0x05},
986 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
987 {N_A4_C0_H,0x02},
988 {N_A4_C1_L,0x3c},
989 {N_A4_C1_H,0x06},
990 {N_A4_C2_L,0x5d},
991 {N_A4_C2_H,0x05},
992 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
993 {N_A5_C0_H,0x02},
994 {N_A5_C1_L,0x28},
995 {N_A5_C1_H,0x06},
996 {N_A5_C2_L,0xa9},
997 {N_A5_C2_H,0x05},
998 {_END_OF_TBL_,0x00}, // PAL DK NICAM
999 };
1000
1001 MS_VIF_REG_TYPE VIF_GDE_L_NICAM_NOTCH[]=
1002 {
1003 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
1004 {N_A3_C0_H,0x02},
1005 {N_A3_C1_L,0x3c},
1006 {N_A3_C1_H,0x06},
1007 {N_A3_C2_L,0xa9},
1008 {N_A3_C2_H,0x05},
1009 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
1010 {N_A4_C0_H,0x02},
1011 {N_A4_C1_L,0x3c},
1012 {N_A4_C1_H,0x06},
1013 {N_A4_C2_L,0x5d},
1014 {N_A4_C2_H,0x05},
1015 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
1016 {N_A5_C0_H,0x02},
1017 {N_A5_C1_L,0x28},
1018 {N_A5_C1_H,0x06},
1019 {N_A5_C2_L,0xa9},
1020 {N_A5_C2_H,0x05},
1021 {_END_OF_TBL_,0x00}, // SECAM L NICAM
1022 };
1023
1024 MS_VIF_REG_TYPE VIF_GDE_MN_NOTCH[]=
1025 {
1026 {N_A3_C0_L,0x1c}, // Notch_A3 (0.98)
1027 {N_A3_C0_H,0x03},
1028 {N_A3_C1_L,0x14},
1029 {N_A3_C1_H,0x06},
1030 {N_A3_C2_L,0xd4},
1031 {N_A3_C2_H,0x04},
1032 {N_A4_C0_L,0xe8}, // Notch_A4, R = 0.94
1033 {N_A4_C0_H,0x02},
1034 {N_A4_C1_L,0x3c},
1035 {N_A4_C1_H,0x06},
1036 {N_A4_C2_L,0xe8},
1037 {N_A4_C2_H,0x04},
1038 {N_A5_C0_L,0x0c}, // Notch_A5, R = 0.96
1039 {N_A5_C0_H,0x03},
1040 {N_A5_C1_L,0x28},
1041 {N_A5_C1_H,0x06},
1042 {N_A5_C2_L,0xd4},
1043 {N_A5_C2_H,0x04},
1044 {_END_OF_TBL_,0x00}, // NTSC M/N
1045 };
1046 MS_VIF_REG_TYPE VIF_NTSC_MN_A2[]=
1047 {
1048 {N_A1_C0_L,0xfc}, // Notch_A1, R = 0.94
1049 {N_A1_C0_H,0x02},
1050 {N_A1_C1_L,0x3c},
1051 {N_A1_C1_H,0x06},
1052 {N_A1_C2_L,0xd4},
1053 {N_A1_C2_H,0x04},
1054 {N_A2_C0_L,0xe8}, // Notch_A2, R = 0.94
1055 {N_A2_C0_H,0x02},
1056 {N_A2_C1_L,0x3c},
1057 {N_A2_C1_H,0x06},
1058 {N_A2_C2_L,0xe8},
1059 {N_A2_C2_H,0x04},
1060 {SOS12_C0_L,0xfc}, // SOS12, R = 0.94
1061 {SOS12_C0_H,0x02},
1062 {SOS12_C1_L,0x3c},
1063 {SOS12_C1_H,0x06},
1064 {SOS12_C2_L,0x00},
1065 {SOS12_C2_H,0x02},
1066 {SOS12_C3_L,0xd4},
1067 {SOS12_C3_H,0x04},
1068 {SOS12_C4_L,0x00},
1069 {SOS12_C4_H,0x02},
1070 {_END_OF_TBL_,0x00}, // NTSC M/N
1071 };
1072 MS_VIF_REG_TYPE VIF_PAL_DK_LOWER_ACI[]=
1073 {
1074 {SOS11_C0_L,0x3a}, // SOS11 notch at 16.5MHz (0.94)
1075 {SOS11_C0_H,0x05},
1076 {SOS11_C1_L,0x3c},
1077 {SOS11_C1_H,0x06},
1078 {SOS11_C2_L,0x00},
1079 {SOS11_C2_H,0x02},
1080 {SOS11_C3_L,0xf3},
1081 {SOS11_C3_H,0x02},
1082 {SOS11_C4_L,0x00},
1083 {SOS11_C4_H,0x02},
1084 {_END_OF_TBL_,0x00},
1085 };
1086 MS_VIF_REG_TYPE VIF_PAL_I_LOWER_ACI[]=
1087 {
1088 {SOS11_C0_L,0x0d}, // SOS11 notch at 17MHz (0.94)
1089 {SOS11_C0_H,0x05},
1090 {SOS11_C1_L,0x3c},
1091 {SOS11_C1_H,0x06},
1092 {SOS11_C2_L,0x00},
1093 {SOS11_C2_H,0x02},
1094 {SOS11_C3_L,0x23},
1095 {SOS11_C3_H,0x03},
1096 {SOS11_C4_L,0x00},
1097 {SOS11_C4_H,0x02},
1098 {_END_OF_TBL_,0x00},
1099 };
1100 MS_VIF_REG_TYPE VIF_PAL_GH_LOWER_ACI[]=
1101 {
1102 {SOS11_C0_L,0xe4}, // SOS11 notch at 17.5MHz (0.94)
1103 {SOS11_C0_H,0x04},
1104 {SOS11_C1_L,0x3c},
1105 {SOS11_C1_H,0x06},
1106 {SOS11_C2_L,0x00},
1107 {SOS11_C2_H,0x02},
1108 {SOS11_C3_L,0x4f},
1109 {SOS11_C3_H,0x03},
1110 {SOS11_C4_L,0x00},
1111 {SOS11_C4_H,0x02},
1112 {_END_OF_TBL_,0x00},
1113 };
1114 MS_VIF_REG_TYPE VIF_PAL_B_LOWER_ACI[]=
1115 {
1116 {SOS11_C0_L,0x1C}, // SOS11 notch at 16.5MHz (0.98)
1117 {SOS11_C0_H,0x05},
1118 {SOS11_C1_L,0x14},
1119 {SOS11_C1_H,0x06},
1120 {SOS11_C2_L,0x00},
1121 {SOS11_C2_H,0x02},
1122 {SOS11_C3_L,0xF3},
1123 {SOS11_C3_H,0x02},
1124 {SOS11_C4_L,0x00},
1125 {SOS11_C4_H,0x02},
1126 {_END_OF_TBL_,0x00},
1127 };
1128
1129 MS_VIF_REG_TYPE VIF_NTSC_MN_LOWER_ACI[]=
1130 {
1131 {SOS11_C0_L,0x15}, // SOS11 notch at 16.5MHz
1132 {SOS11_C0_H,0x05},
1133 {SOS11_C1_L,0x0A},
1134 {SOS11_C1_H,0x06},
1135 {SOS11_C2_L,0x00},
1136 {SOS11_C2_H,0x02},
1137 {SOS11_C3_L,0xF3},
1138 {SOS11_C3_H,0x02},
1139 {SOS11_C4_L,0x00},
1140 {SOS11_C4_H,0x02},
1141 {_END_OF_TBL_,0x00},
1142 };
1143 MS_VIF_REG_TYPE VIF_PAL_DK_Audio_SingleSAW[]=
1144 {
1145 {SOS12_C0_L,0x0D}, // SOS12 notch at 8.5MHz
1146 {SOS12_C0_H,0x01},
1147 {SOS12_C1_L,0xB8},
1148 {SOS12_C1_H,0x06},
1149 {SOS12_C2_L,0x00},
1150 {SOS12_C2_H,0x02},
1151 {SOS12_C3_L,0xB0},
1152 {SOS12_C3_H,0x06},
1153 {SOS12_C4_L,0x00},
1154 {SOS12_C4_H,0x02},
1155 {_END_OF_TBL_,0x00},
1156 };
1157 MS_VIF_REG_TYPE VIF_PAL_GH_Audio_SingleSAW[]=
1158 {
1159 {SOS12_C0_L,0x9A}, // SOS12 notch at 9.5MHz
1160 {SOS12_C0_H,0x00},
1161 {SOS12_C1_L,0xB8},
1162 {SOS12_C1_H,0x06},
1163 {SOS12_C2_L,0x00},
1164 {SOS12_C2_H,0x02},
1165 {SOS12_C3_L,0x40},
1166 {SOS12_C3_H,0x07},
1167 {SOS12_C4_L,0x00},
1168 {SOS12_C4_H,0x02},
1169 {_END_OF_TBL_,0x00},
1170 };
1171 MS_VIF_REG_TYPE VIF_PAL_I_Audio_SingleSAW[]=
1172 {
1173 {SOS12_C0_L,0xD4}, // SOS12 notch at 9MHz
1174 {SOS12_C0_H,0x00},
1175 {SOS12_C1_L,0xB8},
1176 {SOS12_C1_H,0x06},
1177 {SOS12_C2_L,0x00},
1178 {SOS12_C2_H,0x02},
1179 {SOS12_C3_L,0xF7},
1180 {SOS12_C3_H,0x06},
1181 {SOS12_C4_L,0x00},
1182 {SOS12_C4_H,0x02},
1183 {_END_OF_TBL_,0x00},
1184 };
1185
1186 MS_VIF_REG_TYPE VIF_NULL_LOWER_ACI[]=
1187 {
1188 {SOS11_C0_L,0x00}, // SOS11
1189 {SOS11_C0_H,0x00},
1190 {SOS11_C1_L,0x00},
1191 {SOS11_C1_H,0x00},
1192 {SOS11_C2_L,0x00},
1193 {SOS11_C2_H,0x00},
1194 {SOS11_C3_L,0x00},
1195 {SOS11_C3_H,0x00},
1196 {SOS11_C4_L,0x00},
1197 {SOS11_C4_H,0x02},
1198 {_END_OF_TBL_,0x00},
1199 };
1200
1201 MS_VIF_REG_TYPE VIF_CR_IIR_LPF1_OLD[]=
1202 {
1203 {CR_IIR_COEF_G,0x02},
1204 {CR_IIR_COEF_G+1,0x00},
1205 {CR_IIR_COEF_A1,0xfc},
1206 {CR_IIR_COEF_A1+1,0x01},
1207 {CR_IIR_COEF_A2,0x00},
1208 {CR_IIR_COEF_A2+1,0x00},
1209 {CR_IIR_COEF_B1,0x00},
1210 {CR_IIR_COEF_B1+1,0x02},
1211 {CR_IIR_COEF_B2,0x00},
1212 {CR_IIR_COEF_B2+1,0x00},
1213 {_END_OF_TBL_,0x00},
1214 };
1215
1216 MS_VIF_REG_TYPE VIF_CR_IIR_LPF1_NEW[]=
1217 {
1218 {CR_IIR_COEF_G,0x10},
1219 {CR_IIR_COEF_G+1,0x00},
1220 {CR_IIR_COEF_A1,0xc1},
1221 {CR_IIR_COEF_A1+1,0x03},
1222 {CR_IIR_COEF_A2,0x3b},
1223 {CR_IIR_COEF_A2+1,0x06},
1224 {CR_IIR_COEF_B1,0x78},
1225 {CR_IIR_COEF_B1+1,0x04},
1226 {CR_IIR_COEF_B2,0x00},
1227 {CR_IIR_COEF_B2+1,0x02},
1228 {_END_OF_TBL_,0x00},
1229 };
1230
1231 MS_VIF_REG_TYPE VIF_CR_IIR_LPF2[]=
1232 {
1233 {CR_IIR_COEF_G,0x02},
1234 {CR_IIR_COEF_G+1,0x00},
1235 {CR_IIR_COEF_A1,0xd6},
1236 {CR_IIR_COEF_A1+1,0x03},
1237 {CR_IIR_COEF_A2,0x27},
1238 {CR_IIR_COEF_A2+1,0x06},
1239 {CR_IIR_COEF_B1,0x5b},
1240 {CR_IIR_COEF_B1+1,0x06},
1241 {CR_IIR_COEF_B2,0x00},
1242 {CR_IIR_COEF_B2+1,0x02},
1243 {_END_OF_TBL_,0x00},
1244 };
1245
1246 U16 VIF_PAL_EQ_CO_A_REJ[]=
1247 {
1248 0x0009,
1249 0x0003,
1250 0x000B,
1251 0x1FE1,
1252 0x002F,
1253 0x1FD0,
1254 0x001F,
1255 0x1FF2,
1256 0x001A,
1257 0x1FB4,
1258 0x008A,
1259 0x1F5E,
1260 0x0077,
1261 0x1FDC,
1262 0x1FFC,
1263 0x1FBB,
1264 0x00F1,
1265 0x1E79,
1266 0x0165,
1267 0x1FC9,
1268 0x1E4C,
1269 0x037C,
1270 0x0BCA,
1271 0x037C,
1272 0x1E4C,
1273 0x1FC9,
1274 0x0165,
1275 0x1E79,
1276 0x00F1,
1277 0x1FBB,
1278 0x1FFC,
1279 0x1FDC,
1280 0x0077,
1281 0x1F5E,
1282 0x008A,
1283 0x1FB4,
1284 0x001A,
1285 0x1FF2,
1286 0x001F,
1287 0x1FD0,
1288 0x002F,
1289 0x1FE1,
1290 0x000B,
1291 0x0003,
1292 0x0009,
1293 0x0000
1294 };
1295 U16 VIF_NTSC_EQ_CO_A_REJ[]=
1296 {
1297 0x001B,
1298 0x1FEB,
1299 0x0001,
1300 0x0000,
1301 0x0024,
1302 0x1FBF,
1303 0x0027,
1304 0x1FFE,
1305 0x0025,
1306 0x1F87,
1307 0x0083,
1308 0x1FD6,
1309 0x0009,
1310 0x1F78,
1311 0x0106,
1312 0x1F5A,
1313 0x1FD9,
1314 0x1FEF,
1315 0x017E,
1316 0x1DF8,
1317 0x1FB4,
1318 0x044E,
1319 0x09AF,
1320 0x044E,
1321 0x1FB4,
1322 0x1DF8,
1323 0x017E,
1324 0x1FEF,
1325 0x1FD9,
1326 0x1F5A,
1327 0x0106,
1328 0x1F78,
1329 0x0009,
1330 0x1FD6,
1331 0x0083,
1332 0x1F87,
1333 0x0025,
1334 0x1FFE,
1335 0x0027,
1336 0x1FBF,
1337 0x0024,
1338 0x0000,
1339 0x0001,
1340 0x1FEB,
1341 0x001B,
1342 0x0000
1343 };
1344
msWriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1345 void msWriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1346 {
1347 RIU_WriteByteMask(u32Reg, u8Val, u8Mask);
1348 msVifLoad();
1349 }
1350
msWriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1351 void msWriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1352 {
1353 RIU_WriteRegBit(u32Reg, bEnable, u8Mask);
1354 msVifLoad();
1355 }
1356
msWriteByte(U32 u32Reg,U8 u8Val)1357 void msWriteByte(U32 u32Reg, U8 u8Val )
1358 {
1359 RIU_WriteByte(u32Reg,u8Val);
1360 msVifLoad();
1361 }
1362
HAL_VIF_WriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1363 void HAL_VIF_WriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1364 {
1365 msWriteByteMask(u32Reg, u8Val, u8Mask);
1366 }
1367
HAL_VIF_WriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1368 void HAL_VIF_WriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1369 {
1370 msWriteBit(u32Reg, bEnable, u8Mask);
1371 }
1372
HAL_VIF_WriteByte(U32 u32Reg,U8 u8Val)1373 void HAL_VIF_WriteByte(U32 u32Reg, U8 u8Val )
1374 {
1375 msWriteByte(u32Reg, u8Val);
1376 }
1377
HAL_VIF_ReadByte(U32 u32Reg)1378 U8 HAL_VIF_ReadByte(U32 u32Reg )
1379 {
1380 return msReadByte(u32Reg);
1381 }
1382
msWriteRegsTbl(MS_VIF_REG_TYPE * pRegTable)1383 void msWriteRegsTbl(MS_VIF_REG_TYPE *pRegTable)
1384 {
1385 U16 u16Dummy;
1386 U32 u32Address;
1387 U8 u8Value;
1388
1389 u16Dummy = 2000;
1390
1391 do
1392 {
1393 u32Address = pRegTable->u32Address;
1394 u8Value = pRegTable->u8Value;
1395 if (u32Address == 0xFFFF) // check end of table
1396 break;
1397 RIU_WriteByte(u32Address, u8Value);
1398 pRegTable++;
1399 } while (--u16Dummy > 0);
1400 msVifLoad();
1401 }
1402
HAL_VIF_RegInit(void)1403 void HAL_VIF_RegInit (void)
1404 {
1405 DWORD u32NonPMBank, u32NonPMBankSize;
1406
1407 HALVIFDBG(printf("\r\nHAL_VIF_RegInit()"));
1408
1409 if (!MDrv_MMIO_GetBASE( &u32NonPMBank, &u32NonPMBankSize, MS_MODULE_VIF))
1410 {
1411 printf("\r\nIOMap failure to get MAP_NONPM_BANK");
1412 u32NonPMBank = BASEADDR_RIU; // TODO what to do if failed??
1413 }
1414 else
1415 {
1416 HALVIFDBG(printf("\r\nMS_MODULE_VIF base = 0x%lX, length = %lu", u32NonPMBank, u32NonPMBankSize));
1417 }
1418
1419 _hal_VIF.u32VIFBaseAddr = u32NonPMBank;
1420 _hal_VIF.bBaseAddrInitialized = 1;
1421
1422 if (!MDrv_MMIO_GetBASE( &u32PMBank, &u32PMBankSize, MS_MODULE_PM))
1423 {
1424 printf("\r\nIOMap failure to get MAP_PM_BANK");
1425 u32PMBank = BASEADDR_RIU; // TODO what to do if failed??
1426 }
1427 else
1428 {
1429 HALVIFDBG(printf("\r\nMS_MODULE_PM base = 0x%lX, length = %lu", u32PMBank, u32PMBankSize));
1430 }
1431 }
1432
1433
HAL_VIF_SetClock(BOOL bEnable)1434 void HAL_VIF_SetClock(BOOL bEnable)
1435 {
1436 HALVIFDBG(printf("\r\nHAL_VIF_SetClock=%d",bEnable));
1437
1438 //bEnable = (bEnable) ? 0:1; // 0 means enable
1439 }
1440
msVifAdcInitial(void)1441 void msVifAdcInitial(void)
1442 {
1443 HALVIFDBG(printf("\r\nmsVifAdcInitial()"));
1444
1445 if (!_hal_VIF.bBaseAddrInitialized) return ;
1446
1447 RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1)
1448
1449 // only support silicon tuner, internal single SAW and SAW-less architectures
1450 RIU_WriteByte(0x11F0AL, 0x00); // ADC_CLK
1451 RIU_WriteByte(0x11F0BL, 0x00);
1452 RIU_WriteByte(0x3314L, 0x04); // ADC clock
1453 RIU_WriteByte(0x3315L, 0x00); // CLK_DVBTC_INNC clock
1454 RIU_WriteByte(0x11F18L, 0x01); // SRAM
1455 RIU_WriteByte(0x11F19L, 0x40);
1456 RIU_WriteByte(0x331AL, 0x04); // MPLLDIV10/2=43MHz
1457 RIU_WriteByte(0x331BL, 0x04); // MPLLDIV10/2=43MHz
1458 RIU_WriteByte(0x11F1CL, 0x00);
1459 RIU_WriteByte(0x11F1DL, 0x00);
1460 RIU_WriteByte(0x11F2AL, 0x00); // DAGC1/2 SRAM MUX
1461 RIU_WriteByte(0x11F2BL, 0x00);
1462 RIU_WriteByte(0x12000L, 0x10); // ISDBT SRAM share enable, ISDBT and DTMB reset
1463 RIU_WriteByte(0x12001L, 0x01);
1464 RIU_WriteByte(0x12002L, 0x74); // Enable VIF, DVBT, ATSC and VIF reset
1465 RIU_WriteByte(0x12003L, 0x00);
1466 RIU_WriteByte(0x12000L, 0x00); // ISDBT SRAM share enable
1467 RIU_WriteByte(0x12001L, 0x01);
1468 RIU_WriteByte(0x12002L, 0x14); // Enable VIF
1469 RIU_WriteByte(0x12003L, 0x00);
1470 RIU_WriteByte(0x12060L, 0x04); // Disable ADC sign bit
1471 RIU_WriteByte(0x12061L, 0x00);
1472 RIU_WriteByte(0x12064L, 0x00);
1473 RIU_WriteByte(0x12065L, 0x00);
1474 RIU_WriteByte(0x12066L, 0x00);
1475 RIU_WriteByte(0x12067L, 0x00);
1476 RIU_WriteByte(0x120A0L, 0x01); // VIF use DVB SRAM and FIR
1477 RIU_WriteByte(0x11F22L, 0x01);
1478 RIU_WriteByte(0x11F23L, 0x18);
1479
1480 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOs
1481 RIU_WriteRegBit(0x12840L, 0, _BIT4);
1482 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG
1483 RIU_WriteByte(0x12802L, 0x40); // VIF path, Bypass PGA
1484 RIU_WriteByte(0x12803L, 0x04);
1485
1486 RIU_WriteByte(0x12816L, 0x05); // Set ADC gain is 1
1487 RIU_WriteByte(0x12817L, 0x05);
1488 RIU_WriteByte(0x1281EL, 0x80);
1489 RIU_WriteByte(0x1281FL, 0x00);
1490 RIU_WriteByte(0x12860L, 0x00); // Set MPLL_ADC_DIV_SEL
1491 RIU_WriteByte(0x12861L, 0x06);
1492 RIU_WriteByte(0x12866L, 0x01); // Set MPLL_LOOP_DIV_FIRST and SECOND
1493 RIU_WriteByte(0x12867L, 0x12);
1494 RIU_WriteByte(0x1286AL, 0x83); // Disable MPLL reset
1495 RIU_WriteByte(0x1286BL, 0x00);
1496 RIU_WriteByte(0x1286AL, 0x03); // Disable MPLL reset
1497 RIU_WriteByte(0x1286BL, 0x00);
1498 RIU_WriteByte(0x1286CL, 0x10); // AGC enable
1499 RIU_WriteByte(0x1286DL, 0x00);
1500 RIU_WriteByte(0x12818L, 0x00);
1501 RIU_WriteByte(0x12819L, 0x00);
1502 RIU_WriteByte(0x1287EL, 0x00); // SIF_CLK_SEL:0x1128_7E[4]
1503 RIU_WriteByte(0x1287FL, 0x00);
1504 RIU_WriteByte(0x12864L, 0x00);
1505 RIU_WriteByte(0x12865L, 0x00); // OUTPUT_DIV_SECOND
1506
1507
1508 if(VIFInitialIn_inst.VifSawArch == NO_SAW_DIF)
1509 VIFInitialIn_inst.VifSawArch = NO_SAW;
1510
1511 HAL_VIF_Delay1ms(1);
1512
1513 // RFAGC and IFAGC control (ADC)
1514 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC
1515 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC
1516 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1);
1517 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5);
1518 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
1519 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable
1520 else
1521 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable
1522 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable
1523
1524 // RFAGC and IFAGC control (RF)
1525 msWriteBit(RFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1526 msWriteBit(RFAGC_DITHER_EN, 1, _BIT7); // dither disable
1527 msWriteBit(RFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1528 msWriteBit(OREN_RFAGC, 0, _BIT5); // RFAGC 0: BB control; 1: I2C control
1529
1530 msWriteBit(IFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1531 msWriteBit(IFAGC_DITHER_EN, 1, _BIT7); // dither disable
1532 msWriteBit(IFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1533 msWriteBit(OREN_IFAGC, 0, _BIT6); // RFAGC 0: BB control; 1: I2C control
1534
1535 msWriteBit(OREN_PGA1_V, 0, _BIT3); // Video PGA1 0: BB control; 1: I2C control
1536 msWriteBit(OREN_PGA2_V, 0, _BIT2); // Video PGA2 0: BB control; 1: I2C control
1537 msWriteBit(OREN_PGA1_S, 0, _BIT1); // Audio PGA1 0: BB control; 1: I2C control
1538 msWriteBit(OREN_PGA2_S, 0, _BIT0); // Audio PGA2 0: BB control; 1: I2C control
1539
1540 // EQ BYPASS
1541 msWriteBit(BYPASS_EQFIR, 1, _BIT0);
1542 }
1543
1544 // For API
msVifSetIfFreq(IfFrequencyType ucIfFreq)1545 void msVifSetIfFreq(IfFrequencyType ucIfFreq)
1546 {
1547 HALVIFDBG(printf("\r\nmsVifSetIfFreq() ucIfFreq=%d",ucIfFreq));
1548
1549 if (!_hal_VIF.bBaseAddrInitialized) return ;
1550
1551 g_FreqType = ucIfFreq;
1552
1553 // cvbs output
1554 msWriteBit(VIFDAC_ENABLE, 1, _BIT3); // enable vifdac
1555
1556 // for China descrambler box
1557 if (VIFInitialIn_inst.ChinaDescramblerBox == 0)
1558 {
1559 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1560 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1561 }
1562 else
1563 {
1564 msWriteByteMask(VIFDAC_OUT_SEL, 0x04, 0x07); // 0: cvbs output; 4: debug bus
1565 msWriteBit(DEBUG2_EN, 1, _BIT7); // select debug2 data
1566 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1567
1568 if(VIFInitialIn_inst.ChinaDescramblerBox == 1)
1569 {
1570 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1571 msWriteByte(DEBUG_PORT, 0x84); // selsect CVBS output after Notch_A2 filter
1572 }
1573 else if(VIFInitialIn_inst.ChinaDescramblerBox == 2)
1574 {
1575 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1576 msWriteByte(DEBUG_PORT, 0x98); // select CVBS output after IMAGE_IIR
1577 }
1578 else if (VIFInitialIn_inst.ChinaDescramblerBox == 3)
1579 {
1580 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1581 msWriteByte(DEBUG_PORT, 0x8A); // select CVBS output after IMAGE_REJ1
1582 }
1583 else if (VIFInitialIn_inst.ChinaDescramblerBox == 4)
1584 {
1585 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1586 msWriteByte(DEBUG_PORT, 0x88); // select CVBS output after ACI_REJ
1587 }
1588 else if (VIFInitialIn_inst.ChinaDescramblerBox == 5)
1589 {
1590 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1591 msWriteByte(DEBUG_PORT, 0x86); // select CVBS output after MIXER_OUT_I
1592 }
1593 else if (VIFInitialIn_inst.ChinaDescramblerBox == 6)
1594 {
1595 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1596 msWriteByte(DEBUG_PORT, 0x8B); // select CVBS output after IMAGE_REJ2
1597 }
1598 else
1599 {
1600 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1601 msWriteBit(DEBUG2_EN, 0, _BIT7); // select debug2 data
1602 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1603 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1604 }
1605 }
1606
1607 if (VIFInitialIn_inst.VifTunerType == 1)
1608 {
1609 // silicon tuner
1610 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1611 msWriteByte(IF_RATE+1, 0x00);
1612 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1613 }
1614 else if (VIFInitialIn_inst.VifTunerType == 2)
1615 {
1616 // FM tuner
1617 if(VIFInitialIn_inst.VifSawArch == SILICON_TUNER)
1618 {
1619 // silicon tuner
1620 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1621 msWriteByte(IF_RATE+1, 0x00);
1622 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1623 }
1624 }
1625 else
1626 {
1627 switch(ucIfFreq)
1628 {
1629 case IF_FREQ_3395:
1630 msWriteByte(IF_RATE, 0x44); // IF rate for -48.9 MHz // HEX [ (IF/144) * 2^22]
1631 msWriteByte(IF_RATE+1, 0x44);
1632 msWriteByteMask(IF_RATE+2, 0x2A, 0x3F);
1633 break;
1634 case IF_FREQ_3800:
1635 if (g_VifShiftClk == 1)
1636 {
1637 msWriteByte(0x12866L, 0x00);//loop divider
1638 msWriteByte(0x12867L, 0x23);
1639
1640 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
1641 msWriteByte(IF_RATE+1, 0x83);
1642 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1643 }
1644 else if(g_VifShiftClk == 2)
1645 {
1646 msWriteByte(0x12866L, 0x00);//loop divider
1647 msWriteByte(0x12867L, 0x25);
1648
1649 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
1650 msWriteByte(IF_RATE+1, 0xF2);
1651 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
1652 }
1653 else
1654 {
1655 msWriteByte(0x12866L, 0x00);//loop divider
1656 msWriteByte(0x12867L, 0x24);
1657
1658 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
1659 msWriteByte(IF_RATE+1, 0x38);
1660 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1661 }
1662 break;
1663 case IF_FREQ_3890:
1664 msWriteByte(IF_RATE, 0x49); // IF rate for 23.9 MHz
1665 msWriteByte(IF_RATE+1, 0x9F);
1666 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1667 break;
1668 case IF_FREQ_3950:
1669 msWriteByte(IF_RATE, 0x8E); // IF rate for 24.5 MHz
1670 msWriteByte(IF_RATE+1, 0xE3);
1671 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1672 break;
1673 case IF_FREQ_4575:
1674 msWriteByte(IF_RATE, 0xAA); // IF rate for 30.75 MHz
1675 msWriteByte(IF_RATE+1, 0xAA);
1676 msWriteByteMask(IF_RATE+2, 0x0D, 0x3F);
1677 break;
1678 case IF_FREQ_5875:
1679 msWriteByte(IF_RATE, 0xC7); // IF rate for 43.75 MHz
1680 msWriteByte(IF_RATE+1, 0x71);
1681 msWriteByteMask(IF_RATE+2, 0x13, 0x3F);
1682 break;
1683 default:
1684 break;
1685 }
1686 }
1687 }
1688
msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem,FrequencyBand frequencyRange)1689 void msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem, FrequencyBand frequencyRange)
1690 {
1691 BYTE VifPeakingFilter=0, VifYcDelayFilter=0, VifGroupDelayFilter=0;
1692
1693 if (!_hal_VIF.bBaseAddrInitialized) return ;
1694
1695 switch (ucSoundSystem)
1696 {
1697 case VIF_SOUND_B:
1698 case VIF_SOUND_B_NICAM:
1699 if (frequencyRange==FREQ_VHF_L)
1700 {
1701 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_L;
1702 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_L;
1703 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_L;
1704 }
1705 else if (frequencyRange==FREQ_VHF_H)
1706 {
1707 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_H;
1708 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_H;
1709 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_H;
1710 }
1711 else if (frequencyRange==FREQ_UHF)
1712 {
1713 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_UHF;
1714 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_UHF;
1715 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_UHF;
1716 }
1717 else
1718 printf("\r\n ERROR msVifGroupDelayFilter B frequencyRange=%d", frequencyRange);
1719 break;
1720
1721 case VIF_SOUND_GH:
1722 case VIF_SOUND_GH_NICAM:
1723 if (frequencyRange==FREQ_VHF_L)
1724 {
1725 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_L;
1726 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_L;
1727 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_L;
1728 }
1729 else if (frequencyRange==FREQ_VHF_H)
1730 {
1731 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_H;
1732 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_H;
1733 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_H;
1734 }
1735 else if (frequencyRange==FREQ_UHF)
1736 {
1737 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_UHF;
1738 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_UHF;
1739 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_UHF;
1740 }
1741 else
1742 printf("\r\n ERROR msVifGroupDelayFilter GH frequencyRange=%d", frequencyRange);
1743 break;
1744
1745 case VIF_SOUND_I:
1746 if (frequencyRange==FREQ_VHF_L)
1747 {
1748 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_L;
1749 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_L;
1750 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_L;
1751 }
1752 else if (frequencyRange==FREQ_VHF_H)
1753 {
1754 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_H;
1755 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_H;
1756 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_H;
1757 }
1758 else if (frequencyRange==FREQ_UHF)
1759 {
1760 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_UHF;
1761 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_UHF;
1762 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_UHF;
1763 }
1764 else
1765 printf("\r\n ERROR msVifGroupDelayFilter I frequencyRange=%d", frequencyRange);
1766 break;
1767
1768 case VIF_SOUND_DK1:
1769 case VIF_SOUND_DK2:
1770 case VIF_SOUND_DK3:
1771 case VIF_SOUND_DK_NICAM:
1772 if (frequencyRange==FREQ_VHF_L)
1773 {
1774 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_L;
1775 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_L;
1776 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_L;
1777 }
1778 else if (frequencyRange==FREQ_VHF_H)
1779 {
1780 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_H;
1781 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_H;
1782 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_H;
1783 }
1784 else if (frequencyRange==FREQ_UHF)
1785 {
1786 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_UHF;
1787 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_UHF;
1788 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_UHF;
1789 }
1790 else
1791 printf("\r\n ERROR msVifGroupDelayFilter DK frequencyRange=%d", frequencyRange);
1792 break;
1793
1794 case VIF_SOUND_L:
1795 if (frequencyRange==FREQ_VHF_L)
1796 {
1797 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_L;
1798 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_L;
1799 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_L;
1800 }
1801 else if (frequencyRange==FREQ_VHF_H)
1802 {
1803 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_H;
1804 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_H;
1805 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_H;
1806 }
1807 else if (frequencyRange==FREQ_UHF)
1808 {
1809 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_UHF;
1810 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_UHF;
1811 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_UHF;
1812 }
1813 else
1814 printf("\r\n ERROR msVifGroupDelayFilter L frequencyRange=%d", frequencyRange);
1815 break;
1816
1817 case VIF_SOUND_LL:
1818 if (frequencyRange==FREQ_VHF_L)
1819 {
1820 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_L;
1821 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_L;
1822 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_L;
1823 }
1824 else if (frequencyRange==FREQ_VHF_H)
1825 {
1826 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_H;
1827 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_H;
1828 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_H;
1829 }
1830 else if (frequencyRange==FREQ_UHF)
1831 {
1832 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_UHF;
1833 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_UHF;
1834 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_UHF;
1835 }
1836 else
1837 printf("\r\n ERROR msVifGroupDelayFilter LL frequencyRange=%d", frequencyRange);
1838 break;
1839
1840 case VIF_SOUND_MN:
1841 if (frequencyRange==FREQ_VHF_L)
1842 {
1843 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_L;
1844 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_L;
1845 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_L;
1846 }
1847 else if (frequencyRange==FREQ_VHF_H)
1848 {
1849 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_H;
1850 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_H;
1851 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_H;
1852 }
1853 else if (frequencyRange==FREQ_UHF)
1854 {
1855 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_UHF;
1856 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_UHF;
1857 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_UHF;
1858 }
1859 else
1860 printf("\r\n ERROR msVifGroupDelayFilter MN frequencyRange=%d", frequencyRange);
1861 break;
1862
1863 default:
1864 printf("\r\n Error msVifGroupDelayFilter ucSoundSystem=%d",ucSoundSystem);
1865 break;
1866 }
1867
1868 HALVIFDBG(printf("\r\nmsVifGroupDelayFilter() VifPeakingFilter=%d",VifPeakingFilter));
1869 HALVIFDBG(printf(" VifYcDelayFilter=%d VifGroupDelayFilter=%d",VifYcDelayFilter, VifGroupDelayFilter));
1870
1871 if (VifPeakingFilter == 0x00)
1872 {
1873 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_NULL);
1874 }
1875 else if (VifPeakingFilter == 0x01)
1876 {
1877 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_1dB);
1878 }
1879 else if (VifPeakingFilter == 0x02)
1880 {
1881 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_2dB);
1882 }
1883 else if (VifPeakingFilter == 0x03)
1884 {
1885 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB);
1886 }
1887 else if (VifPeakingFilter == 0x04)
1888 {
1889 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB);
1890 }
1891 else if (VifPeakingFilter == 0x05)
1892 {
1893 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB_VSB);
1894 }
1895 else if (VifPeakingFilter == 0x06)
1896 {
1897 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB_VSB);
1898 }
1899 else if (VifPeakingFilter == 0x07)
1900 {
1901 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_5dB_VSB);
1902 }
1903 else if (VifPeakingFilter == 0x80)
1904 {
1905 msWriteByte(SOS21_C0_L, VIFInitialIn_inst.VifSos21FilterC0); // SOS21 (user define)
1906 msWriteByteMask(SOS21_C0_H, VIFInitialIn_inst.VifSos21FilterC0>>8, 0x07);
1907 msWriteByte(SOS21_C1_L, VIFInitialIn_inst.VifSos21FilterC1);
1908 msWriteByteMask(SOS21_C1_H, VIFInitialIn_inst.VifSos21FilterC1>>8, 0x07);
1909 msWriteByte(SOS21_C2_L, VIFInitialIn_inst.VifSos21FilterC2);
1910 msWriteByteMask(SOS21_C2_H, VIFInitialIn_inst.VifSos21FilterC2>>8, 0x07);
1911 msWriteByte(SOS21_C3_L, VIFInitialIn_inst.VifSos21FilterC3);
1912 msWriteByteMask(SOS21_C3_H, VIFInitialIn_inst.VifSos21FilterC3>>8, 0x07);
1913 msWriteByte(SOS21_C4_L, VIFInitialIn_inst.VifSos21FilterC4);
1914 msWriteByteMask(SOS21_C4_H, VIFInitialIn_inst.VifSos21FilterC4>>8, 0x07);
1915 }
1916
1917 if (VifYcDelayFilter == 0x00)
1918 {
1919 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_NULL);
1920 }
1921 else if (VifYcDelayFilter == 0x01)
1922 {
1923 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_VSB);
1924 }
1925 else if (VifYcDelayFilter == 0x80)
1926 {
1927 msWriteByte(SOS22_C0_L, VIFInitialIn_inst.VifSos22FilterC0); // SOS22 (user define)
1928 msWriteByteMask(SOS22_C0_H, VIFInitialIn_inst.VifSos22FilterC0>>8, 0x07);
1929 msWriteByte(SOS22_C1_L, VIFInitialIn_inst.VifSos22FilterC1);
1930 msWriteByteMask(SOS22_C1_H, VIFInitialIn_inst.VifSos22FilterC1>>8, 0x07);
1931 msWriteByte(SOS22_C2_L, VIFInitialIn_inst.VifSos22FilterC2);
1932 msWriteByteMask(SOS22_C2_H, VIFInitialIn_inst.VifSos22FilterC2>>8, 0x07);
1933 msWriteByte(SOS22_C3_L, VIFInitialIn_inst.VifSos22FilterC3);
1934 msWriteByteMask(SOS22_C3_H, VIFInitialIn_inst.VifSos22FilterC3>>8, 0x07);
1935 msWriteByte(SOS22_C4_L, VIFInitialIn_inst.VifSos22FilterC4);
1936 msWriteByteMask(SOS22_C4_H, VIFInitialIn_inst.VifSos22FilterC4>>8, 0x07);
1937 }
1938
1939 if (VifGroupDelayFilter == 0x00)
1940 {
1941 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_NULL);
1942 }
1943 else if (VifGroupDelayFilter == 0x01)
1944 {
1945 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_LG);
1946 }
1947 else if (VifGroupDelayFilter == 0x02)
1948 {
1949 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_Philips);
1950 }
1951 else if (VifGroupDelayFilter == 0x03)
1952 {
1953 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_R);
1954 }
1955 else if (VifGroupDelayFilter == 0x04)
1956 {
1957 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_L);
1958 }
1959 else if (VifGroupDelayFilter == 0x05)
1960 {
1961 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_R);
1962 }
1963 else if (VifGroupDelayFilter == 0x06)
1964 {
1965 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_L);
1966 }
1967 else if (VifGroupDelayFilter == 0x80)
1968 {
1969 msWriteByte(SOS31_C0_L, VIFInitialIn_inst.VifSos31FilterC0); // SOS31 (user define)
1970 msWriteByteMask(SOS31_C0_H, VIFInitialIn_inst.VifSos31FilterC0>>8, 0x07);
1971 msWriteByte(SOS31_C1_L, VIFInitialIn_inst.VifSos31FilterC1);
1972 msWriteByteMask(SOS31_C1_H, VIFInitialIn_inst.VifSos31FilterC1>>8, 0x07);
1973 msWriteByte(SOS31_C2_L, VIFInitialIn_inst.VifSos31FilterC2);
1974 msWriteByteMask(SOS31_C2_H, VIFInitialIn_inst.VifSos31FilterC2>>8, 0x07);
1975 msWriteByte(SOS31_C3_L, VIFInitialIn_inst.VifSos31FilterC3);
1976 msWriteByteMask(SOS31_C3_H, VIFInitialIn_inst.VifSos31FilterC3>>8, 0x07);
1977 msWriteByte(SOS31_C4_L, VIFInitialIn_inst.VifSos31FilterC4);
1978 msWriteByteMask(SOS31_C4_H, VIFInitialIn_inst.VifSos31FilterC4>>8, 0x07);
1979 msWriteByte(SOS32_C0_L, VIFInitialIn_inst.VifSos32FilterC0); // SOS32 (user define)
1980 msWriteByteMask(SOS32_C0_H, VIFInitialIn_inst.VifSos32FilterC0>>8, 0x07);
1981 msWriteByte(SOS32_C1_L, VIFInitialIn_inst.VifSos32FilterC1);
1982 msWriteByteMask(SOS32_C1_H, VIFInitialIn_inst.VifSos32FilterC1>>8, 0x07);
1983 msWriteByte(SOS32_C2_L, VIFInitialIn_inst.VifSos32FilterC2);
1984 msWriteByteMask(SOS32_C2_H, VIFInitialIn_inst.VifSos32FilterC2>>8, 0x07);
1985 msWriteByte(SOS32_C3_L, VIFInitialIn_inst.VifSos32FilterC3);
1986 msWriteByteMask(SOS32_C3_H, VIFInitialIn_inst.VifSos32FilterC3>>8, 0x07);
1987 msWriteByte(SOS32_C4_L, VIFInitialIn_inst.VifSos32FilterC4);
1988 msWriteByteMask(SOS32_C4_H, VIFInitialIn_inst.VifSos32FilterC4>>8, 0x07);
1989 /*
1990 msWriteByte(SOS33_C0_L, sVIFSOS33.Vif_SOS_33_C0); // SOS33 (user define)
1991 msWriteByteMask(SOS33_C0_H, sVIFSOS33.Vif_SOS_33_C0>>8, 0x07);
1992 msWriteByte(SOS33_C1_L, sVIFSOS33.Vif_SOS_33_C1);
1993 msWriteByteMask(SOS33_C1_H, sVIFSOS33.Vif_SOS_33_C1>>8, 0x07);
1994 msWriteByte(SOS33_C2_L, sVIFSOS33.Vif_SOS_33_C2);
1995 msWriteByteMask(SOS33_C2_H, sVIFSOS33.Vif_SOS_33_C2>>8, 0x07);
1996 msWriteByte(SOS33_C3_L, sVIFSOS33.Vif_SOS_33_C3);
1997 msWriteByteMask(SOS33_C3_H, sVIFSOS33.Vif_SOS_33_C3>>8, 0x07);
1998 msWriteByte(SOS33_C4_L, sVIFSOS33.Vif_SOS_33_C4);
1999 msWriteByteMask(SOS33_C4_H, sVIFSOS33.Vif_SOS_33_C4>>8, 0x07);
2000 */
2001 }
2002 msWriteBit(BYPASS_SOS33, 1, _BIT6);
2003 }
2004
2005 // For API
msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)2006 void msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)
2007 {
2008 HALVIFDBG(printf("\r\nmsVifSetSoundSystem() ucSoundSystem=%d",ucSoundSystem));
2009
2010 if (!_hal_VIF.bBaseAddrInitialized) return ;
2011
2012 DWORD VifCrRateTemp;
2013 g_ucVifSoundSystemType = ucSoundSystem;
2014
2015 switch(ucSoundSystem)
2016 {
2017 case VIF_SOUND_B:
2018 if (VIFInitialIn_inst.VifTunerType == 1)
2019 {
2020 // silicon tuner
2021 if(g_VifShiftClk == 1)
2022 {
2023 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2024 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2025 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2026 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2027 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2028 }
2029 else if(g_VifShiftClk == 2)
2030 {
2031 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2032 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2033 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2034 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2035 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2036 }
2037 else
2038 {
2039 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2040 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2041 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2042 }
2043 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2044
2045 }
2046
2047 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_A2);
2048 msVifGroupDelayFilter(VIF_SOUND_B, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2049 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2050 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2051 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2052 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2053 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2054 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2055 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2056 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2057
2058 //for Non-NTSC Setting
2059 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2060 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2061
2062 break;
2063
2064 case VIF_SOUND_B_NICAM:
2065 if (VIFInitialIn_inst.VifTunerType == 1)
2066 {
2067 // silicon tuner
2068 if(g_VifShiftClk == 1)
2069 {
2070 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2071 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2072 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2073 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2074 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2075 }
2076 else if(g_VifShiftClk == 2)
2077 {
2078 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2079 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2080 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2081 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2082 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2083 }
2084 else
2085 {
2086 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2087 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2088 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2089 }
2090 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2091 }
2092
2093 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_NICAM);
2094 msVifGroupDelayFilter(VIF_SOUND_B_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2095 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2096 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2097 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2098 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2099 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2100 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2101 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2102 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2103 //for Non-NTSC Setting
2104 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2105 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2106
2107 break;
2108
2109 case VIF_SOUND_GH:
2110 if (VIFInitialIn_inst.VifTunerType == 1)
2111 {
2112 // silicon tuner
2113 if(g_VifShiftClk == 1)
2114 {
2115 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2116 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2117 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2118 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2119 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2120 }
2121 else if(g_VifShiftClk == 2)
2122 {
2123 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2124 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2125 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2126 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2127 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2128 }
2129 else
2130 {
2131 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2132 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2133 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2134 }
2135 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2136 }
2137
2138 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_A2);
2139 msVifGroupDelayFilter(VIF_SOUND_GH, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2140 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2141 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2142 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2143 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2144 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2145 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2146 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2147 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2148 //for Non-NTSC Setting
2149 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2150 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2151
2152 break;
2153
2154 case VIF_SOUND_GH_NICAM:
2155 if (VIFInitialIn_inst.VifTunerType == 1)
2156 {
2157 // silicon tuner
2158 if(g_VifShiftClk == 1)
2159 {
2160 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2161 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2162 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2163 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2164 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2165 }
2166 else if(g_VifShiftClk == 2)
2167 {
2168 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2169 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2170 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2171 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2172 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2173 }
2174 else
2175 {
2176 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2177 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2178 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2179 }
2180 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2181 }
2182
2183 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_NICAM);
2184 msVifGroupDelayFilter(VIF_SOUND_GH_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2185 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2186 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2187 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2188 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2189 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2190 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2191 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2192 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2193 //for Non-NTSC Setting
2194 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2195 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2196
2197 break;
2198
2199 case VIF_SOUND_I:
2200 if (VIFInitialIn_inst.VifTunerType == 1)
2201 {
2202 // silicon tuner
2203 if(g_VifShiftClk == 1)
2204 {
2205 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2206 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2207 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2208 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2209 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2210 }
2211 else if(g_VifShiftClk == 2)
2212 {
2213 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2214 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2215 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2216 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2217 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2218 }
2219 else
2220 {
2221 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_I & 0x000000FF)); // cr_rate for 6.4 MHz
2222 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>8) & 0x000000FF));
2223 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>16) & 0x000000FF), 0x0F);
2224 }
2225 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_I, _BIT0); // cr_rate not invert
2226 }
2227
2228 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_NICAM);
2229 msVifGroupDelayFilter(VIF_SOUND_I, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2230 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_I_NOTCH);
2231 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_LOWER_ACI); //Notch N-1 Audio Carrier
2232 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2233 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2234 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2235 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2236 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2237 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2238 //for Non-NTSC Setting
2239 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2240 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2241
2242 break;
2243
2244 case VIF_SOUND_DK1:
2245 if (VIFInitialIn_inst.VifTunerType == 1)
2246 {
2247 // silicon tuner
2248 if(g_VifShiftClk == 1)
2249 {
2250 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2251 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2252 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2253 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2254 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2255 }
2256 else if(g_VifShiftClk == 2)
2257 {
2258 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2259 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2260 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2261 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2262 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2263 }
2264 else
2265 {
2266 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2267 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2268 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2269 }
2270 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2271 }
2272
2273 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK1_A2);
2274 msVifGroupDelayFilter(VIF_SOUND_DK1, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2275 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK1_NOTCH);
2276 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2277 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2278 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2279 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2280 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2281 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2282 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2283 //for Non-NTSC Setting
2284 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2285 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2286
2287 break;
2288
2289 case VIF_SOUND_DK2:
2290 if (VIFInitialIn_inst.VifTunerType == 1)
2291 {
2292 // silicon tuner
2293 if(g_VifShiftClk == 1)
2294 {
2295 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2296 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2297 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2298 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2299 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2300 }
2301 else if(g_VifShiftClk == 2)
2302 {
2303 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2304 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2305 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2306 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2307 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2308 }
2309 else
2310 {
2311 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2312 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2313 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2314 }
2315 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2316 }
2317
2318 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_A2);
2319 msVifGroupDelayFilter(VIF_SOUND_DK2, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2320 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK2_NOTCH);
2321 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2322 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2323 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2324 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2325 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2326 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2327 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2328 //for Non-NTSC Setting
2329 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2330 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2331
2332 break;
2333
2334 case VIF_SOUND_DK_NICAM:
2335 if (VIFInitialIn_inst.VifTunerType == 1)
2336 {
2337 // silicon tuner
2338 if(g_VifShiftClk == 1)
2339 {
2340 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2341 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2342 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2343 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2344 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2345 }
2346 else if(g_VifShiftClk == 2)
2347 {
2348 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2349 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2350 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2351 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2352 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2353 }
2354 else
2355 {
2356 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2357 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2358 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2359 }
2360 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2361 }
2362
2363 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_NICAM);
2364 msVifGroupDelayFilter(VIF_SOUND_DK_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2365 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK_NICAM_NOTCH);
2366 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2367 msWriteBit(BYPASS_ACI_REJ_NTSC, 1, _BIT6); // bypass ACI_REJ_NTSC_filter
2368 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2369 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2370 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2371 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2372 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2373 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2374 //for Non-NTSC Setting
2375 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2376 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2377
2378 break;
2379
2380 case VIF_SOUND_DK3:
2381 if (VIFInitialIn_inst.VifTunerType == 1)
2382 {
2383 // silicon tuner
2384 if(g_VifShiftClk == 1)
2385 {
2386 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2387 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2388 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2389 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2390 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2391 }
2392 else if(g_VifShiftClk == 2)
2393 {
2394 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2395 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2396 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2397 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2398 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2399 }
2400 else
2401 {
2402 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2403 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2404 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2405 }
2406 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2407 }
2408
2409 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK3_A2);
2410 msVifGroupDelayFilter(VIF_SOUND_DK3, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2411 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK3_NOTCH);
2412 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2413 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2414 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2415 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2416 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2417 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2418 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2419 //for Non-NTSC Setting
2420 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2421 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2422
2423 break;
2424
2425 case VIF_SOUND_L:
2426 if (VIFInitialIn_inst.VifTunerType == 1)
2427 {
2428 // silicon tuner
2429 if(g_VifShiftClk == 1)
2430 {
2431 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2432 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2433 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2434 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2435 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2436 }
2437 else if(g_VifShiftClk == 2)
2438 {
2439 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2440 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2441 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2442 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2443 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2444 }
2445 else
2446 {
2447 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_L & 0x000000FF)); // cr_rate for 6.4 MHz
2448 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>8) & 0x000000FF));
2449 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>16) & 0x000000FF), 0x0F);
2450 }
2451 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_L, _BIT0); // cr_rate not invert
2452 }
2453
2454 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2455 msVifGroupDelayFilter(VIF_SOUND_L, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2456 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2457 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2458 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2459 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2460 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2461 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2462 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2463 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2464 //for Non-NTSC Setting
2465 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2466 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2467
2468 break;
2469
2470 case VIF_SOUND_LL:
2471 if (VIFInitialIn_inst.VifTunerType == 1)
2472 {
2473 // silicon tuner
2474 if(g_VifShiftClk == 1)
2475 {
2476 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2477 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2478 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2479 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2480 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2481 }
2482 else if(g_VifShiftClk == 2)
2483 {
2484 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2485 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2486 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2487 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2488 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2489 }
2490 else
2491 {
2492 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_LL & 0x000000FF)); // cr_rate for 6.4 MHz
2493 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>8) & 0x000000FF));
2494 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>16) & 0x000000FF), 0x0F);
2495 }
2496 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_LL, _BIT0); // cr_rate not invert
2497 }
2498
2499 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2500 msVifGroupDelayFilter(VIF_SOUND_LL, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2501 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2502 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2503 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2504 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2505 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2506 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2507 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2508 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2509 //for Non-NTSC Setting
2510 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2511 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2512
2513 break;
2514
2515 case VIF_SOUND_MN:
2516 if (VIFInitialIn_inst.VifTunerType == 1)
2517 {
2518 // silicon tuner
2519 if(g_VifShiftClk == 1)
2520 {
2521 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2522 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2523 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2524 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2525 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2526 }
2527 else if(g_VifShiftClk == 2)
2528 {
2529 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2530 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2531 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2532 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2533 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2534 }
2535 else
2536 {
2537 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_MN & 0x000000FF)); // cr_rate for 6.4 MHz
2538 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>8) & 0x000000FF));
2539 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>16) & 0x000000FF), 0x0F);
2540 }
2541 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_MN, _BIT0); // cr_rate not invert
2542 }
2543
2544 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_A2);
2545 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_MN_NOTCH);
2546 msVifGroupDelayFilter(VIF_SOUND_MN, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2547 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_LOWER_ACI); //Notch N-1 Audio Carrier
2548 msWriteBit(A_LPF_BG_SEL, 1, _BIT6); // A_LPF_BG_SEL = 1 (NTSC)
2549 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2550 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2551 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2552 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2553 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2554 //for NTSC Setting
2555 msWriteBit(V_ACI_BPF_SEL, 0 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2556 msWriteBit(A_ACI_BPF_SEL, 0 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2557
2558 break;
2559
2560 default:
2561 break;
2562 }
2563 msVifLoadEQCoeff(ucSoundSystem);
2564 }
2565
2566 // For API
msVifTopAdjust(void)2567 void msVifTopAdjust(void)
2568 {
2569 HALVIFDBG(printf("\r\nmsVifTopAdjust() "));
2570
2571 if (!_hal_VIF.bBaseAddrInitialized) return ;
2572
2573 if (VIFInitialIn_inst.VifTunerType == 0)
2574 {
2575 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifTop, 0x1F); // pga2 min
2576 msWriteByteMask(AGC_PGA2_OV, VIFInitialIn_inst.VifTop, 0x1F);
2577 msWriteBit(AGC_PGA2_OREN, 1, _BIT1);
2578 msWriteBit(AGC_PGA2_OREN, 0, _BIT1);
2579 }
2580 }
2581
msVifDynamicTopAdjust(void)2582 void msVifDynamicTopAdjust(void)
2583 {
2584 HALVIFDBG(printf("\r\nmsVifDynamicTopAdjust() "));
2585
2586 if (!_hal_VIF.bBaseAddrInitialized) return ;
2587
2588 BYTE mean256=0, agc_pga2=0, ref=0, diff=0;
2589 WORD vga=0;
2590
2591 if (VIFInitialIn_inst.VifTunerType == 0)
2592 {
2593 vga = msRead2Bytes(AGC_VGA);
2594 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
2595 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
2596 ref = msReadByte(AGC_REF); // AGC ref
2597
2598 if (g_bCheckModulationType == 0)
2599 {
2600 diff = 0x15; // negative modulation
2601 }
2602 else
2603 {
2604 diff = 0x0A; // positive modulation
2605 }
2606
2607 if ((vga == VIFInitialIn_inst.VifVgaMinimum) && (mean256 >= (ref+diff)) && (agc_pga2 == VIFInitialIn_inst.VifTop))
2608 {
2609 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifDynamicTopMin, 0x1F); // pga2 min
2610 }
2611 else if (((agc_pga2) < VIFInitialIn_inst.VifTop) && ((vga >= 0xF000) || (vga <= VIFInitialIn_inst.VifVgaMaximum)))
2612 {
2613 msVifTopAdjust();
2614 }
2615 }
2616 }
2617
msVifLoad(void)2618 void msVifLoad(void)
2619 {
2620 if (!_hal_VIF.bBaseAddrInitialized) return ;
2621
2622 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0);
2623 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0);
2624 RIU_WriteRegBit(DBB2_LOAD , 1 , _BIT0);
2625 RIU_WriteRegBit(DBB2_LOAD , 0, _BIT0);
2626 }
2627
2628 // For API
msVifInitial(void)2629 void msVifInitial(void)
2630 {
2631 HALVIFDBG(printf("\r\nmsVifInitial()"));
2632
2633 if (!_hal_VIF.bBaseAddrInitialized) return ;
2634
2635 msWriteByteMask(VIF_SOFT_RSTZ, 0x00, 0x7F); // VIF software reset
2636 msWriteBit(CLAMPGAIN_RSTZ, 0, _BIT0); // clampgain software reset
2637 msWriteBit(VSYNC_RSTZ, 0, _BIT0); // vsync software reset
2638
2639 g_VifZeroDetFlag = 0;
2640 g_ucVifStatusStep = VIF_START;
2641
2642 //Serious_ACI_Det parameter
2643 AGC_Change_Index =0;
2644 RIU_WriteByte(0x1286EL, 0x04); // ADC Setting Overflow value
2645
2646 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
2647 {
2648 g_bCheckModulationType = 1; // positive modulation
2649 g_bCheckIFFreq = (g_ucVifSoundSystemType == VIF_SOUND_L) ? 0 : 1; // 0: 38.9 MHz; 1: 33.9 MHz
2650 }
2651 else
2652 {
2653 g_bCheckModulationType = 0; // negative modulation
2654 g_bCheckIFFreq = 0; // 38.9 MHz
2655 }
2656
2657 if (g_bCheckModulationType == 1)
2658 {
2659 msWriteByteMask(MODULATION_TYPE, 0x0F, 0x0F); // positive modulation
2660 }
2661 else
2662 {
2663 msWriteByteMask(MODULATION_TYPE, 0x00, 0x0F); // negative modulation
2664 }
2665
2666 // AGC
2667 if (g_bCheckModulationType == 1)
2668 {
2669 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2670 msWriteByteMask(AGC_PEAK_CNT_H, 0x0B, 0x0F);
2671 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefPositive); // AGC ref
2672 }
2673 else
2674 {
2675 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2676 msWriteByteMask(AGC_PEAK_CNT_H, 0x0C, 0x0F);
2677 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
2678 }
2679 msWriteByteMask(AGC_MEAN_SEL, _BIT2, _BIT2|_BIT3); // mean16
2680 msWriteByte(AGC_LINE_CNT_L, 0x01); // AGC line cnt = 1
2681 msWriteByte(AGC_LINE_CNT_H, 0x00);
2682
2683 if (bEnableUsrNonSteadyAgcK)
2684 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
2685 else
2686 {
2687 if (VIFInitialIn_inst.VifTunerType == 1)
2688 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
2689 else
2690 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
2691 }
2692
2693 msWriteByteMask(AGC_PGA2_OREN, 0x00, 0x03);
2694 msWriteByte(AGC_VGA_MAX_L, VIFInitialIn_inst.VifVgaMaximum); // vga max
2695 msWriteByte(AGC_VGA_MAX_H, VIFInitialIn_inst.VifVgaMaximum>>8);
2696 msWriteByte(AGC_VGA_MIN_L, VIFInitialIn_inst.VifVgaMinimum); // vga min
2697 msWriteByte(AGC_VGA_MIN_H, VIFInitialIn_inst.VifVgaMinimum>>8);
2698 msWriteByteMask(AGC_PGA1_MAX, 0x00, 0x0F); // pga1 max
2699 if (VIFInitialIn_inst.VifTunerType == 1)
2700 msWriteByteMask(AGC_PGA2_MAX, 0x00, 0x1F); // pga2 max
2701 else
2702 msWriteByteMask(AGC_PGA2_MAX, 0x1F, 0x1F); // pga2 max
2703
2704 msWriteByte(VAGC_VGA2_OV_L, 0x00); // VGA2(IFAGC) output minimun
2705 msWriteByte(VAGC_VGA2_OV_H, 0x80);
2706 msWriteBit(VAGC_VGA2_OREN, 1, _BIT2);
2707
2708 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
2709 msWriteBit(VAGC_VGA_OUT_SEL, 1, _BIT0); // VGA1 -> IFAGC
2710
2711 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
2712 {
2713 msWriteBit(LEVEL_SENSE_BYPASS, 0, _BIT0); // Level_Sense not bypass
2714 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
2715 msWriteBit(BYPASS_V_ACI_BPF4AGC, 0, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
2716 }
2717 else
2718 {
2719 msWriteBit(LEVEL_SENSE_BYPASS, 1, _BIT0); // Level_Sense bypass
2720 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
2721 msWriteBit(BYPASS_V_ACI_BPF4AGC, 1, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
2722 }
2723
2724 msWriteBit(AGC_IN_SEL, 1, _BIT1); // AGC input 0: from SOS_out ; 1:from ACI_BPF out(can be bypassed)
2725
2726 // AGC gain distribution
2727 msWriteBit(AGC_DBB_VVGA_SEL, 0, _BIT3); // Vga gain force x1
2728 msWriteBit(AGC_DBB_AVGA_SEL, 0, _BIT4); // Avga gain force x1
2729
2730 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.VifVgaMaximum); // vga threshold
2731 msWriteByte(AGC_VGA_THR+1, (VIFInitialIn_inst.VifVgaMaximum - 0x1000)>>8);
2732 msWriteByte(AGC_VGA_BASE, (VIFInitialIn_inst.VifAgcVgaBase - 0x14)); // vga base
2733 msWriteByte(AGC_VGA_OFFS, VIFInitialIn_inst.VifAgcVgaOffs); // vga offset
2734
2735 msWriteBit(AGC_ENABLE, 1, _BIT0); // AGC enable
2736
2737 // CR
2738 msWriteByte(CR_DL_A, 0x16); // CR audio delay line
2739 msWriteByte(CR_PD_ERR_MAX_L, 0xFF); // CR pd error max
2740 msWriteByteMask(CR_PD_ERR_MAX_H, 0x3F, 0x3F);
2741 msWriteByte(CR_NOTCH_A1_L, 0x41); // CR notch filter coefficient
2742 msWriteByte(CR_NOTCH_A1_H, 0x0C);
2743 msWriteByte(CR_NOTCH_A2_L, 0xE9); // CR notch filter coefficient
2744 msWriteByte(CR_NOTCH_A2_H, 0x0B);
2745 msWriteByte(CR_NOTCH_B1_L, 0x58); // CR notch filter coefficient
2746 msWriteByte(CR_NOTCH_B1_H, 0x00);
2747 msWriteBit(CR_ANCO_SEL, 1, _BIT0); // audio nco select
2748 if (VIFInitialIn_inst.VifTunerType == 2)
2749 {
2750 msWriteByteMask(CR_KF1_HW, 0x00, 0x0F); // kf1 hardware mode
2751 msWriteByteMask(CR_KP1_HW, 0x00, 0x0F); // kp1 hardware mode
2752 msWriteByteMask(CR_KI1_HW, 0x00, 0xF0);// ki1 hardware mode
2753 msWriteByteMask(CR_KP2_HW, 0x00, 0x0F); // kp2 hardware mode
2754 msWriteByteMask(CR_KI2_HW, 0x00, 0xF0);// ki2 hardware mode
2755 msWriteBit(CR_K_SEL, 0, _BIT6); // hw mode
2756 }
2757 else
2758 {
2759 msWriteByteMask(CR_KF1_HW, VIFInitialIn_inst.VifCrKf1, 0x0F); // kf1 hardware mode
2760 msWriteByteMask(CR_KP1_HW, VIFInitialIn_inst.VifCrKp1, 0x0F); // kp1 hardware mode
2761 msWriteByteMask(CR_KI1_HW, VIFInitialIn_inst.VifCrKi1<<4, 0xF0);// ki1 hardware mode
2762 msWriteByteMask(CR_KP2_HW, VIFInitialIn_inst.VifCrKp2, 0x0F); // kp2 hardware mode
2763 msWriteByteMask(CR_KI2_HW, VIFInitialIn_inst.VifCrKi2<<4, 0xF0);// ki2 hardware mode
2764 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
2765 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1); // for > 150% overmodulation
2766 }
2767 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
2768 msWriteByteMask(CR_KP_SW, 0x00, 0x0F); // kp software mode
2769 msWriteByteMask(CR_KI_SW, 0x00, 0xF0); // ki software mode
2770 msWriteBit(CR_JTRDET_IN_SEL, 1, _BIT4); // carrier jitter detector input select CR_LF1
2771 msWriteBit(VNCO_INV_OREN, 0, _BIT1);
2772
2773 //locking range setting
2774 msWriteBit(CR_FD_IN_SEL, 0 , _BIT0); //0:IIR LPF2; 1:FIR
2775 msWriteBit(CR_IIR_SEL, 1 , _BIT1); //0:IIR LPF1; 1:IIR LPF2
2776
2777 if(VIFInitialIn_inst.VifCrPdModeSel == 0) // 0: imaginary part; 1: cordic
2778 {
2779 if(g_VifChipVersion == 0) // Munich
2780 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF1_OLD); // IIR LPF1 coefficients
2781 else // Maldives
2782 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF1_NEW); // IIR LPF1 coefficients
2783 }
2784 else
2785 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
2786
2787 msWriteBit(CR_LPF_SEL, VIFInitialIn_inst.VifCrLpfSel, _BIT4); // CR LPF 0: FIR LPF; 1: IIR LPF
2788 msWriteBit(CR_PD_MODE, VIFInitialIn_inst.VifCrPdModeSel, _BIT1); // 0: imaginary part; 1: cordic
2789 msWriteBit(LOCK_LEAKY_SEL, VIFInitialIn_inst.VifCrLockLeakySel, _BIT0);
2790 msWriteBit(CR_PD_X2, VIFInitialIn_inst.VifCrPdX2, _BIT2); // CR X2 0: lock 0 degree; 1: lock 0 or 180 degree
2791 msWriteByte(CR_LOCK_TH_L, VIFInitialIn_inst.VifCrLockThr); // CR lock threshold
2792 msWriteByteMask(CR_LOCK_TH_H, VIFInitialIn_inst.VifCrLockThr>>8, 0x03);
2793 msWriteByte(CR_UNLOCK_NUM, 0x00); // CR unlock num
2794 msWriteByte(CR_UNLOCK_NUM+1, 0x40);
2795 msWriteByteMask(CR_UNLOCK_NUM+2, 0x00, 0x0F);
2796 msWriteByte(CR_LOCK_NUM, VIFInitialIn_inst.VifCrLockNum); // CR lock num
2797 msWriteByte(CR_LOCK_NUM+1, VIFInitialIn_inst.VifCrLockNum>>8);
2798 msWriteByteMask(CR_LOCK_NUM+2, VIFInitialIn_inst.VifCrLockNum>>16, 0x0F);
2799 msWriteByte(CR_CODIC_TH, VIFInitialIn_inst.VifCrThr); // CR cordic threshold
2800 msWriteByteMask(CR_CODIC_TH+1, VIFInitialIn_inst.VifCrThr>>8, 0x3F);
2801
2802 if (VIFInitialIn_inst.VifTunerType == 0)
2803 {
2804 if (g_VifShiftClk == 1)
2805 {
2806 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
2807 msWriteByte(CR_RATE+1, 0xDB);
2808 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
2809 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2810 }
2811 else if(g_VifShiftClk == 2)
2812 {
2813 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
2814 msWriteByte(CR_RATE+1, 0x9F);
2815 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
2816 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2817 }
2818 else
2819 {
2820 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
2821 msWriteByte(CR_RATE+1, 0x38);
2822 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
2823 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2824 }
2825 }
2826
2827 // tuner step size
2828 if(g_VifChipVersion == 1) // Maldives
2829 VIFInitialIn_inst.VifTunerStepSize = FREQ_STEP_62_5KHz;
2830
2831 if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_62_5KHz) // 62.5KHz
2832 {
2833 if (g_bCheckIFFreq == 0)
2834 {
2835 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xB3); // foe scaling factor
2836 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x02, 0x0F);
2837 }
2838 else
2839 {
2840 // SECAM L'
2841 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x4D); // foe scaling factor
2842 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0D, 0x0F);
2843 }
2844 }
2845 else if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_50KHz) // 50KHz
2846 {
2847 if (g_bCheckIFFreq == 0)
2848 {
2849 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x60); // foe scaling factor
2850 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x03, 0x0F);
2851 }
2852 else
2853 {
2854 // SECAM L'
2855 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xA0); // foe scaling factor
2856 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0C, 0x0F);
2857 }
2858 }
2859
2860 // Filter
2861 msWriteBit(DEBUG_V_A, 1, _BIT5); // single ADC
2862 if (VIFInitialIn_inst.ChinaDescramblerBox !=0)
2863 {
2864 msWriteByteMask(IMAGE_REJ_IIR_SEL, _BIT3, _BIT2|_BIT3); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
2865 }
2866 msWriteByteMask(IMAGE_REJ1_SEL, _BIT0, _BIT0|_BIT1); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
2867 msWriteBit(BYPASS_CO_A_REJ, 0, _BIT4); // CO_A_REJ not bypass
2868
2869 if(g_VifChipVersion == 0) // Munich
2870 {
2871 msWriteBit(BYPASS_SOS11, 0, _BIT0); // SOS11 not bypass
2872 msWriteBit(BYPASS_SOS12, 0, _BIT1); // SOS12 not bypass
2873 }
2874
2875 msWriteBit(IMAGE_REJ_OUT_SEL, 0, _BIT7); // 0: IMAGE_REJ1; 1: IMAGE_REJ_IIR
2876 msWriteBit(A_BP_OUT_X2, 1, _BIT7); // A_BP output x2
2877 msWriteBit(A_DAGC_SEL, 1, _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
2878 msWriteBit(BYPASS_A_NOTCH, 1, _BIT6); // A_NOTCH bypass
2879 msWriteBit(BYPASS_A_SOS, 1, _BIT7); // A_SOS bypass
2880 msWriteBit(BYPASS_SOS21, 0, _BIT2); // SOS21 not bypass
2881 msWriteBit(BYPASS_SOS22, 0, _BIT3); // SOS22 not bypass
2882 msWriteBit(BYPASS_SOS31, 0, _BIT4); // SOS31 not bypass
2883 msWriteBit(BYPASS_SOS32, 0, _BIT5); // SOS32 not bypass
2884
2885 // silicon tuner
2886 if (VIFInitialIn_inst.VifTunerType == 1)
2887 {
2888 msWriteBit(BYPASS_V_ACI_BPF4LS, 1, _BIT5); // VACI_BPF bypass
2889 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
2890 msWriteBit(BYPASS_VSPUR_REJ, 1, _BIT2); // VSPUR_REJ bypass
2891 msWriteBit(BYPASS_ASPUR_REJ, 1, _BIT3); // ASPUR_REJ bypass
2892
2893 if ((msReadByte(CR_RATE_INV) & 0x01) != 0)
2894 {
2895 msWriteBit(BYPASS_N_A1, 1, _BIT2); // Notch_A1 bypass
2896 msWriteBit(BYPASS_N_A2, 1, _BIT3); // Notch_A2 bypass
2897 msWriteBit(BYPASS_SOS11, 1, _BIT0); // SOS11 bypass
2898 msWriteBit(BYPASS_SOS12, 1, _BIT1); // SOS12 bypass
2899 }
2900 else
2901 {
2902 msWriteBit(BYPASS_N_A1, 0, _BIT2); // Notch_A1 not bypass
2903 msWriteBit(BYPASS_N_A2, 0, _BIT3); // Notch_A2 not bypass
2904 }
2905 }
2906 else
2907 {
2908 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
2909 }
2910
2911 // DAGC1
2912 if (_bit1_(VIFInitialIn_inst.VifDelayReduce))
2913 {
2914 msWriteBit(DAGC1_DL_BYPASS, 1, _BIT3); // DAGC1 delay line bypass
2915 }
2916 else
2917 {
2918 msWriteBit(DAGC1_DL_BYPASS, 0, _BIT3); // DAGC1 delay line not bypass
2919 }
2920 msWriteBit(DAGC1_BYPASS, 0, _BIT1); // DAGC1 not bypass
2921
2922 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
2923 msWriteBit(DAGC1_OREN, 0, _BIT6); // DAGC1 gain_overwrite = 0
2924
2925 msWriteBit(DAGC1_GAIN0_FB_EN, 0, _BIT2); // DAGC1 gain_update = 1
2926
2927 if (g_bCheckModulationType == 1)
2928 {
2929 msWriteByteMask(DAGC1_REF, 0x0B, 0x3F); // DAGC1 ref
2930 msWriteByteMask(DAGC1_RATIO, 0x03, 0x07); // DAGC1 ratio
2931 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
2932 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0B, 0x0F);
2933 msWriteByte(DAGC1_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc1GainOv);
2934 msWriteByteMask(DAGC1_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc1GainOv>>8, 0x3F);
2935 }
2936 else
2937 {
2938 msWriteByteMask(DAGC1_REF, VIFInitialIn_inst.VifDagc1Ref, 0x3F); // DAGC1 ref
2939 msWriteByteMask(DAGC1_RATIO, 0x00, 0x07); // DAGC1 ratio
2940 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
2941 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0C, 0x0F);
2942 }
2943 msWriteBit(DAGC1_ENABLE, 1, _BIT0); // DAGC1 enable
2944
2945 // DAGC2
2946 if (_bit2_(VIFInitialIn_inst.VifDelayReduce))
2947 {
2948 msWriteBit(DAGC2_DL_BYPASS, 1, _BIT3); // DAGC2 delay line bypass
2949 }
2950 else
2951 {
2952 msWriteBit(DAGC2_DL_BYPASS, 0, _BIT3); // DAGC2 delay line not bypass
2953 }
2954 msWriteBit(DAGC2_BYPASS, 0, _BIT1); // DAGC2 not bypass
2955
2956 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
2957 msWriteBit(DAGC2_OREN, 0, _BIT6); // DAGC2 gain_overwrite = 0
2958
2959 msWriteBit(DAGC2_GAIN0_FB_EN, 0, _BIT2); // DAGC2 gain_update = 1
2960
2961 if (g_bCheckModulationType == 1)
2962 {
2963 msWriteByteMask(DAGC2_REF, 0x0B, 0x3F); // DAGC2 ref
2964 msWriteByteMask(DAGC2_RATIO, 0x03, 0x07); // DAGC2 ratio
2965 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
2966 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0B, 0x0F);
2967 msWriteByte(DAGC2_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc2GainOv);
2968 msWriteByteMask(DAGC2_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc2GainOv>>8, 0x3F);
2969 }
2970 else
2971 {
2972 msWriteByteMask(DAGC2_REF, VIFInitialIn_inst.VifDagc2Ref, 0x3F); // DAGC2 ref
2973 msWriteByteMask(DAGC2_RATIO, 0x00, 0x07); // DAGC2 ratio
2974 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
2975 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0C, 0x0F);
2976 }
2977 msWriteBit(DAGC2_ENABLE, 1, _BIT0); // DAGC2 enable
2978
2979 // clampgain
2980 if (g_bCheckModulationType == 1)
2981 {
2982 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvPositive); // clampgain clamp overwrite value
2983 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvPositive>>8, 0x07);
2984 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvPositive); // clampgain gain overwrite value
2985 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvPositive>>8, 0x07);
2986 }
2987 else
2988 {
2989 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvNegative); // clampgain clamp overwrite value
2990 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvNegative>>8, 0x07);
2991 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvNegative); // clampgain gain overwrite value
2992 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvNegative>>8, 0x07);
2993 }
2994 msWriteBit(CLAMPGAIN_BYPASS, 0, _BIT1); // clampgain not bypass
2995 msWriteBit(CLAMPGAIN_SEL, VIFInitialIn_inst.VifClampgainClampSel, _BIT3); // 0: clamp select sync bottom; 1: clamp select porch
2996 msWriteByte(CLAMPGAIN_SYNCBOTT_REF, VIFInitialIn_inst.VifClampgainSyncbottRef); // porch or syncbottom ref
2997 msWriteByte(CLAMPGAIN_SYNCHEIGHT_REF, VIFInitialIn_inst.VifClampgainSyncheightRef); // syncheight ref
2998 msWriteByteMask(CLAMPGAIN_KC, VIFInitialIn_inst.VifClampgainKc, 0x07); // kc
2999 msWriteByteMask(CLAMPGAIN_KG, VIFInitialIn_inst.VifClampgainKg<<4, 0x70); // kg
3000 msWriteByte(CLAMPGAIN_PORCH_CNT, VIFInitialIn_inst.VifClampgainPorchCnt); // clampgain porch cnt for NTSC
3001 msWriteByteMask(CLAMPGAIN_PORCH_CNT+1, VIFInitialIn_inst.VifClampgainPorchCnt>>8, 0x01);
3002 msWriteByte(CLAMPGAIN_CLAMP_MIN, VIFInitialIn_inst.VifClampgainClampMin); // clampgain clamp min
3003 msWriteByte(CLAMPGAIN_CLAMP_MAX, VIFInitialIn_inst.VifClampgainClampMax); // clampgain clamp max
3004 msWriteByte(CLAMPGAIN_GAIN_MIN, VIFInitialIn_inst.VifClampgainGainMin); // clampgain gain min
3005 msWriteByte(CLAMPGAIN_GAIN_MAX, VIFInitialIn_inst.VifClampgainGainMax); // clampgain gain max
3006 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainClampOren, _BIT0); // clampgain clamp overwrite enable
3007 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainGainOren, _BIT1); // clampgain gain overwrite enable
3008 msWriteBit(CLAMPGAIN_EN, 1, _BIT2); // clampgain enable
3009
3010 // vsync
3011 msWriteBit(VSYNC_ENABLE, 1, _BIT1); // vsync enable
3012
3013 // ADAGC
3014 if (g_bCheckModulationType == 1)
3015 {
3016 msWriteBit(ADAGC_BYPASS, 1, _BIT1); // ADAGC bypass
3017 msWriteByteMask(ADAGC_K, 0x00, 0x07); // ADAGC k
3018 msWriteBit(ADAGC_ENABLE, 0, _BIT0); // ADAGC disable
3019 }
3020 else
3021 {
3022 msWriteBit(ADAGC_BYPASS, 0, _BIT1); // ADAGC not bypass
3023 msWriteByteMask(ADAGC_K, 0x04, 0x07); // ADAGC k
3024 msWriteBit(ADAGC_ENABLE, 1, _BIT0); // ADAGC enable
3025 }
3026
3027 if(VIFInitialIn_inst.VifSeriousACIDetect == 1) //ACI_Functions_Selective
3028 {
3029 VIFInitialIn_inst.VifACIDetect = 0;
3030 }
3031
3032 // zero detector
3033 msWriteBit(ZERO_IN_SEL, 1 , _BIT1); // 0: from dagc_in; 1: from dagc_out
3034 msWriteByteMask(ZERO_TH, 0x20, 0x7F);
3035 msWriteByte(ZERO_CNT_NUM, 0x0A);
3036 msWriteByteMask(ZERO_CNT_NUM+1, 0x00, 0x0F);
3037 msWriteByte(ZERO_ZERO_NUM, 0x20);
3038 msWriteByte(ZERO_ZERO_NUM+1, 0x00);
3039 msWriteBit(ZERO_ENABLE, 0 , _BIT0); // zero detector disable
3040
3041 // Level Sense setting
3042 msWriteByte(LEVEL_SENSE_LOCK_CNT, 0x00);
3043 msWriteByte(LEVEL_SENSE_LOCK_CNT+1, 0x01);
3044
3045 msWriteByte(LEVEL_SENSE_DIFF_AVG_TH, 0x28);
3046 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_TH+1, 0x00, 0x0F);
3047
3048 msWriteBit(LEVEL_SENSE_EN, 1, _BIT0);
3049 msWriteBit(LEVLE_SENSE_MOD_TYPE, 0, _BIT4); // 0: negedge; 1: posedge
3050 msWriteBit(LEVEL_SENSE_MODE, 0, _BIT0); // 0: porch; 1: sync height
3051 msWriteBit(LEVEL_SENSE_VGA_OREN, 0, _BIT4);
3052
3053 msWriteByteMask(LEVEL_SENSE_MEAN_SEL, 0x01, 0x03); // 0: 1 line; 1: 16 lines; 2, 3: 256 lines
3054 msWriteBit(LEVEL_SENSE_DVGA_OREN_SEL, 1 , _BIT4); // 0: SW; 1: HW
3055
3056 msWriteByte(LEVEL_SENSE_REF, 0x59);
3057 msWriteByte(LEVEL_SENSE_REF+1, 0x00);
3058
3059 msWriteByte(LEVEL_SENSE_LINE_CNT, 0x04);
3060 msWriteByte(LEVEL_SENSE_LINE_CNT+1, 0x00);
3061
3062 msWriteByte(LEVEL_SENSE_PORCH_CNT, 0xE0);
3063 msWriteByteMask(LEVEL_SENSE_PORCH_CNT+1, 0x00, 0x01);
3064
3065 msWriteByte(LEVEL_SENSE_PEAK_CNT , 0x00);
3066 msWriteByteMask(LEVEL_SENSE_PEAK_CNT +1, 0x0C, 0x0F);
3067
3068 msWriteByteMask(LEVEL_SENSE_K, 0x04, 0x07); // 0~7: 0, 2^-2 ~ 2^-8
3069 msWriteByteMask(LEVEL_SENSE_K+1, 0x00, 0x00);
3070
3071 msWriteByte(LEVEL_SENSE_VGA_OV, 0x80);
3072 msWriteByte(LEVEL_SENSE_VGA_OV+1, 0x00);
3073
3074 msWriteByte(LEVEL_SENSE_DIFF_AVG_INI, 0xFF); // level_sense diff_avg initial value
3075 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_INI+1, 0x0F, 0x0F);
3076
3077 //AM Hum detection setting
3078 msWriteByteMask(AGC_HUM_CNT_MAX , _BIT5 , _BIT4|_BIT5|_BIT6); // 0->128 ,1->256, 2->512 samples
3079 msWriteByte(AGC_HUM_ERR_THR , 0x20); // format <8,8> => 0.125 = 0x20
3080 msWriteByte(AGC_HUM_DET_LIM , 0x20); // format <8,-2> => 128 samples
3081
3082 //CR_Ki/Kp speed up setting
3083 msWriteBit(CR_KPKI_SPEEDUP_EN , 0 , _BIT0); //0:disable , 1:enable
3084 msWriteBit(CR_INV2_EN , 0 , _BIT4); //0:disable , 1:enable
3085 msWriteByteMask(CR_KP_SPEED, _BIT2 , _BIT0|_BIT1|_BIT2|_BIT3);
3086 msWriteByteMask(CR_KI_SPEED, _BIT6 , _BIT4|_BIT5|_BIT6|_BIT7);
3087
3088 if(g_VifChipVersion == 1) // Maldives
3089 {
3090 // locking range +/- 500KHz -> +/- 1MHz setting
3091 msWriteByteMask(CR_KF1_HW, 0x02, 0x0F); // kf1 hardware mode
3092 msWriteByteMask(CR_KP1_HW, 0x43, 0x0F); // kp1 hardware mode
3093 msWriteByteMask(CR_KI1_HW, 0x43, 0xF0); // ki1 hardware mode
3094 msWriteByteMask(CR_FD_DELAY_SEL, _BIT5, _BIT4|_BIT5); // fd_delay = 8
3095 msWriteByteMask(CR_FD_MU, _BIT5, _BIT4|_BIT5); // fd_mu = 2^-4
3096 }
3097
3098 //msWriteBit(BYPASS_SOS33, 1, _BIT6);
3099
3100 // real HW_KPKI_THR1_L
3101 msWriteByte(KPKI_ADJ_TH1_L, 0x50);
3102 msWriteByte(KPKI_ADJ_TH1_L+1, 0x00);
3103
3104 // real HW_KPKI_THR1_H
3105 msWriteByte(KPKI_ADJ_TH1_H, 0x50);
3106 msWriteByte(KPKI_ADJ_TH1_H+1, 0x00);
3107
3108 // real HW_KPKI_THR2_L
3109 msWriteByte(KPKI_ADJ_TH2_L, 0x00);
3110 msWriteByte(KPKI_ADJ_TH2_L+1, 0x01);
3111
3112 // real HW_KPKI_THR2_H
3113 msWriteByte(KPKI_ADJ_TH2_H, 0x00);
3114 msWriteByte(KPKI_ADJ_TH2_H+1, 0x01);
3115
3116 // real HW_KPKI_THR3_L
3117 msWriteByte(KPKI_ADJ_TH3_L, 0xFF);
3118 msWriteByte(KPKI_ADJ_TH3_L+1, 0xFF);
3119
3120 // real HW_KPKI_THR3_H
3121 msWriteByte(KPKI_ADJ_TH3_H, 0xFF);
3122 msWriteByte(KPKI_ADJ_TH3_H+1, 0xFF);
3123
3124 // real HW_KPKI setting
3125 msWriteByteMask(CR_KP_ADJ1, 0x05, 0x0F);
3126 msWriteByteMask(CR_KI_ADJ1, 0x80, 0xF0);
3127 msWriteByteMask(CR_KP_ADJ2, 0x04, 0x0F);
3128 msWriteByteMask(CR_KI_ADJ2, 0x70, 0xF0);
3129 msWriteByteMask(CR_KP_ADJ3, 0x03, 0x0F);
3130 msWriteByteMask(CR_KI_ADJ3, 0x60, 0xF0);
3131
3132 // real HW_KPKI_disable
3133 msWriteBit(KPKI_ADJ_EN, 0, _BIT0);
3134 g_VifHWKpKiFlag = 1; // 0:SW_Kp/Ki ; 1:Real HW_Kp/Ki
3135 msWriteBit(HALVIFDBG2_BIT, g_VifHWKpKiFlag, _BIT0);
3136
3137 // for China stream setting
3138 msWriteByte(CR_JTR_MAX_CNT, 0x00);
3139 msWriteByte(CR_JTR_MAX_CNT+1, 0x70);
3140 msWriteByteMask(JTR_DELTA_AVE_NUM, 0x20, 0x30);
3141
3142 if(g_VifChipVersion == 1) // Maldives
3143 {
3144 msWriteBit(BYPASS_N_A1, 1, _BIT2);
3145 msWriteBit(BYPASS_N_A2, 1, _BIT3);
3146 msWriteBit(BYPASS_SOS11, 1, _BIT0);
3147 msWriteBit(BYPASS_SOS12, 1, _BIT1);
3148 }
3149
3150 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7D); // VIF software reset
3151 msWriteBit(CLAMPGAIN_RSTZ, 1, _BIT0); // clampgain software reset
3152 msWriteBit(VSYNC_RSTZ, 1, _BIT0); // vsync software reset
3153
3154 // TOP
3155 msVifTopAdjust();
3156
3157 // version control
3158 if(g_VifChipVersion == 0) // Munich
3159 {
3160 msWriteByte(FIRMWARE_VERSION_L, 0x04); // 04(dd)
3161 msWriteByte(FIRMWARE_VERSION_H, 0x6F); // 06/15 (mm/yy) firmware version control
3162 }
3163 else // Maldives
3164 {
3165 msWriteByte(FIRMWARE_VERSION_L, 0x08); // 08(dd)
3166 msWriteByte(FIRMWARE_VERSION_H, 0x7F); // 07/15 (mm/yy) firmware version control
3167 }
3168
3169 HAL_VIF_Delay1ms(1);
3170 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7F);
3171 }
3172
3173 // For API
msVifExit(void)3174 void msVifExit(void)
3175 {
3176 if (!_hal_VIF.bBaseAddrInitialized) return ;
3177 }
3178
3179 // For API
msVifHandler(BOOL bVifDbbAcq)3180 void msVifHandler(BOOL bVifDbbAcq)
3181 {
3182 BYTE afc_foe;
3183 BYTE mean16;
3184 BYTE agc_pga2;
3185 WORD agc_vga;
3186 BYTE dagc1_var;
3187 BYTE KPKI_GEAR;
3188 static BYTE crjtr_det_cnt = 0;
3189 static WORD CNT_IDX = 0;
3190
3191 if (!_hal_VIF.bBaseAddrInitialized) return ;
3192
3193 MsOS_DelayTask(3);
3194
3195 switch(g_ucVifStatusStep)
3196 {
3197 case VIF_START:
3198 case VIF_AGC_STATUS:
3199 g_VifCrKpKiAdjLoopCnt = 0;
3200 CNT_IDX = 0;
3201 crjtr_det_cnt = 0;
3202 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3203 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3204 agc_vga = msRead2Bytes(AGC_VGA);
3205 if (g_bCheckModulationType == 0)
3206 {
3207 if (((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3208 {
3209 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3210 msWriteByte(AGC_LINE_CNT_H, 0x00);
3211
3212 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1; kp2,ki2,kf2
3213 msWriteBit(CR_K_SEL2, 0, _BIT0);
3214
3215 g_ucVifStatusStep = VIF_AFC_STATUS;
3216 }
3217 }
3218 else
3219 {
3220 if (((mean16 < AGC_MEAN16_UPBOUND_SECAM) && (mean16 > AGC_MEAN16_LOWBOUND_SECAM)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3221 {
3222 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3223 msWriteByte(AGC_LINE_CNT_H, 0x00);
3224
3225 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3226
3227 g_ucVifStatusStep = VIF_AFC_STATUS;
3228 }
3229 }
3230
3231 // for No-SAW use
3232 if((VIFInitialIn_inst.VifSawArch == NO_SAW)&&(g_bCheckModulationType == 0))
3233 {
3234 if(bVifDbbAcq == 0)
3235 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative);
3236 else
3237 msWriteByte(AGC_REF, VIFInitialIn_inst.VifChanelScanAGCREF);
3238 }
3239
3240 break;
3241
3242 case VIF_AFC_STATUS:
3243 if (_bit0_(msReadByte(CR_LOCK_STATUS)))
3244 {
3245 // DAGC
3246 if (g_bCheckModulationType == 1)
3247 {
3248 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
3249 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
3250 }
3251 g_ucVifStatusStep = VIF_AFC_STATUS2;
3252 }
3253 else
3254 {
3255 if(g_VifChipVersion == 0) // Munich
3256 {
3257 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3258 HAL_VIF_Delay1us(1);
3259 msWriteBit(CR_LF_FF_RSTZ, 0, _BIT5); // reset AFC integral part
3260 HAL_VIF_Delay1us(1);
3261 msWriteBit(CR_LF_FF_RSTZ, 1, _BIT5);
3262 }
3263 else // Maldives
3264 {
3265 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3266 HAL_VIF_Delay1us(1);
3267 msWriteBit(CR_NCO_FF_RSTZ, 0, _BIT2); // reset NCO_FF
3268 msWriteBit(CR_LF_FF_RSTZ, 0, _BIT5); // reset AFC integral part
3269 HAL_VIF_Delay1us(5);
3270 msWriteBit(CR_NCO_FF_RSTZ, 1, _BIT2);
3271 HAL_VIF_Delay1us(1);
3272 msWriteBit(CR_LF_FF_RSTZ, 1, _BIT5);
3273 }
3274 }
3275 break;
3276
3277 case VIF_AFC_STATUS2:
3278 afc_foe = msReadByte(CR_FOE); // AFC_FOE
3279 if ((afc_foe <= 0x04) || (afc_foe >= 0xFC)) // |AFC_FOE|<=4
3280 {
3281 // AGC
3282 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.GainDistributionThr); // vga threshold
3283 msWriteByte(AGC_VGA_THR+1, VIFInitialIn_inst.GainDistributionThr>>8);
3284 msWriteByte(AGC_VGA_BASE, VIFInitialIn_inst.VifAgcVgaBase); // vga base
3285 if (bVifDbbAcq == 0) // 0: not channel scan; 1: channel scan
3286 {
3287 // AGC
3288 if (bEnableUsrSteadyAgcK)
3289 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3290 else
3291 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2);// k
3292
3293 msWriteByte(AGC_LINE_CNT_L, 0x10); // AGC line cnt = 16
3294 msWriteByte(AGC_LINE_CNT_H, 0x00);
3295
3296 // CR
3297 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
3298
3299 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3300 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3301 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3302 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3303
3304 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
3305 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
3306
3307 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3308 {
3309 //if(g_VifHWKpKiFlag == 1)
3310 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3311 {
3312 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3313 KPKI_GEAR = msReadByte(CR_KPKI_GEAR) & 0x30;
3314 }
3315 }
3316
3317 msWriteByte(CR_PD_ERR_MAX_L, VIFInitialIn_inst.VifCrPdErrMax); // CR pd error max
3318 msWriteByteMask(CR_PD_ERR_MAX_H, VIFInitialIn_inst.VifCrPdErrMax>>8, 0x3F);
3319 msWriteByte(CR_UNLOCK_NUM, VIFInitialIn_inst.VifCrUnlockNum); // CR unlock num
3320 msWriteByte(CR_UNLOCK_NUM+1, VIFInitialIn_inst.VifCrUnlockNum>>8);
3321 msWriteByteMask(CR_UNLOCK_NUM+2, VIFInitialIn_inst.VifCrUnlockNum>>16, 0x0F);
3322
3323 // over modulation
3324 if ((VIFInitialIn_inst.VifOverModulation == 1) && (g_bCheckModulationType == 0))
3325 {
3326 msWriteBit(VNCO_INV_OREN, 1, _BIT1);
3327 msWriteBit(VNCO_INV_OV, 0, _BIT2);
3328 }
3329
3330 g_ucVifStatusStep = VIF_STEADY_STATUS;
3331 }
3332 }
3333
3334 if (!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3335 msVifInitial();
3336 break;
3337
3338 case VIF_STEADY_STATUS:
3339
3340 // for SAWless, ADC back-off for +20dB ACI
3341 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
3342 {
3343 if(VIFInitialIn_inst.VifSeriousACIDetect)
3344 msVifSeriousACIDetection();
3345 }
3346
3347 // Dynamic TOP adjust for strong signal
3348 if (VIFInitialIn_inst.VifDynamicTopAdjust)
3349 {
3350 msVifDynamicTopAdjust();
3351 }
3352
3353 // AM hum detector
3354 agc_vga = msRead2Bytes(AGC_VGA);
3355 dagc1_var = msReadByte(DAGC1_VAR+1);
3356 if ((VIFInitialIn_inst.VifAmHumDetection == 1) && ((agc_vga > VIFInitialIn_inst.VifVgaMinimum) || (agc_vga < (VIFInitialIn_inst.GainDistributionThr - 0x1000))))
3357 {
3358 if ((dagc1_var >= 0x18) && (g_bCheckModulationType == 0))
3359 {
3360 // 20% AM modulation
3361 msWriteByte(AGC_REF, 0x43); // AGC ref
3362 }
3363 else if ((dagc1_var <= 0x05) && (g_bCheckModulationType == 0))
3364 {
3365 // 10% AM modulation
3366 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
3367 }
3368 }
3369
3370 // AGC
3371 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3372 if (g_bCheckModulationType == 0)
3373 {
3374 if ((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND))
3375 {
3376 if (bEnableUsrSteadyAgcK)
3377 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3378 else
3379 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2); // k
3380 }
3381 else
3382 {
3383 if (bEnableUsrNonSteadyAgcK)
3384 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
3385 else
3386 {
3387 if (VIFInitialIn_inst.VifTunerType == 1)
3388 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
3389 else
3390 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
3391 }
3392 }
3393 }
3394
3395 // CR monitor
3396 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3397 if ((agc_pga2 >= 0x0F) && (VIFInitialIn_inst.VifCrPdModeSel == 1))
3398 {
3399 msWriteByteMask(CR_KP_SW, (VIFInitialIn_inst.VifCrKp)+0x01, 0x0F); // kp software mode
3400 msWriteByteMask(CR_KI_SW, (VIFInitialIn_inst.VifCrKi<<4)+0x10, 0xF0); // ki software mode
3401 }
3402 else
3403 {
3404 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3405 {
3406 //if(g_VifHWKpKiFlag == 1)
3407 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3408 {
3409 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3410 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3411 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3412 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3413
3414 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3415 KPKI_GEAR = msReadByte(CR_KPKI_GEAR) & 0x30;
3416
3417 if(KPKI_GEAR == 0)
3418 CNT_IDX = 0;
3419 else
3420 {
3421 if(CNT_IDX == 5000)
3422 {
3423 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1); // for > 150% overmodulation
3424 CNT_IDX = 0;
3425 }
3426 CNT_IDX++;
3427 }
3428 }
3429 else
3430 {
3431 msWriteBit(KPKI_ADJ_EN, 0, _BIT0); // real HW_KPKI_disable
3432
3433 if(crjtr_det_cnt < 6)
3434 {
3435 msVifCrKpKiAutoAdjust(VIFInitialIn_inst.VifCrKpKiAdjustThr1, VIFInitialIn_inst.VifCrKpKiAdjustThr2);
3436
3437 if(g_VifCrKpKiAdjLoopCnt == 0)
3438 {
3439 crjtr_det_cnt++;
3440 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3441 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3442
3443 if(g_VifCrKp != VIFInitialIn_inst.VifCrKp) // If carrier drift
3444 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1);
3445 else
3446 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1);
3447 }
3448 }
3449 }
3450 }
3451 else
3452 {
3453 msWriteByteMask(CR_KP_SW, VIFInitialIn_inst.VifCrKp, 0x0F); // kp software mode
3454 msWriteByteMask(CR_KI_SW, VIFInitialIn_inst.VifCrKi<<4, 0xF0); // ki software mode
3455 }
3456 }
3457
3458 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3459 {
3460 HAL_VIF_Delay1ms(50); // for Fluke 54200 50dBuV <-> 51dBuV switch
3461 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3462 {
3463 // for debug
3464 if (msReadByte(HALVIFDBG_BIT) & 0x08)
3465 {
3466 printf("VIF msVifInitial!!!");
3467 }
3468 msVifInitial();
3469 }
3470 }
3471
3472 // for debug
3473 if (msReadByte(HALVIFDBG_BIT) & 0x40)
3474 {
3475 if (VIFInitialIn_inst.VifCrKpKiAdjust==1 )
3476 {
3477 VIFInitialIn_inst.VifCrKpKiAdjust=0;
3478 }
3479 printf("\r\n Disable VIF KpKi auto adjust");
3480 }
3481
3482 // for debug
3483 if ((msReadByte(HALVIFDBG_BIT) & 0x80) || (VIFInitialIn_inst.VifReserve & _BIT3))
3484 {
3485 U8 ir_rate;
3486
3487 // IR Rate
3488 ir_rate = msReadByte(IF_RATE);
3489 if (ir_rate==0x49)
3490 printf("\r\n IF_FREQ_3395 IF_FREQ_3890");
3491 else if (ir_rate==0xE3)
3492 printf("\r\n IF_FREQ_3800");
3493 else if (ir_rate==0x8E)
3494 printf("\r\n IF_FREQ_3950");
3495 else if (ir_rate==0xAA)
3496 printf("\r\n IF_FREQ_4575");
3497 else if (ir_rate==0xC7)
3498 printf("\r\n IF_FREQ_5875");
3499 else
3500 printf("\r\n unknown");
3501
3502 printf(" IR_RATE=0x%x ", ir_rate);
3503
3504 // sound system
3505 if (g_ucVifSoundSystemType==0)
3506 printf("\r\n VIF_SOUND_B");
3507 else if (g_ucVifSoundSystemType==1)
3508 printf("\r\n VIF_SOUND_B_NICAM");
3509 else if (g_ucVifSoundSystemType==2)
3510 printf("\r\n VIF_SOUND_GH");
3511 else if (g_ucVifSoundSystemType==3)
3512 printf("\r\n VIF_SOUND_GH_NICAM");
3513 else if (g_ucVifSoundSystemType==4)
3514 printf("\r\n VIF_SOUND_I");
3515 else if (g_ucVifSoundSystemType==5)
3516 printf("\r\n VIF_SOUND_DK1");
3517 else if (g_ucVifSoundSystemType==6)
3518 printf("\r\n VIF_SOUND_DK2");
3519 else if (g_ucVifSoundSystemType==7)
3520 printf("\r\n VIF_SOUND_DK3");
3521 else if (g_ucVifSoundSystemType==8)
3522 printf("\r\n VIF_SOUND_DK_NICAM");
3523 else if (g_ucVifSoundSystemType==9)
3524 printf("\r\n VIF_SOUND_L");
3525 else if (g_ucVifSoundSystemType==10)
3526 printf("\r\n VIF_SOUND_LL");
3527 else if (g_ucVifSoundSystemType==11)
3528 printf("\r\n VIF_SOUND_MN");
3529 else
3530 printf("\r\n unknown");
3531
3532 printf(" sound system=%d", (BYTE)g_ucVifSoundSystemType);
3533
3534 // freq band select
3535 printf("\r\n band=%d", (BYTE)VIFInitialIn_inst.VifFreqBand);
3536 }
3537 break;
3538
3539 default:
3540 g_ucVifStatusStep++;
3541 break;
3542 }
3543
3544 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
3545 {
3546 if (g_bCheckModulationType == 0)
3547 msVifInitial();
3548 if ((g_ucVifSoundSystemType == VIF_SOUND_L) && (g_bCheckIFFreq == 1))
3549 msVifInitial();
3550 if ((g_ucVifSoundSystemType == VIF_SOUND_LL) && (g_bCheckIFFreq == 0))
3551 msVifInitial();
3552 }
3553 else
3554 {
3555 if (g_bCheckModulationType == 1)
3556 msVifInitial();
3557 }
3558 }
3559
msVifSeriousACIDetection(void)3560 void msVifSeriousACIDetection(void)
3561 {
3562 BYTE AGC_Ref ,AGC_Mean256,temp;
3563 temp = msReadByte(AGC_REF);
3564 AGC_Ref =(temp << 1);
3565 AGC_Mean256 = msReadByte(AGC_MEAN256);
3566
3567 if(SeriousACI_Index == 1)
3568 {
3569 VGA = msRead2Bytes(AGC_VGA);
3570 PGA = msReadByte(AGC_PGA2C);
3571 ADC_Index = RIU_ReadByte(0x12870L);
3572 ADC_Underflow_Index = ADC_Index & 0x02;
3573 ADC_Overflow_Index = ADC_Index & 0x04;
3574
3575 if((ADC_Underflow_Index == 0x02 ||ADC_Overflow_Index == 0x04)&&(VGA == 0x7000)&&(PGA == 0x1F)&&(AGC_Change_Index == 0)
3576 &&(AGC_Ref - AGC_Mean256 > 5))
3577 {
3578 msWriteByte(AGC_REF, VIFInitialIn_inst.VifADCOverflowAGCREF);
3579 AGC_Change_Index = 1;
3580 msWriteBit(BYPASS_SOS21, 1 , _BIT2);
3581 msWriteBit(BYPASS_SOS22, 1 , _BIT3);
3582 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, 0x00);
3583 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE+1, 0x04);
3584 }
3585 SeriousACI_Index = 0;
3586 }
3587 SeriousACI_Index = SeriousACI_Index + 1;
3588 }
3589
msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1,BYTE VifCrKpKiAdjustThr2)3590 void msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1, BYTE VifCrKpKiAdjustThr2)
3591 {
3592 MS_S16 CrJtrMax, CrJtrMin;
3593 static DWORD CrJtrDelta;
3594
3595 HALVIFDBG(printf("\r\msVifCrKpKiAutoAdjust()"));
3596
3597 msWriteBit(CR_STATUS_LATCH_EN, 1, _BIT4); // latch CR loop-filter
3598
3599 msWriteByteMask(CR_JTR_SEL, 0, _BIT3|_BIT2|_BIT1|_BIT0); // 0: max
3600 CrJtrMax = msRead2Bytes(CR_JTR_OUT);
3601
3602 msWriteByteMask(CR_JTR_SEL, _BIT0, _BIT3|_BIT2|_BIT1|_BIT0); // 1: min
3603 CrJtrMin = msRead2Bytes(CR_JTR_OUT);
3604
3605 msWriteBit(CR_STATUS_LATCH_EN, 0, _BIT4); // un-latch CR loop-filter status
3606
3607 if(g_VifCrKpKiAdjLoopCnt == 0) // reset delta value
3608 CrJtrDelta = 0;
3609
3610 CrJtrDelta += (DWORD)(CrJtrMax - CrJtrMin);
3611
3612 if (++g_VifCrKpKiAdjLoopCnt == 32) // 32 samples
3613 {
3614 CrJtrDelta = CrJtrDelta >> 5; // divided by 32
3615 CrJtrDelta = CrJtrDelta >> 7;
3616 if (g_VifCrKp >= VIFInitialIn_inst.VifCrKp)
3617 {
3618 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3619 {
3620 g_VifCrKp -= 0x02;
3621 g_VifCrKi -= 0x02;
3622 }
3623 else if ((CrJtrDelta < VifCrKpKiAdjustThr2) && (CrJtrDelta >= VifCrKpKiAdjustThr1))
3624 {
3625 g_VifCrKp -= 0x01;
3626 g_VifCrKi -= 0x01;
3627 }
3628 }
3629 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 1)
3630 {
3631 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3632 {
3633 g_VifCrKp -= 0x01;
3634 g_VifCrKi -= 0x01;
3635 }
3636 else if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3637 {
3638 g_VifCrKp += 0x01 ;
3639 g_VifCrKi += 0x01;
3640 }
3641 }
3642 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 2)
3643 {
3644 if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3645 {
3646 g_VifCrKp += 0x02;
3647 g_VifCrKi += 0x02;
3648 }
3649 else if (CrJtrDelta < VifCrKpKiAdjustThr2 - 3)
3650 {
3651 g_VifCrKp += 0x01;
3652 g_VifCrKi += 0x01;
3653 }
3654 }
3655
3656 g_VifCrKpKiAdjLoopCnt = 0;
3657 if (msReadByte(HALVIFDBG_BIT) & 0x20)
3658 {
3659 printf("\r\ng_ucVifStatusStep = %d", g_ucVifStatusStep);
3660 printf("\nKi/Kp = %x%x", g_VifCrKi, g_VifCrKp);
3661 printf("\nCrJtrMax = %x", CrJtrMax >> 7);
3662 printf("\nCrJtrMin = %x", CrJtrMin >> 7);
3663 printf("\r\nCrJtrDelta = %x", (WORD)((CrJtrDelta & 0xFFFF0000) >> 16));
3664 printf("%x\r\n",(WORD)(CrJtrDelta & 0x0000FFFF));
3665 }
3666 }
3667 }
3668
msVifReadCRFOE(void)3669 U8 msVifReadCRFOE(void)
3670 {
3671 HALVIFDBG(printf("\r\nmsVifReadCRFOE()"));
3672
3673 if (!_hal_VIF.bBaseAddrInitialized) return 0;
3674
3675 return msReadByte(CR_FOE);
3676 }
3677
msVifReadLockStatus(void)3678 U8 msVifReadLockStatus(void)
3679 {
3680 HALVIFDBG(printf("\r\nmsVifReadLockStatus()"));
3681
3682 if (!_hal_VIF.bBaseAddrInitialized) return 0;
3683
3684 return msReadByte(CR_LOCK_STATUS);
3685 }
3686
msVifLoadEQCoeff(BYTE VifSoundStandard)3687 void msVifLoadEQCoeff(BYTE VifSoundStandard)
3688 {
3689 U8 u8index;
3690
3691 HALVIFDBG(printf("\r\n msVifLoadEQCoeff()"));
3692
3693 // set coef
3694 RIU_WriteByte(0x120A0L, 0x01); // VIF use DVB SRAM and FIR
3695 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl
3696 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl
3697 msWriteBit(BYPASS_EQFIR, 1, _BIT0); // EQ BYPASS
3698
3699 if(VifSoundStandard == VIF_SOUND_MN)
3700 {
3701 for(u8index = 0; u8index < 46; ++u8index)
3702 {
3703 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]+0x8000);
3704 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]);
3705 }
3706 }
3707 else
3708 {
3709 for(u8index = 0; u8index < 46; ++u8index)
3710 {
3711 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]+0x8000);
3712 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]);
3713 }
3714 }
3715 msWriteBit(BYPASS_EQFIR , 0 , _BIT0); // EQ not BYPASS
3716 }
3717
msVifShiftClk(BYTE VifShiftClk)3718 void msVifShiftClk(BYTE VifShiftClk)
3719 {
3720 if (VifShiftClk == 1)
3721 {
3722 g_VifShiftClk = 1;
3723
3724 msWriteByte(0x12866L, 0x00);//loop divider
3725 msWriteByte(0x12867L, 0x23);
3726 if (VIFInitialIn_inst.VifTunerType == 0)
3727 {
3728 // move to clk 42 Mhz
3729 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
3730 msWriteByte(CR_RATE+1, 0xDB);
3731 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3732 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3733
3734 // move to clk 140 Mhz
3735 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
3736 msWriteByte(IF_RATE+1, 0x83);
3737 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
3738 }
3739 }
3740 else if(VifShiftClk == 2)
3741 {
3742 g_VifShiftClk = 2;
3743
3744 msWriteByte(0x12866L, 0x00);//loop divider
3745 msWriteByte(0x12867L, 0x25);
3746 if (VIFInitialIn_inst.VifTunerType == 0)
3747 {
3748 // move to clk 44.4 Mhz
3749 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
3750 msWriteByte(CR_RATE+1, 0x9F);
3751 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
3752 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3753
3754 // move to clk 148 Mhz
3755 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
3756 msWriteByte(IF_RATE+1, 0xF2);
3757 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
3758 }
3759 }
3760 else
3761 {
3762 g_VifShiftClk = 0;
3763
3764 msWriteByte(0x12866L, 0x00);//loop divider
3765 msWriteByte(0x12867L, 0x24);
3766 if (VIFInitialIn_inst.VifTunerType == 0)
3767 {
3768 // move to clk 43.2 Mhz
3769 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
3770 msWriteByte(CR_RATE+1, 0x38);
3771 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3772 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3773
3774 // move to clk 142 Mhz
3775 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
3776 msWriteByte(IF_RATE+1, 0x38);
3777 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
3778 }
3779 }
3780 }
3781
HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)3782 void HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)
3783 {
3784 HALVIFDBG(printf("HAL_VIF_BypassDBBAudioFilter() bEnableq=%d\n",bEnable));
3785 msWriteBit(A_DAGC_SEL, (!bEnable), _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
3786 }
3787
HAL_VIF_GetInputLevelIndicator(void)3788 BOOL HAL_VIF_GetInputLevelIndicator(void)
3789 {
3790 BYTE ref, mean256, diff;
3791
3792 HALVIFDBG(printf("\r\nHAL_VIF_GetInputLevelIndicator()"));
3793
3794 ref = msReadByte(AGC_REF); // AGC ref
3795 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
3796
3797 if (g_bCheckModulationType == 0)
3798 diff = 0x15; // negative modulation
3799 else
3800 diff = 0x0A; // positive modulation
3801
3802 if (mean256 >= (ref-diff))
3803 return 1;
3804 else
3805 return 0;
3806 }
3807
HAL_VIF_GetCrPDInverse(void)3808 U8 HAL_VIF_GetCrPDInverse(void)
3809 {
3810 HALVIFDBG(printf("HAL_VIF_GetCrPDInverse() %d \n", 0));
3811 if ((HAL_VIF_ReadByte(CR_PD_IMAG_INV) & _BIT1)!=0)
3812 return 1;
3813 else
3814 return 0;
3815 }
3816
HAL_VIF_SetCrPDInverse(BOOL bEnable)3817 void HAL_VIF_SetCrPDInverse(BOOL bEnable)
3818 {
3819 HALVIFDBG(printf("HAL_VIF_SetCrPDInverse() bEnableq=%d\n",bEnable));
3820 msWriteBit(CR_PD_IMAG_INV, (bEnable), _BIT1); // 0: disable; 1: enable
3821 }
3822
3823 #endif //_HALVIF_C_
3824
3825