Lines Matching refs:RIU_WriteRegBit
148 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6293 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6517 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6556 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6608 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6893 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6944 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), bEnable, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6950 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
6984 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
7007 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
7072 RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5)); in HAL_AVD_AFEC_SetPatchFlag()
7131 RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6] in HAL_AVD_AFEC_SetInput()
7145 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7150 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7165 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7170 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7187 RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7192 RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C in HAL_AVD_AFEC_SetInput()
7206 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7211 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7225 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD in HAL_AVD_AFEC_SetInput()
7245 RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7249 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7254 RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7255 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7256 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move … in HAL_AVD_AFEC_SetInput()
7257 RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware in HAL_AVD_AFEC_SetInput()
7264 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7265 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7266 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7267 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7276 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7280 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7281 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7282 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7283 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7370 RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7))); in HAL_AVD_AFEC_SetHTotal()
7388 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
7392 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
7427 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7461 RIU_WriteRegBit( BK_AFEC_CE, bEnable, BIT(0)); in HAL_AVD_AFEC_EnableForceMode()
7512 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
7513 RIU_WriteRegBit(BK_AFEC_CF, bEnable, BIT(2)); in HAL_AVD_AFEC_EnableCVBSLPF()
7554 RIU_WriteRegBit(BK_AFEC_D4, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableVBIDPLSpeedup()
7573 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7575 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7594 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7596 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7615 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7617 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7764 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); // BK_COMB_4C[7] COMB memory prote… in HAL_AVD_COMB_SetMemoryProtect()
7784 RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7785 RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7789 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7790 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7811 … RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7823 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
8050 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
8057 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
8063 RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
8070 RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
8134 RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); in HAL_AVD_COMB_SetMemoryRequest()
8141 RIU_WriteRegBit(BK_COMB_4C, DISABLE, BIT(7)); in HAL_AVD_COMB_SetMemoryRequest()
8172 RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8176 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8245 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8247 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8272 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()
8290 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()