Lines Matching refs:RIU_WriteRegBit
143 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
2934 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
3129 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3135 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3168 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3174 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3215 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3216 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3434 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3473 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
3483 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
3484 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
3485 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
3489 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
3490 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
3507 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
3509 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
3510 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
3530 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
3590 RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5)); in HAL_AVD_AFEC_SetPatchFlag()
3643 RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6] in HAL_AVD_AFEC_SetInput()
3657 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3662 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3677 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3682 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3699 RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3704 RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C in HAL_AVD_AFEC_SetInput()
3718 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3723 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3737 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD in HAL_AVD_AFEC_SetInput()
3757 RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3761 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3766 RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3767 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3768 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move … in HAL_AVD_AFEC_SetInput()
3769 RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware in HAL_AVD_AFEC_SetInput()
3776 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3777 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3778 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3779 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3788 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3792 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3793 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3794 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3795 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3882 RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7))); in HAL_AVD_AFEC_SetHTotal()
3900 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
3904 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
3939 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
3973 RIU_WriteRegBit( BK_AFEC_CE, bEnable, BIT(0)); in HAL_AVD_AFEC_EnableForceMode()
4024 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
4025 RIU_WriteRegBit(BK_AFEC_CF, bEnable, BIT(2)); in HAL_AVD_AFEC_EnableCVBSLPF()
4066 RIU_WriteRegBit(BK_AFEC_D4, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableVBIDPLSpeedup()
4085 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4087 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4106 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4108 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4127 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4129 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4273 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); // BK_COMB_4C[7] COMB memory prote… in HAL_AVD_COMB_SetMemoryProtect()
4293 RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
4294 RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
4298 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
4299 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
4320 … RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
4332 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
4559 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
4566 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
4572 RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
4579 RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
4654 RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
4658 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
4727 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4729 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4754 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()
4772 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()