1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 #ifndef _HALVIF_C_
95 #define _HALVIF_C_
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #include "MsCommon.h"
102 #include "MsIRQ.h"
103 #include "MsOS.h"
104 #include "MsTypes.h"
105 #include "drvMMIO.h"
106
107 // Internal Definition
108 #include "regVIF.h"
109 #include "VIF.h"
110 #include "halVIF.h"
111 #include "halVIF_Customer.h"
112 #include "asmCPU.h"
113 //-------------------------------------------------------------------------------------------------
114 // Driver Compiler Options
115 //-------------------------------------------------------------------------------------------------
116 #define HALVIFDBG(x) //x
117 #define HALVIFDBG_BIT (DBB1_REG_BASE+0x06) // Bit 4~7
118 #define HALVIFDBG1_BIT (DBB1_REG_BASE+0x04) // Bit 1
119 #define HALVIFDBG2_BIT (DBB1_REG_BASE+0xF6) // Bit 0~1
120 //-------------------------------------------------------------------------------------------------
121 // extern function
122 //-------------------------------------------------------------------------------------------------
123 #define HAL_VIF_Delay1ms(x) MAsm_CPU_DelayMs(x)
124 #define HAL_VIF_Delay1us(x) MAsm_CPU_DelayUs(x)
125 #define HAL_VIF_GetSystemTime() MsOS_GetSystemTime()
126 //-------------------------------------------------------------------------------------------------
127 // Local Defines
128 //-------------------------------------------------------------------------------------------------
129 #define __CHIP_VERSION 0x1ECF
130
131 #ifndef _END_OF_TBL_
132 #define _END_OF_TBL_ 0xFFFF
133 #endif
134
135 #define msRead2Bytes(x) RIU_Read2Byte(x)
136 #define msReadByte(x) RIU_ReadByte(x)
137
138 // Base address should be initial.
139 #if defined (__aeon__) // Non-OS
140 #define BASEADDR_RIU 0xA0000000UL
141 #else // ecos
142 #define BASEADDR_RIU 0xBF800000UL
143 #endif
144
145 #define RIU_MACRO_START do {
146 #define RIU_MACRO_END } while (0)
147
148 // Address bus of RIU is 16 bits.
149 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_VIF.virtVIFBaseAddr + (addr) ) )
150 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_VIF.virtVIFBaseAddr + (addr) ) )
151 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_VIF.virtVIFBaseAddr + (addr), val) }
152 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_VIF.virtVIFBaseAddr + (addr), val) }
153
154 // Standard Form
155
156 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
157
158 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
159
160 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
161
162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
163 RIU_MACRO_START \
164 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
165 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
166 RIU_MACRO_END
167
168 #define RIU_WriteByte( u32Reg, u8Val ) \
169 RIU_MACRO_START \
170 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
171 RIU_MACRO_END
172
173 #define RIU_Write2Byte( u32Reg, u16Val ) \
174 RIU_MACRO_START \
175 if ( ((u32Reg) & 0x01) ) \
176 { \
177 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
178 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
179 } \
180 else \
181 { \
182 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
183 } \
184 RIU_MACRO_END
185
186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
187 RIU_MACRO_START \
188 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
189 RIU_MACRO_END
190
191 // Address bus of RIU is 16 bits for PM bank.
192 #define PM_RIU_READ_BYTE(addr) ( READ_BYTE(virtPMBank + (addr) ) )
193 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD(virtPMBank+ (addr) ) )
194 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE(virtPMBank + (addr), val) }
195 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD(virtPMBank + (addr), val) }
196
197 // Standard Form for PM bank
198 #define PM_RIU_ReadByte( u32Reg ) PM_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
199
200 #define PM_RIU_Read2Byte( u32Reg ) (PM_RIU_READ_2BYTE((u32Reg)<<1))
201
202 #define PM_RIU_ReadRegBit( u32Reg, u8Mask ) (PM_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
203
204 #define PM_RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
205 RIU_MACRO_START \
206 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
207 (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
208 RIU_MACRO_END
209
210 #define PM_RIU_WriteByte( u32Reg, u8Val ) \
211 RIU_MACRO_START \
212 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
213 RIU_MACRO_END
214
215 #define PM_RIU_Write2Byte( u32Reg, u16Val ) \
216 RIU_MACRO_START \
217 if ( ((u32Reg) & 0x01) ) \
218 { \
219 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
220 PM_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
221 } \
222 else \
223 { \
224 PM_RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
225 } \
226 RIU_MACRO_END
227
228 #define PM_RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
229 RIU_MACRO_START \
230 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (PM_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
231 RIU_MACRO_END
232
233 //-------------------------------------------------------------------------------------------------
234 // Local Structures
235 //-------------------------------------------------------------------------------------------------
236 typedef struct
237 {
238 MS_VIRT virtVIFBaseAddr;
239 BOOL bBaseAddrInitialized;
240 } hal_VIF_t;
241
242 //-------------------------------------------------------------------------------------------------
243 // Local Variables
244 //-------------------------------------------------------------------------------------------------
245 static hal_VIF_t _hal_VIF ={BASEADDR_RIU, 0};
246 extern VIFInitialIn VIFInitialIn_inst;
247 //extern VIFSOS33 sVIFSOS33;
248 extern BOOL bEnableUsrSteadyAgcK;
249 extern U8 u8UsrSteadyAgcK;
250 extern BOOL bEnableUsrNonSteadyAgcK;
251 extern U8 u8UsrNonSteadyAgcK;
252 /////////////////////////////////////////////////////
253 BOOL AGC_Change_Index; //for Serious ACI Parameter
254 U16 SeriousACI_Index = 0;
255 ////////////////////////////////////////////////////
256 BYTE g_ucVifStatusStep;
257 BOOL g_bCheckIFFreq; // 0: 38.9 MHz (PAL/SECAM L); 1: 33.9 MHz (SECAM L')
258 BOOL g_VifHWKpKiFlag;
259 BYTE g_VifCrKp;
260 BYTE g_VifCrKi;
261 BYTE g_VifCrKpKiAdjLoopCnt;
262 BOOL g_bCheckModulationType; // 0: negative; 1: positive
263 BYTE g_ucVifSoundSystemType;
264 ////////////////////////////////////////////////////
265
266 #define VIF_IS_ADC_48MHz 0 // 0:144MHz ; 1:48MHz
267
268 //-------------------------------------------------------------------------------------------------
269 // Local code data
270 //-------------------------------------------------------------------------------------------------
271 MS_VIF_REG_TYPE VIF_GDE_PEAKING_1dB[]=
272 {
273 {SOS21_C0_L,0xc1}, // SOS21 peaking
274 {SOS21_C0_H,0x02},
275 {SOS21_C1_L,0x87},
276 {SOS21_C1_H,0x06},
277 {SOS21_C2_L,0x08},
278 {SOS21_C2_H,0x02},
279 {SOS21_C3_L,0x3f},
280 {SOS21_C3_H,0x05},
281 {SOS21_C4_L,0x70},
282 {SOS21_C4_H,0x01},
283 {_END_OF_TBL_,0x00},
284 };
285 MS_VIF_REG_TYPE VIF_GDE_PEAKING_2dB[]=
286 {
287 {SOS21_C0_L,0xa4}, // SOS21 peaking
288 {SOS21_C0_H,0x02},
289 {SOS21_C1_L,0x8e},
290 {SOS21_C1_H,0x06},
291 {SOS21_C2_L,0x12},
292 {SOS21_C2_H,0x02},
293 {SOS21_C3_L,0x5c},
294 {SOS21_C3_H,0x05},
295 {SOS21_C4_L,0x60},
296 {SOS21_C4_H,0x01},
297 {_END_OF_TBL_,0x00},
298 };
299 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB[]=
300 {
301 {SOS21_C0_L,0xc1}, // SOS21 peaking
302 {SOS21_C0_H,0x02},
303 {SOS21_C1_L,0x87},
304 {SOS21_C1_H,0x06},
305 {SOS21_C2_L,0x1c},
306 {SOS21_C2_H,0x02},
307 {SOS21_C3_L,0x3f},
308 {SOS21_C3_H,0x05},
309 {SOS21_C4_L,0x5d},
310 {SOS21_C4_H,0x01},
311 {_END_OF_TBL_,0x00},
312 };
313 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB[]=
314 {
315 {SOS21_C0_L,0xc1}, // SOS21 peaking
316 {SOS21_C0_H,0x02},
317 {SOS21_C1_L,0x87},
318 {SOS21_C1_H,0x06},
319 {SOS21_C2_L,0x28},
320 {SOS21_C2_H,0x02},
321 {SOS21_C3_L,0x3f},
322 {SOS21_C3_H,0x05},
323 {SOS21_C4_L,0x51},
324 {SOS21_C4_H,0x01},
325 {_END_OF_TBL_,0x00},
326 };
327 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB_VSB[]=
328 {
329 {SOS21_C0_L,0xf5}, // SOS21 peaking
330 {SOS21_C0_H,0x02},
331 {SOS21_C1_L,0x23},
332 {SOS21_C1_H,0x06},
333 {SOS21_C2_L,0x07},
334 {SOS21_C2_H,0x02},
335 {SOS21_C3_L,0x0b},
336 {SOS21_C3_H,0x05},
337 {SOS21_C4_L,0xd5},
338 {SOS21_C4_H,0x01},
339 {_END_OF_TBL_,0x00},
340 };
341 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB_VSB[]=
342 {
343 {SOS21_C0_L,0xf5}, // SOS21 peaking
344 {SOS21_C0_H,0x02},
345 {SOS21_C1_L,0x23},
346 {SOS21_C1_H,0x06},
347 {SOS21_C2_L,0x0a},
348 {SOS21_C2_H,0x02},
349 {SOS21_C3_L,0x0b},
350 {SOS21_C3_H,0x05},
351 {SOS21_C4_L,0xd2},
352 {SOS21_C4_H,0x01},
353 {_END_OF_TBL_,0x00},
354 };
355 MS_VIF_REG_TYPE VIF_GDE_PEAKING_5dB_VSB[]=
356 {
357 {SOS21_C0_L,0xf5}, // SOS21 peaking
358 {SOS21_C0_H,0x02},
359 {SOS21_C1_L,0x23},
360 {SOS21_C1_H,0x06},
361 {SOS21_C2_L,0x0e},
362 {SOS21_C2_H,0x02},
363 {SOS21_C3_L,0x0b},
364 {SOS21_C3_H,0x05},
365 {SOS21_C4_L,0xcf},
366 {SOS21_C4_H,0x01},
367 {_END_OF_TBL_,0x00},
368 };
369 MS_VIF_REG_TYPE VIF_GDE_PEAKING_NULL[]=
370 {
371 {SOS21_C0_L,0x00}, // SOS21
372 {SOS21_C0_H,0x00},
373 {SOS21_C1_L,0x00},
374 {SOS21_C1_H,0x00},
375 {SOS21_C2_L,0x00},
376 {SOS21_C2_H,0x00},
377 {SOS21_C3_L,0x00},
378 {SOS21_C3_H,0x00},
379 {SOS21_C4_L,0x00},
380 {SOS21_C4_H,0x02},
381 {_END_OF_TBL_,0x00},
382 };
383 MS_VIF_REG_TYPE VIF_GDE_YCDelay_VSB[]=
384 {
385 {SOS22_C0_L,0x15}, // SOS22 Y/C delay
386 {SOS22_C0_H,0x02},
387 {SOS22_C1_L,0x84},
388 {SOS22_C1_H,0x06},
389 {SOS22_C2_L,0x7c},
390 {SOS22_C2_H,0x01},
391 {SOS22_C3_L,0xeb},
392 {SOS22_C3_H,0x05},
393 {SOS22_C4_L,0x00},
394 {SOS22_C4_H,0x02},
395 {_END_OF_TBL_,0x00},
396 };
397 MS_VIF_REG_TYPE VIF_GDE_YCDelay_NULL[]=
398 {
399 {SOS22_C0_L,0x00}, // SOS22
400 {SOS22_C0_H,0x00},
401 {SOS22_C1_L,0x00},
402 {SOS22_C1_H,0x00},
403 {SOS22_C2_L,0x00},
404 {SOS22_C2_H,0x00},
405 {SOS22_C3_L,0x00},
406 {SOS22_C3_H,0x00},
407 {SOS22_C4_L,0x00},
408 {SOS22_C4_H,0x02},
409 {_END_OF_TBL_,0x00},
410 };
411 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_R[]=
412 {
413 {SOS31_C0_L,0xcc}, // SOS31
414 {SOS31_C0_H,0x00},
415 {SOS31_C1_L,0x6c},
416 {SOS31_C1_H,0x07},
417 {SOS31_C2_L,0x94},
418 {SOS31_C2_H,0x00},
419 {SOS31_C3_L,0x34},
420 {SOS31_C3_H,0x07},
421 {SOS31_C4_L,0x00},
422 {SOS31_C4_H,0x02},
423 {SOS32_C0_L,0xb4}, // SOS32
424 {SOS32_C0_H,0x02},
425 {SOS32_C1_L,0xf8},
426 {SOS32_C1_H,0x06},
427 {SOS32_C2_L,0x08},
428 {SOS32_C2_H,0x01},
429 {SOS32_C3_L,0x4c},
430 {SOS32_C3_H,0x05},
431 {SOS32_C4_L,0x00},
432 {SOS32_C4_H,0x02},
433 {_END_OF_TBL_,0x00},
434 };
435 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_L[]=
436 {
437 {SOS31_C0_L,0x3c}, // SOS31
438 {SOS31_C0_H,0x02},
439 {SOS31_C1_L,0xb8},
440 {SOS31_C1_H,0x06},
441 {SOS31_C2_L,0x48},
442 {SOS31_C2_H,0x01},
443 {SOS31_C3_L,0xc4},
444 {SOS31_C3_H,0x05},
445 {SOS31_C4_L,0x00},
446 {SOS31_C4_H,0x02},
447 {SOS32_C0_L,0xd9}, // SOS32
448 {SOS32_C0_H,0x02},
449 {SOS32_C1_L,0xf7},
450 {SOS32_C1_H,0x06},
451 {SOS32_C2_L,0x0a},
452 {SOS32_C2_H,0x01},
453 {SOS32_C3_L,0x28},
454 {SOS32_C3_H,0x05},
455 {SOS32_C4_L,0x00},
456 {SOS32_C4_H,0x02},
457 {_END_OF_TBL_,0x00},
458 };
459 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_R[]=
460 {
461 {SOS31_C0_L,0xcc}, // SOS31
462 {SOS31_C0_H,0x00},
463 {SOS31_C1_L,0x6c},
464 {SOS31_C1_H,0x07},
465 {SOS31_C2_L,0x94},
466 {SOS31_C2_H,0x00},
467 {SOS31_C3_L,0x34},
468 {SOS31_C3_H,0x07},
469 {SOS31_C4_L,0x00},
470 {SOS31_C4_H,0x02},
471 {SOS32_C0_L,0xc7}, // SOS32
472 {SOS32_C0_H,0x02},
473 {SOS32_C1_L,0xd8},
474 {SOS32_C1_H,0x06},
475 {SOS32_C2_L,0x28},
476 {SOS32_C2_H,0x01},
477 {SOS32_C3_L,0x39},
478 {SOS32_C3_H,0x05},
479 {SOS32_C4_L,0x00},
480 {SOS32_C4_H,0x02},
481 {_END_OF_TBL_,0x00},
482 };
483 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_L[]=
484 {
485 {SOS31_C0_L,0xcc}, // SOS31
486 {SOS31_C0_H,0x00},
487 {SOS31_C1_L,0x6c},
488 {SOS31_C1_H,0x07},
489 {SOS31_C2_L,0x94},
490 {SOS31_C2_H,0x00},
491 {SOS31_C3_L,0x34},
492 {SOS31_C3_H,0x07},
493 {SOS31_C4_L,0x00},
494 {SOS31_C4_H,0x02},
495 {SOS32_C0_L,0xb0}, // SOS32
496 {SOS32_C0_H,0x02},
497 {SOS32_C1_L,0x13},
498 {SOS32_C1_H,0x07},
499 {SOS32_C2_L,0xed},
500 {SOS32_C2_H,0x00},
501 {SOS32_C3_L,0x50},
502 {SOS32_C3_H,0x05},
503 {SOS32_C4_L,0x00},
504 {SOS32_C4_H,0x02},
505 {_END_OF_TBL_,0x00},
506 };
507 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_LG[]=
508 {
509 {SOS31_C0_L,0xab}, // SOS31
510 {SOS31_C0_H,0x02},
511 {SOS31_C1_L,0x9b},
512 {SOS31_C1_H,0x06},
513 {SOS31_C2_L,0x65},
514 {SOS31_C2_H,0x01},
515 {SOS31_C3_L,0x55},
516 {SOS31_C3_H,0x05},
517 {SOS31_C4_L,0x00},
518 {SOS31_C4_H,0x02},
519 {SOS32_C0_L,0xe1}, // SOS32
520 {SOS32_C0_H,0x02},
521 {SOS32_C1_L,0xf7},
522 {SOS32_C1_H,0x06},
523 {SOS32_C2_L,0x0a},
524 {SOS32_C2_H,0x01},
525 {SOS32_C3_L,0x1f},
526 {SOS32_C3_H,0x05},
527 {SOS32_C4_L,0x00},
528 {SOS32_C4_H,0x02},
529 {_END_OF_TBL_,0x00},
530 };
531 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_Philips[]=
532 {
533 {SOS31_C0_L,0x9f}, // SOS31
534 {SOS31_C0_H,0x02},
535 {SOS31_C1_L,0xa8},
536 {SOS31_C1_H,0x06},
537 {SOS31_C2_L,0x58},
538 {SOS31_C2_H,0x01},
539 {SOS31_C3_L,0x62},
540 {SOS31_C3_H,0x05},
541 {SOS31_C4_L,0x00},
542 {SOS31_C4_H,0x02},
543 {SOS32_C0_L,0xcd}, // SOS32
544 {SOS32_C0_H,0x02},
545 {SOS32_C1_L,0x05},
546 {SOS32_C1_H,0x07},
547 {SOS32_C2_L,0xfb},
548 {SOS32_C2_H,0x00},
549 {SOS32_C3_L,0x33},
550 {SOS32_C3_H,0x05},
551 {SOS32_C4_L,0x00},
552 {SOS32_C4_H,0x02},
553 {_END_OF_TBL_,0x00},
554 };
555 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_NULL[]=
556 {
557 {SOS31_C0_L,0x00}, // SOS31
558 {SOS31_C0_H,0x00},
559 {SOS31_C1_L,0x00},
560 {SOS31_C1_H,0x00},
561 {SOS31_C2_L,0x00},
562 {SOS31_C2_H,0x00},
563 {SOS31_C3_L,0x00},
564 {SOS31_C3_H,0x00},
565 {SOS31_C4_L,0x00},
566 {SOS31_C4_H,0x02},
567 {SOS32_C0_L,0x00}, // SOS32
568 {SOS32_C0_H,0x00},
569 {SOS32_C1_L,0x00},
570 {SOS32_C1_H,0x00},
571 {SOS32_C2_L,0x00},
572 {SOS32_C2_H,0x00},
573 {SOS32_C3_L,0x00},
574 {SOS32_C3_H,0x00},
575 {SOS32_C4_L,0x00},
576 {SOS32_C4_H,0x02},
577 {_END_OF_TBL_,0x00},
578 };
579 MS_VIF_REG_TYPE VIF_PAL_B_A2[]=
580 {
581 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
582 {N_A1_C0_H,0x02},
583 {N_A1_C1_L,0x3c},
584 {N_A1_C1_H,0x06},
585 {N_A1_C2_L,0x37},
586 {N_A1_C2_H,0x05},
587 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
588 {N_A2_C0_H,0x02},
589 {N_A2_C1_L,0x3c},
590 {N_A2_C1_H,0x06},
591 {N_A2_C2_L,0x51},
592 {N_A2_C2_H,0x05},
593 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
594 {SOS12_C0_H,0x02},
595 {SOS12_C1_L,0x3c},
596 {SOS12_C1_H,0x06},
597 {SOS12_C2_L,0x00},
598 {SOS12_C2_H,0x02},
599 {SOS12_C3_L,0x37},
600 {SOS12_C3_H,0x05},
601 {SOS12_C4_L,0x00},
602 {SOS12_C4_H,0x02},
603 {_END_OF_TBL_,0x00}, // PAL B/G A2
604 };
605 MS_VIF_REG_TYPE VIF_PAL_B_NICAM[]=
606 {
607 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
608 {N_A1_C0_H,0x02},
609 {N_A1_C1_L,0x3c},
610 {N_A1_C1_H,0x06},
611 {N_A1_C2_L,0x37},
612 {N_A1_C2_H,0x05},
613 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
614 {N_A2_C0_H,0x02},
615 {N_A2_C1_L,0x3c},
616 {N_A2_C1_H,0x06},
617 {N_A2_C2_L,0x5d},
618 {N_A2_C2_H,0x05},
619 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
620 {SOS12_C0_H,0x02},
621 {SOS12_C1_L,0x3c},
622 {SOS12_C1_H,0x06},
623 {SOS12_C2_L,0x00},
624 {SOS12_C2_H,0x02},
625 {SOS12_C3_L,0x37},
626 {SOS12_C3_H,0x05},
627 {SOS12_C4_L,0x00},
628 {SOS12_C4_H,0x02},
629 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
630 };
631 MS_VIF_REG_TYPE VIF_PAL_GH_A2[]=
632 {
633 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
634 {N_A1_C0_H,0x02},
635 {N_A1_C1_L,0x3c},
636 {N_A1_C1_H,0x06},
637 {N_A1_C2_L,0x37},
638 {N_A1_C2_H,0x05},
639 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
640 {N_A2_C0_H,0x02},
641 {N_A2_C1_L,0x3c},
642 {N_A2_C1_H,0x06},
643 {N_A2_C2_L,0x51},
644 {N_A2_C2_H,0x05},
645 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
646 {SOS12_C0_H,0x02},
647 {SOS12_C1_L,0x3c},
648 {SOS12_C1_H,0x06},
649 {SOS12_C2_L,0x00},
650 {SOS12_C2_H,0x02},
651 {SOS12_C3_L,0x37},
652 {SOS12_C3_H,0x05},
653 {SOS12_C4_L,0x00},
654 {SOS12_C4_H,0x02},
655 {_END_OF_TBL_,0x00}, // PAL B/G A2
656 };
657 MS_VIF_REG_TYPE VIF_PAL_GH_NICAM[]=
658 {
659 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
660 {N_A1_C0_H,0x02},
661 {N_A1_C1_L,0x3c},
662 {N_A1_C1_H,0x06},
663 {N_A1_C2_L,0x37},
664 {N_A1_C2_H,0x05},
665 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
666 {N_A2_C0_H,0x02},
667 {N_A2_C1_L,0x3c},
668 {N_A2_C1_H,0x06},
669 {N_A2_C2_L,0x5d},
670 {N_A2_C2_H,0x05},
671 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
672 {SOS12_C0_H,0x02},
673 {SOS12_C1_L,0x3c},
674 {SOS12_C1_H,0x06},
675 {SOS12_C2_L,0x00},
676 {SOS12_C2_H,0x02},
677 {SOS12_C3_L,0x37},
678 {SOS12_C3_H,0x05},
679 {SOS12_C4_L,0x00},
680 {SOS12_C4_H,0x02},
681 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
682 };
683 MS_VIF_REG_TYPE VIF_SECAM_L_NICAM[]=
684 {
685 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
686 {N_A1_C0_H,0x02},
687 {N_A1_C1_L,0x3c},
688 {N_A1_C1_H,0x06},
689 {N_A1_C2_L,0xa9},
690 {N_A1_C2_H,0x05},
691 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
692 {N_A2_C0_H,0x02},
693 {N_A2_C1_L,0x3c},
694 {N_A2_C1_H,0x06},
695 {N_A2_C2_L,0x5d},
696 {N_A2_C2_H,0x05},
697 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
698 {SOS12_C0_H,0x02},
699 {SOS12_C1_L,0x3c},
700 {SOS12_C1_H,0x06},
701 {SOS12_C2_L,0x00},
702 {SOS12_C2_H,0x02},
703 {SOS12_C3_L,0xa9},
704 {SOS12_C3_H,0x05},
705 {SOS12_C4_L,0x00},
706 {SOS12_C4_H,0x02},
707 {_END_OF_TBL_,0x00}, // SECAM L NICAM
708 };
709
710 MS_VIF_REG_TYPE VIF_PAL_I_NICAM[]=
711 {
712 {N_A1_C0_L,0x6b}, // Notch_A1, R = 0.94
713 {N_A1_C0_H,0x02},
714 {N_A1_C1_L,0x3c},
715 {N_A1_C1_H,0x06},
716 {N_A1_C2_L,0x6e},
717 {N_A1_C2_H,0x05},
718 {N_A2_C0_L,0x2e}, // Notch_A2, R = 0.94
719 {N_A2_C0_H,0x02},
720 {N_A2_C1_L,0x3c},
721 {N_A2_C1_H,0x06},
722 {N_A2_C2_L,0xaf},
723 {N_A2_C2_H,0x05},
724 {SOS12_C0_L,0x6b}, // SOS12, R = 0.94
725 {SOS12_C0_H,0x02},
726 {SOS12_C1_L,0x3c},
727 {SOS12_C1_H,0x06},
728 {SOS12_C2_L,0x00},
729 {SOS12_C2_H,0x02},
730 {SOS12_C3_L,0x6e},
731 {SOS12_C3_H,0x05},
732 {SOS12_C4_L,0x00},
733 {SOS12_C4_H,0x02},
734 {_END_OF_TBL_,0x00}, // PAL I NICAM
735 };
736
737 MS_VIF_REG_TYPE VIF_SECAM_DK1_A2[]=
738 {
739 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
740 {N_A1_C0_H,0x02},
741 {N_A1_C1_L,0x3c},
742 {N_A1_C1_H,0x06},
743 {N_A1_C2_L,0xa9},
744 {N_A1_C2_H,0x05},
745 {N_A2_C0_L,0x4f}, // Notch_A2, R = 0.94
746 {N_A2_C0_H,0x02},
747 {N_A2_C1_L,0x3c},
748 {N_A2_C1_H,0x06},
749 {N_A2_C2_L,0x8c},
750 {N_A2_C2_H,0x05},
751 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
752 {SOS12_C0_H,0x02},
753 {SOS12_C1_L,0x3c},
754 {SOS12_C1_H,0x06},
755 {SOS12_C2_L,0x00},
756 {SOS12_C2_H,0x02},
757 {SOS12_C3_L,0xa9},
758 {SOS12_C3_H,0x05},
759 {SOS12_C4_L,0x00},
760 {SOS12_C4_H,0x02},
761 {_END_OF_TBL_,0x00}, // PAL DK1 A2
762 };
763
764 MS_VIF_REG_TYPE VIF_PAL_DK2_A2[]=
765 {
766 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
767 {N_A1_C0_H,0x02},
768 {N_A1_C1_L,0x3c},
769 {N_A1_C1_H,0x06},
770 {N_A1_C2_L,0xa9},
771 {N_A1_C2_H,0x05},
772 {N_A2_C0_L,0x18}, // Notch_A2, R = 0.94
773 {N_A2_C0_H,0x02},
774 {N_A2_C1_L,0x3c},
775 {N_A2_C1_H,0x06},
776 {N_A2_C2_L,0xc6},
777 {N_A2_C2_H,0x05},
778 {SOS12_C0_L,0x34}, // SOS12, R = 0.96
779 {SOS12_C0_H,0x02},
780 {SOS12_C1_L,0x3c},
781 {SOS12_C1_H,0x06},
782 {SOS12_C2_L,0x00},
783 {SOS12_C2_H,0x02},
784 {SOS12_C3_L,0xa9},
785 {SOS12_C3_H,0x05},
786 {SOS12_C4_L,0x00},
787 {SOS12_C4_H,0x02},
788 {_END_OF_TBL_,0x00}, // PAL DK2 A2
789 };
790
791 MS_VIF_REG_TYPE VIF_PAL_DK2_NICAM[]=
792 {
793 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
794 {N_A1_C0_H,0x02},
795 {N_A1_C1_L,0x3c},
796 {N_A1_C1_H,0x06},
797 {N_A1_C2_L,0xa9},
798 {N_A1_C2_H,0x05},
799 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
800 {N_A2_C0_H,0x02},
801 {N_A2_C1_L,0x3c},
802 {N_A2_C1_H,0x06},
803 {N_A2_C2_L,0x5d},
804 {N_A2_C2_H,0x05},
805 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
806 {SOS12_C0_H,0x02},
807 {SOS12_C1_L,0x3c},
808 {SOS12_C1_H,0x06},
809 {SOS12_C2_L,0x00},
810 {SOS12_C2_H,0x02},
811 {SOS12_C3_L,0xa9},
812 {SOS12_C3_H,0x05},
813 {SOS12_C4_L,0x00},
814 {SOS12_C4_H,0x02},
815 {_END_OF_TBL_,0x00}, // PAL DK NICAM
816 };
817
818 MS_VIF_REG_TYPE VIF_SECAM_DK3_A2[]=
819 {
820 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
821 {N_A1_C0_H,0x02},
822 {N_A1_C1_L,0x3c},
823 {N_A1_C1_H,0x06},
824 {N_A1_C2_L,0xa9},
825 {N_A1_C2_H,0x05},
826 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
827 {N_A2_C0_H,0x02},
828 {N_A2_C1_L,0x3c},
829 {N_A2_C1_H,0x06},
830 {N_A2_C2_L,0x51},
831 {N_A2_C2_H,0x05},
832 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
833 {SOS12_C0_H,0x02},
834 {SOS12_C1_L,0x3c},
835 {SOS12_C1_H,0x06},
836 {SOS12_C2_L,0x00},
837 {SOS12_C2_H,0x02},
838 {SOS12_C3_L,0xa9},
839 {SOS12_C3_H,0x05},
840 {SOS12_C4_L,0x00},
841 {SOS12_C4_H,0x02},
842 {_END_OF_TBL_,0x00}, // PAL DK3 A2
843 };
844
845 MS_VIF_REG_TYPE VIF_GDE_BG_A2_NOTCH[]=
846 {
847 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
848 {N_A3_C0_H,0x02},
849 {N_A3_C1_L,0x3c},
850 {N_A3_C1_H,0x06},
851 {N_A3_C2_L,0x37},
852 {N_A3_C2_H,0x05},
853 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
854 {N_A4_C0_H,0x02},
855 {N_A4_C1_L,0x3c},
856 {N_A4_C1_H,0x06},
857 {N_A4_C2_L,0x51},
858 {N_A4_C2_H,0x05},
859 {N_A5_C0_L,0xad}, // Notch_A5, R = 0.96
860 {N_A5_C0_H,0x02},
861 {N_A5_C1_L,0x28},
862 {N_A5_C1_H,0x06},
863 {N_A5_C2_L,0x37},
864 {N_A5_C2_H,0x05},
865 {_END_OF_TBL_,0x00}, // PAL B/G A2
866 };
867
868 MS_VIF_REG_TYPE VIF_GDE_BG_NICAM_NOTCH[]=
869 {
870 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
871 {N_A3_C0_H,0x02},
872 {N_A3_C1_L,0x3c},
873 {N_A3_C1_H,0x06},
874 {N_A3_C2_L,0x37},
875 {N_A3_C2_H,0x05},
876 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
877 {N_A4_C0_H,0x02},
878 {N_A4_C1_L,0x3c},
879 {N_A4_C1_H,0x06},
880 {N_A4_C2_L,0x5d},
881 {N_A4_C2_H,0x05},
882 {N_A5_C0_L,0xad}, // Notch_A5, R = 0.96
883 {N_A5_C0_H,0x02},
884 {N_A5_C1_L,0x28},
885 {N_A5_C1_H,0x06},
886 {N_A5_C2_L,0x37},
887 {N_A5_C2_H,0x05},
888 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
889 };
890
891 MS_VIF_REG_TYPE VIF_GDE_I_NOTCH[]=
892 {
893 {N_A3_C0_L,0x6b}, // Notch_A3, R = 0.94
894 {N_A3_C0_H,0x02},
895 {N_A3_C1_L,0x3c},
896 {N_A3_C1_H,0x06},
897 {N_A3_C2_L,0x6e},
898 {N_A3_C2_H,0x05},
899 {N_A4_C0_L,0x2e}, // Notch_A4, R = 0.94
900 {N_A4_C0_H,0x02},
901 {N_A4_C1_L,0x3c},
902 {N_A4_C1_H,0x06},
903 {N_A4_C2_L,0xaf},
904 {N_A4_C2_H,0x05},
905 {N_A5_C0_L,0x78}, // Notch_A5, R = 0.96
906 {N_A5_C0_H,0x02},
907 {N_A5_C1_L,0x28},
908 {N_A5_C1_H,0x06},
909 {N_A5_C2_L,0x6e},
910 {N_A5_C2_H,0x05},
911 {_END_OF_TBL_,0x00}, // PAL I NICAM
912 };
913
914 MS_VIF_REG_TYPE VIF_GDE_DK1_NOTCH[]=
915 {
916 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
917 {N_A3_C0_H,0x02},
918 {N_A3_C1_L,0x3c},
919 {N_A3_C1_H,0x06},
920 {N_A3_C2_L,0xa9},
921 {N_A3_C2_H,0x05},
922 {N_A4_C0_L,0x4f}, // Notch_A4, R = 0.94
923 {N_A4_C0_H,0x02},
924 {N_A4_C1_L,0x3c},
925 {N_A4_C1_H,0x06},
926 {N_A4_C2_L,0x8c},
927 {N_A4_C2_H,0x05},
928 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
929 {N_A5_C0_H,0x02},
930 {N_A5_C1_L,0x28},
931 {N_A5_C1_H,0x06},
932 {N_A5_C2_L,0xa9},
933 {N_A5_C2_H,0x05},
934 {_END_OF_TBL_,0x00}, // PAL DK1 A2
935 };
936
937 MS_VIF_REG_TYPE VIF_GDE_DK2_NOTCH[]=
938 {
939 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
940 {N_A3_C0_H,0x02},
941 {N_A3_C1_L,0x3c},
942 {N_A3_C1_H,0x06},
943 {N_A3_C2_L,0xa9},
944 {N_A3_C2_H,0x05},
945 {N_A4_C0_L,0x18}, // Notch_A4, R = 0.94
946 {N_A4_C0_H,0x02},
947 {N_A4_C1_L,0x3c},
948 {N_A4_C1_H,0x06},
949 {N_A4_C2_L,0xc6},
950 {N_A4_C2_H,0x05},
951 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
952 {N_A5_C0_H,0x02},
953 {N_A5_C1_L,0x28},
954 {N_A5_C1_H,0x06},
955 {N_A5_C2_L,0xa9},
956 {N_A5_C2_H,0x05},
957 {_END_OF_TBL_,0x00}, // PAL DK2 A2
958 };
959
960 MS_VIF_REG_TYPE VIF_GDE_DK3_NOTCH[]=
961 {
962 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
963 {N_A3_C0_H,0x02},
964 {N_A3_C1_L,0x3c},
965 {N_A3_C1_H,0x06},
966 {N_A3_C2_L,0xa9},
967 {N_A3_C2_H,0x05},
968 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
969 {N_A4_C0_H,0x02},
970 {N_A4_C1_L,0x3c},
971 {N_A4_C1_H,0x06},
972 {N_A4_C2_L,0x51},
973 {N_A4_C2_H,0x05},
974 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
975 {N_A5_C0_H,0x02},
976 {N_A5_C1_L,0x28},
977 {N_A5_C1_H,0x06},
978 {N_A5_C2_L,0xa9},
979 {N_A5_C2_H,0x05},
980 {_END_OF_TBL_,0x00}, // PAL DK3 A2
981 };
982
983 MS_VIF_REG_TYPE VIF_GDE_DK_NICAM_NOTCH[]=
984 {
985 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
986 {N_A3_C0_H,0x02},
987 {N_A3_C1_L,0x3c},
988 {N_A3_C1_H,0x06},
989 {N_A3_C2_L,0xa9},
990 {N_A3_C2_H,0x05},
991 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
992 {N_A4_C0_H,0x02},
993 {N_A4_C1_L,0x3c},
994 {N_A4_C1_H,0x06},
995 {N_A4_C2_L,0x5d},
996 {N_A4_C2_H,0x05},
997 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
998 {N_A5_C0_H,0x02},
999 {N_A5_C1_L,0x28},
1000 {N_A5_C1_H,0x06},
1001 {N_A5_C2_L,0xa9},
1002 {N_A5_C2_H,0x05},
1003 {_END_OF_TBL_,0x00}, // PAL DK NICAM
1004 };
1005
1006 MS_VIF_REG_TYPE VIF_GDE_L_NICAM_NOTCH[]=
1007 {
1008 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
1009 {N_A3_C0_H,0x02},
1010 {N_A3_C1_L,0x3c},
1011 {N_A3_C1_H,0x06},
1012 {N_A3_C2_L,0xa9},
1013 {N_A3_C2_H,0x05},
1014 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
1015 {N_A4_C0_H,0x02},
1016 {N_A4_C1_L,0x3c},
1017 {N_A4_C1_H,0x06},
1018 {N_A4_C2_L,0x5d},
1019 {N_A4_C2_H,0x05},
1020 {N_A5_C0_L,0x40}, // Notch_A5, R = 0.96
1021 {N_A5_C0_H,0x02},
1022 {N_A5_C1_L,0x28},
1023 {N_A5_C1_H,0x06},
1024 {N_A5_C2_L,0xa9},
1025 {N_A5_C2_H,0x05},
1026 {_END_OF_TBL_,0x00}, // SECAM L NICAM
1027 };
1028
1029 MS_VIF_REG_TYPE VIF_GDE_MN_NOTCH[]=
1030 {
1031 {N_A3_C0_L,0x1c}, // Notch_A3 (0.98)
1032 {N_A3_C0_H,0x03},
1033 {N_A3_C1_L,0x14},
1034 {N_A3_C1_H,0x06},
1035 {N_A3_C2_L,0xd4},
1036 {N_A3_C2_H,0x04},
1037 {N_A4_C0_L,0xe8}, // Notch_A4, R = 0.94
1038 {N_A4_C0_H,0x02},
1039 {N_A4_C1_L,0x3c},
1040 {N_A4_C1_H,0x06},
1041 {N_A4_C2_L,0xe8},
1042 {N_A4_C2_H,0x04},
1043 {N_A5_C0_L,0x0c}, // Notch_A5, R = 0.96
1044 {N_A5_C0_H,0x03},
1045 {N_A5_C1_L,0x28},
1046 {N_A5_C1_H,0x06},
1047 {N_A5_C2_L,0xd4},
1048 {N_A5_C2_H,0x04},
1049 {_END_OF_TBL_,0x00}, // NTSC M/N
1050 };
1051 MS_VIF_REG_TYPE VIF_NTSC_MN_A2[]=
1052 {
1053 {N_A1_C0_L,0xfc}, // Notch_A1, R = 0.94
1054 {N_A1_C0_H,0x02},
1055 {N_A1_C1_L,0x3c},
1056 {N_A1_C1_H,0x06},
1057 {N_A1_C2_L,0xd4},
1058 {N_A1_C2_H,0x04},
1059 {N_A2_C0_L,0xe8}, // Notch_A2, R = 0.94
1060 {N_A2_C0_H,0x02},
1061 {N_A2_C1_L,0x3c},
1062 {N_A2_C1_H,0x06},
1063 {N_A2_C2_L,0xe8},
1064 {N_A2_C2_H,0x04},
1065 {SOS12_C0_L,0xfc}, // SOS12, R = 0.94
1066 {SOS12_C0_H,0x02},
1067 {SOS12_C1_L,0x3c},
1068 {SOS12_C1_H,0x06},
1069 {SOS12_C2_L,0x00},
1070 {SOS12_C2_H,0x02},
1071 {SOS12_C3_L,0xd4},
1072 {SOS12_C3_H,0x04},
1073 {SOS12_C4_L,0x00},
1074 {SOS12_C4_H,0x02},
1075 {_END_OF_TBL_,0x00}, // NTSC M/N
1076 };
1077 MS_VIF_REG_TYPE VIF_PAL_DK_LOWER_ACI[]=
1078 {
1079 {SOS11_C0_L,0x3a}, // SOS11 notch at 16.5MHz (0.94)
1080 {SOS11_C0_H,0x05},
1081 {SOS11_C1_L,0x3c},
1082 {SOS11_C1_H,0x06},
1083 {SOS11_C2_L,0x00},
1084 {SOS11_C2_H,0x02},
1085 {SOS11_C3_L,0xf3},
1086 {SOS11_C3_H,0x02},
1087 {SOS11_C4_L,0x00},
1088 {SOS11_C4_H,0x02},
1089 {_END_OF_TBL_,0x00},
1090 };
1091 MS_VIF_REG_TYPE VIF_PAL_I_LOWER_ACI[]=
1092 {
1093 {SOS11_C0_L,0x0d}, // SOS11 notch at 17MHz (0.94)
1094 {SOS11_C0_H,0x05},
1095 {SOS11_C1_L,0x3c},
1096 {SOS11_C1_H,0x06},
1097 {SOS11_C2_L,0x00},
1098 {SOS11_C2_H,0x02},
1099 {SOS11_C3_L,0x23},
1100 {SOS11_C3_H,0x03},
1101 {SOS11_C4_L,0x00},
1102 {SOS11_C4_H,0x02},
1103 {_END_OF_TBL_,0x00},
1104 };
1105 MS_VIF_REG_TYPE VIF_PAL_GH_LOWER_ACI[]=
1106 {
1107 {SOS11_C0_L,0xe4}, // SOS11 notch at 17.5MHz (0.94)
1108 {SOS11_C0_H,0x04},
1109 {SOS11_C1_L,0x3c},
1110 {SOS11_C1_H,0x06},
1111 {SOS11_C2_L,0x00},
1112 {SOS11_C2_H,0x02},
1113 {SOS11_C3_L,0x4f},
1114 {SOS11_C3_H,0x03},
1115 {SOS11_C4_L,0x00},
1116 {SOS11_C4_H,0x02},
1117 {_END_OF_TBL_,0x00},
1118 };
1119 MS_VIF_REG_TYPE VIF_PAL_B_LOWER_ACI[]=
1120 {
1121 {SOS11_C0_L,0x1C}, // SOS11 notch at 16.5MHz (0.98)
1122 {SOS11_C0_H,0x05},
1123 {SOS11_C1_L,0x14},
1124 {SOS11_C1_H,0x06},
1125 {SOS11_C2_L,0x00},
1126 {SOS11_C2_H,0x02},
1127 {SOS11_C3_L,0xF3},
1128 {SOS11_C3_H,0x02},
1129 {SOS11_C4_L,0x00},
1130 {SOS11_C4_H,0x02},
1131 {_END_OF_TBL_,0x00},
1132 };
1133
1134 MS_VIF_REG_TYPE VIF_NTSC_MN_LOWER_ACI[]=
1135 {
1136 {SOS11_C0_L,0x15}, // SOS11 notch at 16.5MHz
1137 {SOS11_C0_H,0x05},
1138 {SOS11_C1_L,0x0A},
1139 {SOS11_C1_H,0x06},
1140 {SOS11_C2_L,0x00},
1141 {SOS11_C2_H,0x02},
1142 {SOS11_C3_L,0xF3},
1143 {SOS11_C3_H,0x02},
1144 {SOS11_C4_L,0x00},
1145 {SOS11_C4_H,0x02},
1146 {_END_OF_TBL_,0x00},
1147 };
1148 MS_VIF_REG_TYPE VIF_PAL_DK_Audio_SingleSAW[]=
1149 {
1150 {SOS12_C0_L,0x0D}, // SOS12 notch at 8.5MHz
1151 {SOS12_C0_H,0x01},
1152 {SOS12_C1_L,0xB8},
1153 {SOS12_C1_H,0x06},
1154 {SOS12_C2_L,0x00},
1155 {SOS12_C2_H,0x02},
1156 {SOS12_C3_L,0xB0},
1157 {SOS12_C3_H,0x06},
1158 {SOS12_C4_L,0x00},
1159 {SOS12_C4_H,0x02},
1160 {_END_OF_TBL_,0x00},
1161 };
1162 MS_VIF_REG_TYPE VIF_PAL_GH_Audio_SingleSAW[]=
1163 {
1164 {SOS12_C0_L,0x9A}, // SOS12 notch at 9.5MHz
1165 {SOS12_C0_H,0x00},
1166 {SOS12_C1_L,0xB8},
1167 {SOS12_C1_H,0x06},
1168 {SOS12_C2_L,0x00},
1169 {SOS12_C2_H,0x02},
1170 {SOS12_C3_L,0x40},
1171 {SOS12_C3_H,0x07},
1172 {SOS12_C4_L,0x00},
1173 {SOS12_C4_H,0x02},
1174 {_END_OF_TBL_,0x00},
1175 };
1176 MS_VIF_REG_TYPE VIF_PAL_I_Audio_SingleSAW[]=
1177 {
1178 {SOS12_C0_L,0xD4}, // SOS12 notch at 9MHz
1179 {SOS12_C0_H,0x00},
1180 {SOS12_C1_L,0xB8},
1181 {SOS12_C1_H,0x06},
1182 {SOS12_C2_L,0x00},
1183 {SOS12_C2_H,0x02},
1184 {SOS12_C3_L,0xF7},
1185 {SOS12_C3_H,0x06},
1186 {SOS12_C4_L,0x00},
1187 {SOS12_C4_H,0x02},
1188 {_END_OF_TBL_,0x00},
1189 };
1190
1191 MS_VIF_REG_TYPE VIF_NULL_LOWER_ACI[]=
1192 {
1193 {SOS11_C0_L,0x00}, // SOS11
1194 {SOS11_C0_H,0x00},
1195 {SOS11_C1_L,0x00},
1196 {SOS11_C1_H,0x00},
1197 {SOS11_C2_L,0x00},
1198 {SOS11_C2_H,0x00},
1199 {SOS11_C3_L,0x00},
1200 {SOS11_C3_H,0x00},
1201 {SOS11_C4_L,0x00},
1202 {SOS11_C4_H,0x02},
1203 {_END_OF_TBL_,0x00},
1204 };
1205
1206 MS_VIF_REG_TYPE VIF_CR_IIR_LPF1[]=
1207 {
1208 {CR_IIR_COEF_G,0x02},
1209 {CR_IIR_COEF_G+1,0x00},
1210 {CR_IIR_COEF_A1,0xfc},
1211 {CR_IIR_COEF_A1+1,0x01},
1212 {CR_IIR_COEF_A2,0x00},
1213 {CR_IIR_COEF_A2+1,0x00},
1214 {CR_IIR_COEF_B1,0x00},
1215 {CR_IIR_COEF_B1+1,0x02},
1216 {CR_IIR_COEF_B2,0x00},
1217 {CR_IIR_COEF_B2+1,0x00},
1218 {_END_OF_TBL_,0x00},
1219 };
1220 MS_VIF_REG_TYPE VIF_CR_IIR_LPF2[]=
1221 {
1222 {CR_IIR_COEF_G,0x02},
1223 {CR_IIR_COEF_G+1,0x00},
1224 {CR_IIR_COEF_A1,0xd6},
1225 {CR_IIR_COEF_A1+1,0x03},
1226 {CR_IIR_COEF_A2,0x27},
1227 {CR_IIR_COEF_A2+1,0x06},
1228 {CR_IIR_COEF_B1,0x5b},
1229 {CR_IIR_COEF_B1+1,0x06},
1230 {CR_IIR_COEF_B2,0x00},
1231 {CR_IIR_COEF_B2+1,0x02},
1232 {_END_OF_TBL_,0x00},
1233 };
1234
1235
1236 U16 VIF_PAL_EQ_CO_A_REJ[]=
1237 {
1238 0x0009,
1239 0x0003,
1240 0x000B,
1241 0x1FE1,
1242 0x002F,
1243 0x1FD0,
1244 0x001F,
1245 0x1FF2,
1246 0x001A,
1247 0x1FB4,
1248 0x008A,
1249 0x1F5E,
1250 0x0077,
1251 0x1FDC,
1252 0x1FFC,
1253 0x1FBB,
1254 0x00F1,
1255 0x1E79,
1256 0x0165,
1257 0x1FC9,
1258 0x1E4C,
1259 0x037C,
1260 0x0BCA,
1261 0x037C,
1262 0x1E4C,
1263 0x1FC9,
1264 0x0165,
1265 0x1E79,
1266 0x00F1,
1267 0x1FBB,
1268 0x1FFC,
1269 0x1FDC,
1270 0x0077,
1271 0x1F5E,
1272 0x008A,
1273 0x1FB4,
1274 0x001A,
1275 0x1FF2,
1276 0x001F,
1277 0x1FD0,
1278 0x002F,
1279 0x1FE1,
1280 0x000B,
1281 0x0003,
1282 0x0009,
1283 0x0000
1284 };
1285 U16 VIF_NTSC_EQ_CO_A_REJ[]=
1286 {
1287 0x001B,
1288 0x1FEB,
1289 0x0001,
1290 0x0000,
1291 0x0024,
1292 0x1FBF,
1293 0x0027,
1294 0x1FFE,
1295 0x0025,
1296 0x1F87,
1297 0x0083,
1298 0x1FD6,
1299 0x0009,
1300 0x1F78,
1301 0x0106,
1302 0x1F5A,
1303 0x1FD9,
1304 0x1FEF,
1305 0x017E,
1306 0x1DF8,
1307 0x1FB4,
1308 0x044E,
1309 0x09AF,
1310 0x044E,
1311 0x1FB4,
1312 0x1DF8,
1313 0x017E,
1314 0x1FEF,
1315 0x1FD9,
1316 0x1F5A,
1317 0x0106,
1318 0x1F78,
1319 0x0009,
1320 0x1FD6,
1321 0x0083,
1322 0x1F87,
1323 0x0025,
1324 0x1FFE,
1325 0x0027,
1326 0x1FBF,
1327 0x0024,
1328 0x0000,
1329 0x0001,
1330 0x1FEB,
1331 0x001B,
1332 0x0000
1333 };
1334
msWriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1335 void msWriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1336 {
1337 RIU_WriteByteMask(u32Reg, u8Val, u8Mask);
1338 msVifLoad();
1339 }
1340
msWriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1341 void msWriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1342 {
1343 RIU_WriteRegBit(u32Reg, bEnable, u8Mask);
1344 msVifLoad();
1345 }
1346
msWriteByte(U32 u32Reg,U8 u8Val)1347 void msWriteByte(U32 u32Reg, U8 u8Val )
1348 {
1349 RIU_WriteByte(u32Reg,u8Val);
1350 msVifLoad();
1351 }
1352
HAL_VIF_WriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1353 void HAL_VIF_WriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1354 {
1355 msWriteByteMask(u32Reg, u8Val, u8Mask);
1356 }
1357
HAL_VIF_WriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1358 void HAL_VIF_WriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1359 {
1360 msWriteBit(u32Reg, bEnable, u8Mask);
1361 }
1362
HAL_VIF_WriteByte(U32 u32Reg,U8 u8Val)1363 void HAL_VIF_WriteByte(U32 u32Reg, U8 u8Val )
1364 {
1365 msWriteByte(u32Reg, u8Val);
1366 }
1367
HAL_VIF_ReadByte(U32 u32Reg)1368 U8 HAL_VIF_ReadByte(U32 u32Reg )
1369 {
1370 return msReadByte(u32Reg);
1371 }
1372
msWriteRegsTbl(MS_VIF_REG_TYPE * pRegTable)1373 void msWriteRegsTbl(MS_VIF_REG_TYPE *pRegTable)
1374 {
1375 U16 u16Dummy;
1376 U32 u32Address;
1377 U8 u8Value;
1378
1379 u16Dummy = 2000;
1380
1381 do
1382 {
1383 u32Address = pRegTable->u32Address;
1384 u8Value = pRegTable->u8Value;
1385 if (u32Address == 0xFFFF) // check end of table
1386 break;
1387 RIU_WriteByte(u32Address, u8Value);
1388 pRegTable++;
1389 } while (--u16Dummy > 0);
1390 msVifLoad();
1391 }
1392
HAL_VIF_RegInit(void)1393 void HAL_VIF_RegInit (void)
1394 {
1395 MS_PHY phyNonPMBankSize, phyPMBankSize;
1396 MS_VIRT virtNonPMBank, virtPMBank;
1397
1398 HALVIFDBG(printf("\r\nHAL_VIF_RegInit()"));
1399 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_VIF))
1400 {
1401 printf("\r\nIOMap failure to get MAP_NONPM_BANK");
1402 virtNonPMBank = BASEADDR_RIU; // TODO what to do if failed??
1403 }
1404 else
1405 {
1406 HALVIFDBG(printf("\r\nMS_MODULE_VIF base = 0x%lX, length = %lu", virtNonPMBank, phyNonPMBankSize));
1407 }
1408
1409 _hal_VIF.virtVIFBaseAddr = virtNonPMBank;
1410 _hal_VIF.bBaseAddrInitialized = 1;
1411
1412 if (!MDrv_MMIO_GetBASE( &virtPMBank, &phyPMBankSize, MS_MODULE_PM))
1413 {
1414 printf("\r\nIOMap failure to get MAP_PM_BANK");
1415 virtPMBank = (VIRT)BASEADDR_RIU; // TODO what to do if failed??
1416 }
1417 else
1418 {
1419 HALVIFDBG(printf("\r\nMS_MODULE_PM base = 0x%lX, length = %lu", virtPMBank, phyPMBankSize));
1420 }
1421 }
1422
1423
HAL_VIF_SetClock(BOOL bEnable)1424 void HAL_VIF_SetClock(BOOL bEnable)
1425 {
1426 HALVIFDBG(printf("\r\nHAL_VIF_SetClock=%d",bEnable));
1427
1428 //bEnable = (bEnable) ? 0:1; // 0 means enable
1429 }
1430
msVifAdcInitial(void)1431 void msVifAdcInitial(void)
1432 {
1433 HALVIFDBG(printf("\r\nmsVifAdcInitial()"));
1434
1435 if (!_hal_VIF.bBaseAddrInitialized) return ;
1436
1437 RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1)
1438
1439 // Digital setting
1440 // SRAM Power Control
1441 RIU_WriteByte(0x12090L, 0x00);
1442 RIU_WriteByte(0x12091L, 0x5A);
1443 // ADC clock
1444 RIU_WriteByte(0x11F0AL, 0x00); // ADC_CLK
1445 RIU_WriteByte(0x11F0BL, 0x00);
1446 RIU_WriteByte(0x3314L, 0x04); // ADC clock
1447 RIU_WriteByte(0x3315L, 0x00); // CLK_DVBTC_INNC clock
1448 // VIF clock
1449 RIU_WriteByte(0x331AL, 0x04); // MPLLDIV10/2=43MHz
1450 RIU_WriteByte(0x331BL, 0x04); // MPLLDIV10/2=43MHz
1451 RIU_WriteByte(0x11F1CL, 0x00);
1452 RIU_WriteByte(0x11F1DL, 0x00);
1453 RIU_WriteByte(0x11F2AL, 0x00); // DAGC1/2 SRAM MUX
1454 RIU_WriteByte(0x11F2BL, 0x00);
1455 // Data path
1456 RIU_WriteByte(0x12000L, 0x10);
1457 RIU_WriteByte(0x12001L, 0x11);
1458 RIU_WriteByte(0x12002L, 0x74); // Enable VIF, DVBT, ATSC and VIF reset
1459 RIU_WriteByte(0x12003L, 0x00);
1460 RIU_WriteByte(0x12000L, 0x00);
1461 RIU_WriteByte(0x12001L, 0x11);
1462 RIU_WriteByte(0x12002L, 0x14); // Enable VIF
1463 RIU_WriteByte(0x12003L, 0x00);
1464 RIU_WriteByte(0x12060L, 0x04); // Disable ADC sign bit
1465 RIU_WriteByte(0x12061L, 0x00);
1466 RIU_WriteByte(0x12064L, 0x00);
1467 RIU_WriteByte(0x12065L, 0x00);
1468 RIU_WriteByte(0x12066L, 0x00);
1469 RIU_WriteByte(0x12067L, 0x00);
1470 RIU_WriteByte(0x120A0L, 0x01); // VIF use DVB SRAM and FIR
1471 // SRAM share
1472 RIU_WriteByte(0x11F18L, 0x01);
1473 RIU_WriteByte(0x11F19L, 0x40);
1474 RIU_WriteByte(0x11F84L, 0x00);
1475 RIU_WriteByte(0x11F85L, 0x00);
1476 RIU_WriteByte(0x11F86L, 0x00);
1477 RIU_WriteByte(0x11F87L, 0x00);
1478 // FIR share
1479 RIU_WriteByte(0x11F22L, 0x11);
1480 RIU_WriteByte(0x11F23L, 0x18);
1481
1482 // Analog setting
1483 RIU_WriteByteMask(0x12879L, 0x00, 0xF0); // Enable LDOS
1484 RIU_WriteRegBit(0x12840L, 0, _BIT4); // Ref Enable
1485 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG
1486 RIU_WriteByte(0x12802L, 0x40); // VIF path, Bypass PGA
1487 RIU_WriteByte(0x12803L, 0x04); // Mux selection
1488 RIU_WriteByte(0x12816L, 0x05); // Set ADC gain is 1
1489 RIU_WriteByte(0x12817L, 0x05);
1490 RIU_WriteByte(0x1281EL, 0x80); // Calibration buffer
1491 RIU_WriteByte(0x1281FL, 0x00);
1492
1493 if(VIF_IS_ADC_48MHz == 0)
1494 {
1495 // 144MHz case
1496 RIU_WriteByte(0x12860L, 0x00); // DMPLL post divider
1497 RIU_WriteByte(0x12861L, 0x06);
1498 }
1499 else
1500 {
1501 // 48MHz case
1502 RIU_WriteByte(0x12860L, 0x00); // DMPLL post divider
1503 RIU_WriteByte(0x12861L, 0x12);
1504 }
1505
1506 RIU_WriteByte(0x12864L, 0x00); // MPLL_output_div_second
1507 RIU_WriteByte(0x12865L, 0x00);
1508 RIU_WriteByte(0x1287EL, 0x00); // SIF CLK select
1509 RIU_WriteByte(0x1287FL, 0x00);
1510 RIU_WriteByte(0x12866L, 0x01); // loop divider
1511 RIU_WriteByte(0x12867L, 0x12);
1512 RIU_WriteByte(0x1286AL, 0x83); // PLL power down
1513 RIU_WriteByte(0x1286BL, 0x00);
1514 RIU_WriteByte(0x1286AL, 0x03); // PLL power up
1515 RIU_WriteByte(0x1286BL, 0x00);
1516 RIU_WriteByte(0x1286CL, 0x10); // AGC enable
1517 RIU_WriteByte(0x1286DL, 0x00);
1518 RIU_WriteByte(0x12818L, 0x02); // ADC power down
1519 RIU_WriteByte(0x12819L, 0x00);
1520
1521 if(VIFInitialIn_inst.VifSawArch == NO_SAW_DIF)
1522 VIFInitialIn_inst.VifSawArch = NO_SAW;
1523
1524 HAL_VIF_Delay1ms(1);
1525
1526 // RFAGC and IFAGC control (ADC)
1527 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC
1528 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC
1529 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1);
1530 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5);
1531 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
1532 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable
1533 else
1534 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable
1535 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable
1536
1537 // RFAGC and IFAGC control (RF)
1538 msWriteBit(RFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1539 msWriteBit(RFAGC_DITHER_EN, 1, _BIT7); // dither disable
1540 msWriteBit(RFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1541 msWriteBit(OREN_RFAGC, 0, _BIT5); // RFAGC 0: BB control; 1: I2C control
1542
1543 msWriteBit(IFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1544 msWriteBit(IFAGC_DITHER_EN, 1, _BIT7); // dither disable
1545 msWriteBit(IFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1546 msWriteBit(OREN_IFAGC, 0, _BIT6); // RFAGC 0: BB control; 1: I2C control
1547
1548 msWriteBit(OREN_PGA1_V, 0, _BIT3); // Video PGA1 0: BB control; 1: I2C control
1549 msWriteBit(OREN_PGA2_V, 0, _BIT2); // Video PGA2 0: BB control; 1: I2C control
1550 msWriteBit(OREN_PGA1_S, 0, _BIT1); // Audio PGA1 0: BB control; 1: I2C control
1551 msWriteBit(OREN_PGA2_S, 0, _BIT0); // Audio PGA2 0: BB control; 1: I2C control
1552
1553 // EQ BYPASS
1554 msWriteBit(BYPASS_EQFIR, 1, _BIT0);
1555 }
1556
1557 // For API
msVifSetIfFreq(IfFrequencyType ucIfFreq)1558 void msVifSetIfFreq(IfFrequencyType ucIfFreq)
1559 {
1560 HALVIFDBG(printf("\r\nmsVifSetIfFreq() ucIfFreq=%d",ucIfFreq));
1561
1562 if (!_hal_VIF.bBaseAddrInitialized) return ;
1563
1564 //g_FreqType = ucIfFreq; // 0x1121_D2
1565 msWriteByte(VIF_RF_RESERVED_1, ucIfFreq);
1566
1567 // VifShiftClk : 0x1121_D3
1568 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
1569
1570 // cvbs output
1571 msWriteBit(VIFDAC_ENABLE, 1, _BIT3); // enable vifdac
1572
1573 // for China descrambler box
1574 if (VIFInitialIn_inst.ChinaDescramblerBox == 0)
1575 {
1576 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1577 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1578 }
1579 else
1580 {
1581 msWriteByteMask(VIFDAC_OUT_SEL, 0x04, 0x07); // 0: cvbs output; 4: debug bus
1582 msWriteBit(DEBUG2_EN, 1, _BIT7); // select debug2 data
1583 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1584
1585 if(VIFInitialIn_inst.ChinaDescramblerBox == 1)
1586 {
1587 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1588 msWriteByte(DEBUG_PORT, 0x84); // selsect CVBS output after Notch_A2 filter
1589 }
1590 else if(VIFInitialIn_inst.ChinaDescramblerBox == 2)
1591 {
1592 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1593 msWriteByte(DEBUG_PORT, 0x98); // select CVBS output after IMAGE_IIR
1594 }
1595 else if (VIFInitialIn_inst.ChinaDescramblerBox == 3)
1596 {
1597 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1598 msWriteByte(DEBUG_PORT, 0x8A); // select CVBS output after IMAGE_REJ1
1599 }
1600 else if (VIFInitialIn_inst.ChinaDescramblerBox == 4)
1601 {
1602 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1603 msWriteByte(DEBUG_PORT, 0x88); // select CVBS output after ACI_REJ
1604 }
1605 else if (VIFInitialIn_inst.ChinaDescramblerBox == 5)
1606 {
1607 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1608 msWriteByte(DEBUG_PORT, 0x86); // select CVBS output after MIXER_OUT_I
1609 }
1610 else if (VIFInitialIn_inst.ChinaDescramblerBox == 6)
1611 {
1612 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1613 msWriteByte(DEBUG_PORT, 0x8B); // select CVBS output after IMAGE_REJ2
1614 }
1615 else
1616 {
1617 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1618 msWriteBit(DEBUG2_EN, 0, _BIT7); // select debug2 data
1619 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1620 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1621 }
1622 }
1623
1624 if (VIFInitialIn_inst.VifTunerType == 1)
1625 {
1626 // silicon tuner
1627 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1628 msWriteByte(IF_RATE+1, 0x00);
1629 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1630 }
1631 else if (VIFInitialIn_inst.VifTunerType == 2)
1632 {
1633 // FM tuner
1634 if(VIFInitialIn_inst.VifSawArch == SILICON_TUNER)
1635 {
1636 // silicon tuner
1637 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1638 msWriteByte(IF_RATE+1, 0x00);
1639 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1640 }
1641 }
1642 else
1643 {
1644 switch(ucIfFreq)
1645 {
1646 case IF_FREQ_3395:
1647 msWriteByte(IF_RATE, 0x44); // IF rate for -48.9 MHz // HEX [ (IF/144) * 2^22]
1648 msWriteByte(IF_RATE+1, 0x44);
1649 msWriteByteMask(IF_RATE+2, 0x2A, 0x3F);
1650 break;
1651 case IF_FREQ_3800:
1652 if (VifShiftClk/*g_VifShiftClk*/ == 1)
1653 {
1654 msWriteByte(0x12866L, 0x00);//loop divider
1655 msWriteByte(0x12867L, 0x23);
1656
1657 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
1658 msWriteByte(IF_RATE+1, 0x83);
1659 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1660 }
1661 else if(VifShiftClk/*g_VifShiftClk*/ == 2)
1662 {
1663 msWriteByte(0x12866L, 0x00);//loop divider
1664 msWriteByte(0x12867L, 0x25);
1665
1666 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
1667 msWriteByte(IF_RATE+1, 0xF2);
1668 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
1669 }
1670 else
1671 {
1672 msWriteByte(0x12866L, 0x00);//loop divider
1673 msWriteByte(0x12867L, 0x24);
1674
1675 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
1676 msWriteByte(IF_RATE+1, 0x38);
1677 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1678 }
1679 break;
1680 case IF_FREQ_3890:
1681 msWriteByte(IF_RATE, 0x49); // IF rate for 23.9 MHz
1682 msWriteByte(IF_RATE+1, 0x9F);
1683 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1684 break;
1685 case IF_FREQ_3950:
1686 msWriteByte(IF_RATE, 0x8E); // IF rate for 24.5 MHz
1687 msWriteByte(IF_RATE+1, 0xE3);
1688 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1689 break;
1690 case IF_FREQ_4575:
1691 msWriteByte(IF_RATE, 0xAA); // IF rate for 30.75 MHz
1692 msWriteByte(IF_RATE+1, 0xAA);
1693 msWriteByteMask(IF_RATE+2, 0x0D, 0x3F);
1694 break;
1695 case IF_FREQ_5875:
1696 msWriteByte(IF_RATE, 0xC7); // IF rate for 43.75 MHz
1697 msWriteByte(IF_RATE+1, 0x71);
1698 msWriteByteMask(IF_RATE+2, 0x13, 0x3F);
1699 break;
1700 default:
1701 break;
1702 }
1703 }
1704 }
1705
msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem,FrequencyBand frequencyRange)1706 void msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem, FrequencyBand frequencyRange)
1707 {
1708 BYTE VifPeakingFilter=0, VifYcDelayFilter=0, VifGroupDelayFilter=0;
1709
1710 if (!_hal_VIF.bBaseAddrInitialized) return ;
1711
1712 switch (ucSoundSystem)
1713 {
1714 case VIF_SOUND_B:
1715 case VIF_SOUND_B_NICAM:
1716 if (frequencyRange==FREQ_VHF_L)
1717 {
1718 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_L;
1719 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_L;
1720 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_L;
1721 }
1722 else if (frequencyRange==FREQ_VHF_H)
1723 {
1724 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_H;
1725 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_H;
1726 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_H;
1727 }
1728 else if (frequencyRange==FREQ_UHF)
1729 {
1730 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_UHF;
1731 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_UHF;
1732 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_UHF;
1733 }
1734 else
1735 printf("\r\n ERROR msVifGroupDelayFilter B frequencyRange=%d", frequencyRange);
1736 break;
1737
1738 case VIF_SOUND_GH:
1739 case VIF_SOUND_GH_NICAM:
1740 if (frequencyRange==FREQ_VHF_L)
1741 {
1742 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_L;
1743 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_L;
1744 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_L;
1745 }
1746 else if (frequencyRange==FREQ_VHF_H)
1747 {
1748 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_H;
1749 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_H;
1750 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_H;
1751 }
1752 else if (frequencyRange==FREQ_UHF)
1753 {
1754 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_UHF;
1755 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_UHF;
1756 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_UHF;
1757 }
1758 else
1759 printf("\r\n ERROR msVifGroupDelayFilter GH frequencyRange=%d", frequencyRange);
1760 break;
1761
1762 case VIF_SOUND_I:
1763 if (frequencyRange==FREQ_VHF_L)
1764 {
1765 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_L;
1766 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_L;
1767 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_L;
1768 }
1769 else if (frequencyRange==FREQ_VHF_H)
1770 {
1771 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_H;
1772 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_H;
1773 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_H;
1774 }
1775 else if (frequencyRange==FREQ_UHF)
1776 {
1777 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_UHF;
1778 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_UHF;
1779 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_UHF;
1780 }
1781 else
1782 printf("\r\n ERROR msVifGroupDelayFilter I frequencyRange=%d", frequencyRange);
1783 break;
1784
1785 case VIF_SOUND_DK1:
1786 case VIF_SOUND_DK2:
1787 case VIF_SOUND_DK3:
1788 case VIF_SOUND_DK_NICAM:
1789 if (frequencyRange==FREQ_VHF_L)
1790 {
1791 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_L;
1792 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_L;
1793 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_L;
1794 }
1795 else if (frequencyRange==FREQ_VHF_H)
1796 {
1797 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_H;
1798 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_H;
1799 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_H;
1800 }
1801 else if (frequencyRange==FREQ_UHF)
1802 {
1803 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_UHF;
1804 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_UHF;
1805 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_UHF;
1806 }
1807 else
1808 printf("\r\n ERROR msVifGroupDelayFilter DK frequencyRange=%d", frequencyRange);
1809 break;
1810
1811 case VIF_SOUND_L:
1812 if (frequencyRange==FREQ_VHF_L)
1813 {
1814 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_L;
1815 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_L;
1816 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_L;
1817 }
1818 else if (frequencyRange==FREQ_VHF_H)
1819 {
1820 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_H;
1821 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_H;
1822 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_H;
1823 }
1824 else if (frequencyRange==FREQ_UHF)
1825 {
1826 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_UHF;
1827 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_UHF;
1828 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_UHF;
1829 }
1830 else
1831 printf("\r\n ERROR msVifGroupDelayFilter L frequencyRange=%d", frequencyRange);
1832 break;
1833
1834 case VIF_SOUND_LL:
1835 if (frequencyRange==FREQ_VHF_L)
1836 {
1837 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_L;
1838 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_L;
1839 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_L;
1840 }
1841 else if (frequencyRange==FREQ_VHF_H)
1842 {
1843 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_H;
1844 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_H;
1845 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_H;
1846 }
1847 else if (frequencyRange==FREQ_UHF)
1848 {
1849 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_UHF;
1850 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_UHF;
1851 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_UHF;
1852 }
1853 else
1854 printf("\r\n ERROR msVifGroupDelayFilter LL frequencyRange=%d", frequencyRange);
1855 break;
1856
1857 case VIF_SOUND_MN:
1858 if (frequencyRange==FREQ_VHF_L)
1859 {
1860 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_L;
1861 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_L;
1862 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_L;
1863 }
1864 else if (frequencyRange==FREQ_VHF_H)
1865 {
1866 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_H;
1867 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_H;
1868 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_H;
1869 }
1870 else if (frequencyRange==FREQ_UHF)
1871 {
1872 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_UHF;
1873 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_UHF;
1874 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_UHF;
1875 }
1876 else
1877 printf("\r\n ERROR msVifGroupDelayFilter MN frequencyRange=%d", frequencyRange);
1878 break;
1879
1880 default:
1881 printf("\r\n Error msVifGroupDelayFilter ucSoundSystem=%d",ucSoundSystem);
1882 break;
1883 }
1884
1885 HALVIFDBG(printf("\r\nmsVifGroupDelayFilter() VifPeakingFilter=%d",VifPeakingFilter));
1886 HALVIFDBG(printf(" VifYcDelayFilter=%d VifGroupDelayFilter=%d",VifYcDelayFilter, VifGroupDelayFilter));
1887
1888 if (VifPeakingFilter == 0x00)
1889 {
1890 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_NULL);
1891 }
1892 else if (VifPeakingFilter == 0x01)
1893 {
1894 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_1dB);
1895 }
1896 else if (VifPeakingFilter == 0x02)
1897 {
1898 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_2dB);
1899 }
1900 else if (VifPeakingFilter == 0x03)
1901 {
1902 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB);
1903 }
1904 else if (VifPeakingFilter == 0x04)
1905 {
1906 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB);
1907 }
1908 else if (VifPeakingFilter == 0x05)
1909 {
1910 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB_VSB);
1911 }
1912 else if (VifPeakingFilter == 0x06)
1913 {
1914 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB_VSB);
1915 }
1916 else if (VifPeakingFilter == 0x07)
1917 {
1918 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_5dB_VSB);
1919 }
1920 else if (VifPeakingFilter == 0x80)
1921 {
1922 msWriteByte(SOS21_C0_L, VIFInitialIn_inst.VifSos21FilterC0); // SOS21 (user define)
1923 msWriteByteMask(SOS21_C0_H, VIFInitialIn_inst.VifSos21FilterC0>>8, 0x07);
1924 msWriteByte(SOS21_C1_L, VIFInitialIn_inst.VifSos21FilterC1);
1925 msWriteByteMask(SOS21_C1_H, VIFInitialIn_inst.VifSos21FilterC1>>8, 0x07);
1926 msWriteByte(SOS21_C2_L, VIFInitialIn_inst.VifSos21FilterC2);
1927 msWriteByteMask(SOS21_C2_H, VIFInitialIn_inst.VifSos21FilterC2>>8, 0x07);
1928 msWriteByte(SOS21_C3_L, VIFInitialIn_inst.VifSos21FilterC3);
1929 msWriteByteMask(SOS21_C3_H, VIFInitialIn_inst.VifSos21FilterC3>>8, 0x07);
1930 msWriteByte(SOS21_C4_L, VIFInitialIn_inst.VifSos21FilterC4);
1931 msWriteByteMask(SOS21_C4_H, VIFInitialIn_inst.VifSos21FilterC4>>8, 0x07);
1932 }
1933
1934 if (VifYcDelayFilter == 0x00)
1935 {
1936 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_NULL);
1937 }
1938 else if (VifYcDelayFilter == 0x01)
1939 {
1940 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_VSB);
1941 }
1942 else if (VifYcDelayFilter == 0x80)
1943 {
1944 msWriteByte(SOS22_C0_L, VIFInitialIn_inst.VifSos22FilterC0); // SOS22 (user define)
1945 msWriteByteMask(SOS22_C0_H, VIFInitialIn_inst.VifSos22FilterC0>>8, 0x07);
1946 msWriteByte(SOS22_C1_L, VIFInitialIn_inst.VifSos22FilterC1);
1947 msWriteByteMask(SOS22_C1_H, VIFInitialIn_inst.VifSos22FilterC1>>8, 0x07);
1948 msWriteByte(SOS22_C2_L, VIFInitialIn_inst.VifSos22FilterC2);
1949 msWriteByteMask(SOS22_C2_H, VIFInitialIn_inst.VifSos22FilterC2>>8, 0x07);
1950 msWriteByte(SOS22_C3_L, VIFInitialIn_inst.VifSos22FilterC3);
1951 msWriteByteMask(SOS22_C3_H, VIFInitialIn_inst.VifSos22FilterC3>>8, 0x07);
1952 msWriteByte(SOS22_C4_L, VIFInitialIn_inst.VifSos22FilterC4);
1953 msWriteByteMask(SOS22_C4_H, VIFInitialIn_inst.VifSos22FilterC4>>8, 0x07);
1954 }
1955
1956 if (VifGroupDelayFilter == 0x00)
1957 {
1958 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_NULL);
1959 }
1960 else if (VifGroupDelayFilter == 0x01)
1961 {
1962 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_LG);
1963 }
1964 else if (VifGroupDelayFilter == 0x02)
1965 {
1966 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_Philips);
1967 }
1968 else if (VifGroupDelayFilter == 0x03)
1969 {
1970 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_R);
1971 }
1972 else if (VifGroupDelayFilter == 0x04)
1973 {
1974 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_L);
1975 }
1976 else if (VifGroupDelayFilter == 0x05)
1977 {
1978 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_R);
1979 }
1980 else if (VifGroupDelayFilter == 0x06)
1981 {
1982 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_L);
1983 }
1984 else if (VifGroupDelayFilter == 0x80)
1985 {
1986 msWriteByte(SOS31_C0_L, VIFInitialIn_inst.VifSos31FilterC0); // SOS31 (user define)
1987 msWriteByteMask(SOS31_C0_H, VIFInitialIn_inst.VifSos31FilterC0>>8, 0x07);
1988 msWriteByte(SOS31_C1_L, VIFInitialIn_inst.VifSos31FilterC1);
1989 msWriteByteMask(SOS31_C1_H, VIFInitialIn_inst.VifSos31FilterC1>>8, 0x07);
1990 msWriteByte(SOS31_C2_L, VIFInitialIn_inst.VifSos31FilterC2);
1991 msWriteByteMask(SOS31_C2_H, VIFInitialIn_inst.VifSos31FilterC2>>8, 0x07);
1992 msWriteByte(SOS31_C3_L, VIFInitialIn_inst.VifSos31FilterC3);
1993 msWriteByteMask(SOS31_C3_H, VIFInitialIn_inst.VifSos31FilterC3>>8, 0x07);
1994 msWriteByte(SOS31_C4_L, VIFInitialIn_inst.VifSos31FilterC4);
1995 msWriteByteMask(SOS31_C4_H, VIFInitialIn_inst.VifSos31FilterC4>>8, 0x07);
1996 msWriteByte(SOS32_C0_L, VIFInitialIn_inst.VifSos32FilterC0); // SOS32 (user define)
1997 msWriteByteMask(SOS32_C0_H, VIFInitialIn_inst.VifSos32FilterC0>>8, 0x07);
1998 msWriteByte(SOS32_C1_L, VIFInitialIn_inst.VifSos32FilterC1);
1999 msWriteByteMask(SOS32_C1_H, VIFInitialIn_inst.VifSos32FilterC1>>8, 0x07);
2000 msWriteByte(SOS32_C2_L, VIFInitialIn_inst.VifSos32FilterC2);
2001 msWriteByteMask(SOS32_C2_H, VIFInitialIn_inst.VifSos32FilterC2>>8, 0x07);
2002 msWriteByte(SOS32_C3_L, VIFInitialIn_inst.VifSos32FilterC3);
2003 msWriteByteMask(SOS32_C3_H, VIFInitialIn_inst.VifSos32FilterC3>>8, 0x07);
2004 msWriteByte(SOS32_C4_L, VIFInitialIn_inst.VifSos32FilterC4);
2005 msWriteByteMask(SOS32_C4_H, VIFInitialIn_inst.VifSos32FilterC4>>8, 0x07);
2006 /*
2007 msWriteByte(SOS33_C0_L, sVIFSOS33.Vif_SOS_33_C0); // SOS33 (user define)
2008 msWriteByteMask(SOS33_C0_H, sVIFSOS33.Vif_SOS_33_C0>>8, 0x07);
2009 msWriteByte(SOS33_C1_L, sVIFSOS33.Vif_SOS_33_C1);
2010 msWriteByteMask(SOS33_C1_H, sVIFSOS33.Vif_SOS_33_C1>>8, 0x07);
2011 msWriteByte(SOS33_C2_L, sVIFSOS33.Vif_SOS_33_C2);
2012 msWriteByteMask(SOS33_C2_H, sVIFSOS33.Vif_SOS_33_C2>>8, 0x07);
2013 msWriteByte(SOS33_C3_L, sVIFSOS33.Vif_SOS_33_C3);
2014 msWriteByteMask(SOS33_C3_H, sVIFSOS33.Vif_SOS_33_C3>>8, 0x07);
2015 msWriteByte(SOS33_C4_L, sVIFSOS33.Vif_SOS_33_C4);
2016 msWriteByteMask(SOS33_C4_H, sVIFSOS33.Vif_SOS_33_C4>>8, 0x07);
2017 */
2018 }
2019 msWriteBit(BYPASS_SOS33, 1, _BIT6);
2020 }
2021
2022 // For API
msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)2023 void msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)
2024 {
2025 HALVIFDBG(printf("\r\nmsVifSetSoundSystem() ucSoundSystem=%d",ucSoundSystem));
2026
2027 if (!_hal_VIF.bBaseAddrInitialized) return ;
2028
2029 DWORD VifCrRateTemp;
2030
2031 // VifShiftClk : 0x1121_D3
2032 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
2033
2034 g_ucVifSoundSystemType = ucSoundSystem;
2035
2036 switch(ucSoundSystem)
2037 {
2038 case VIF_SOUND_B:
2039 if (VIFInitialIn_inst.VifTunerType == 1)
2040 {
2041 // silicon tuner
2042 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2043 {
2044 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2045 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2046 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2047 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2048 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2049 }
2050 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2051 {
2052 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2053 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2054 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2055 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2056 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2057 }
2058 else
2059 {
2060 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2061 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2062 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2063 }
2064 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2065
2066 }
2067
2068 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_A2);
2069 msVifGroupDelayFilter(VIF_SOUND_B, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2070 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2071 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2072 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2073 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2074 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2075 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2076 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2077 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2078
2079 //for Non-NTSC Setting
2080 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2081 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2082
2083 break;
2084
2085 case VIF_SOUND_B_NICAM:
2086 if (VIFInitialIn_inst.VifTunerType == 1)
2087 {
2088 // silicon tuner
2089 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2090 {
2091 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2092 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2093 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2094 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2095 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2096 }
2097 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2098 {
2099 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2100 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2101 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2102 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2103 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2104 }
2105 else
2106 {
2107 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2108 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2109 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2110 }
2111 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2112 }
2113
2114 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_NICAM);
2115 msVifGroupDelayFilter(VIF_SOUND_B_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2116 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2117 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2118 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2119 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2120 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2121 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2122 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2123 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2124 //for Non-NTSC Setting
2125 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2126 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2127
2128 break;
2129
2130 case VIF_SOUND_GH:
2131 if (VIFInitialIn_inst.VifTunerType == 1)
2132 {
2133 // silicon tuner
2134 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2135 {
2136 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2137 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2138 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2139 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2140 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2141 }
2142 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2143 {
2144 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2145 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2146 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2147 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2148 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2149 }
2150 else
2151 {
2152 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2153 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2154 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2155 }
2156 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2157 }
2158
2159 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_A2);
2160 msVifGroupDelayFilter(VIF_SOUND_GH, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2161 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2162 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2163 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2164 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2165 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2166 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2167 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2168 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2169 //for Non-NTSC Setting
2170 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2171 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2172
2173 break;
2174
2175 case VIF_SOUND_GH_NICAM:
2176 if (VIFInitialIn_inst.VifTunerType == 1)
2177 {
2178 // silicon tuner
2179 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2180 {
2181 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2182 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2183 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2184 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2185 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2186 }
2187 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2188 {
2189 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2190 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2191 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2192 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2193 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2194 }
2195 else
2196 {
2197 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2198 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2199 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2200 }
2201 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2202 }
2203
2204 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_NICAM);
2205 msVifGroupDelayFilter(VIF_SOUND_GH_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2206 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2207 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2208 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2209 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2210 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2211 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2212 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2213 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2214 //for Non-NTSC Setting
2215 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2216 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2217
2218 break;
2219
2220 case VIF_SOUND_I:
2221 if (VIFInitialIn_inst.VifTunerType == 1)
2222 {
2223 // silicon tuner
2224 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2225 {
2226 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2227 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2228 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2229 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2230 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2231 }
2232 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2233 {
2234 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2235 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2236 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2237 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2238 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2239 }
2240 else
2241 {
2242 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_I & 0x000000FF)); // cr_rate for 6.4 MHz
2243 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>8) & 0x000000FF));
2244 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>16) & 0x000000FF), 0x0F);
2245 }
2246 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_I, _BIT0); // cr_rate not invert
2247 }
2248
2249 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_NICAM);
2250 msVifGroupDelayFilter(VIF_SOUND_I, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2251 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_I_NOTCH);
2252 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_LOWER_ACI); //Notch N-1 Audio Carrier
2253 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2254 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2255 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2256 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2257 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2258 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2259 //for Non-NTSC Setting
2260 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2261 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2262
2263 break;
2264
2265 case VIF_SOUND_DK1:
2266 if (VIFInitialIn_inst.VifTunerType == 1)
2267 {
2268 // silicon tuner
2269 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2270 {
2271 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2272 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2273 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2274 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2275 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2276 }
2277 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2278 {
2279 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2280 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2281 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2282 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2283 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2284 }
2285 else
2286 {
2287 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2288 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2289 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2290 }
2291 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2292 }
2293
2294 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK1_A2);
2295 msVifGroupDelayFilter(VIF_SOUND_DK1, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2296 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK1_NOTCH);
2297 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2298 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2299 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2300 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2301 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2302 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2303 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2304 //for Non-NTSC Setting
2305 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2306 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2307
2308 break;
2309
2310 case VIF_SOUND_DK2:
2311 if (VIFInitialIn_inst.VifTunerType == 1)
2312 {
2313 // silicon tuner
2314 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2315 {
2316 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2317 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2318 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2319 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2320 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2321 }
2322 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2323 {
2324 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2325 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2326 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2327 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2328 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2329 }
2330 else
2331 {
2332 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2333 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2334 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2335 }
2336 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2337 }
2338
2339 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_A2);
2340 msVifGroupDelayFilter(VIF_SOUND_DK2, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2341 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK2_NOTCH);
2342 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2343 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2344 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2345 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2346 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2347 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2348 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2349 //for Non-NTSC Setting
2350 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2351 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2352
2353 break;
2354
2355 case VIF_SOUND_DK_NICAM:
2356 if (VIFInitialIn_inst.VifTunerType == 1)
2357 {
2358 // silicon tuner
2359 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2360 {
2361 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2362 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2363 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2364 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2365 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2366 }
2367 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2368 {
2369 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2370 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2371 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2372 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2373 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2374 }
2375 else
2376 {
2377 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2378 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2379 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2380 }
2381 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2382 }
2383
2384 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_NICAM);
2385 msVifGroupDelayFilter(VIF_SOUND_DK_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2386 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK_NICAM_NOTCH);
2387 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2388 msWriteBit(BYPASS_ACI_REJ_NTSC, 1, _BIT6); // bypass ACI_REJ_NTSC_filter
2389 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2390 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2391 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2392 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2393 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2394 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2395 //for Non-NTSC Setting
2396 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2397 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2398
2399 break;
2400
2401 case VIF_SOUND_DK3:
2402 if (VIFInitialIn_inst.VifTunerType == 1)
2403 {
2404 // silicon tuner
2405 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2406 {
2407 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2408 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2409 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2410 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2411 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2412 }
2413 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2414 {
2415 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2416 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2417 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2418 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2419 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2420 }
2421 else
2422 {
2423 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2424 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2425 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2426 }
2427 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2428 }
2429
2430 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK3_A2);
2431 msVifGroupDelayFilter(VIF_SOUND_DK3, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2432 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK3_NOTCH);
2433 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2434 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2435 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2436 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2437 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2438 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2439 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2440 //for Non-NTSC Setting
2441 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2442 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2443
2444 break;
2445
2446 case VIF_SOUND_L:
2447 if (VIFInitialIn_inst.VifTunerType == 1)
2448 {
2449 // silicon tuner
2450 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2451 {
2452 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2453 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2454 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2455 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2456 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2457 }
2458 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2459 {
2460 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2461 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2462 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2463 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2464 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2465 }
2466 else
2467 {
2468 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_L & 0x000000FF)); // cr_rate for 6.4 MHz
2469 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>8) & 0x000000FF));
2470 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>16) & 0x000000FF), 0x0F);
2471 }
2472 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_L, _BIT0); // cr_rate not invert
2473 }
2474
2475 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2476 msVifGroupDelayFilter(VIF_SOUND_L, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2477 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2478 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2479 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2480 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2481 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2482 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2483 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2484 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2485 //for Non-NTSC Setting
2486 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2487 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2488
2489 break;
2490
2491 case VIF_SOUND_LL:
2492 if (VIFInitialIn_inst.VifTunerType == 1)
2493 {
2494 // silicon tuner
2495 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2496 {
2497 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2498 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2499 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2500 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2501 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2502 }
2503 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2504 {
2505 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2506 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2507 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2508 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2509 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2510 }
2511 else
2512 {
2513 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_LL & 0x000000FF)); // cr_rate for 6.4 MHz
2514 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>8) & 0x000000FF));
2515 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>16) & 0x000000FF), 0x0F);
2516 }
2517 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_LL, _BIT0); // cr_rate not invert
2518 }
2519
2520 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2521 msVifGroupDelayFilter(VIF_SOUND_LL, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2522 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2523 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2524 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2525 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2526 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2527 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2528 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2529 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2530 //for Non-NTSC Setting
2531 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2532 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2533
2534 break;
2535
2536 case VIF_SOUND_MN:
2537 if (VIFInitialIn_inst.VifTunerType == 1)
2538 {
2539 // silicon tuner
2540 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2541 {
2542 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2543 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2544 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2545 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2546 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2547 }
2548 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2549 {
2550 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2551 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2552 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2553 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2554 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2555 }
2556 else
2557 {
2558 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_MN & 0x000000FF)); // cr_rate for 6.4 MHz
2559 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>8) & 0x000000FF));
2560 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>16) & 0x000000FF), 0x0F);
2561 }
2562 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_MN, _BIT0); // cr_rate not invert
2563 }
2564
2565 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_A2);
2566 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_MN_NOTCH);
2567 msVifGroupDelayFilter(VIF_SOUND_MN, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2568 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_LOWER_ACI); //Notch N-1 Audio Carrier
2569 msWriteBit(A_LPF_BG_SEL, 1, _BIT6); // A_LPF_BG_SEL = 1 (NTSC)
2570 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2571 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2572 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2573 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2574 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2575 //for NTSC Setting
2576 msWriteBit(V_ACI_BPF_SEL, 0 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2577 msWriteBit(A_ACI_BPF_SEL, 0 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2578
2579 break;
2580
2581 default:
2582 break;
2583 }
2584 msVifLoadEQCoeff(ucSoundSystem);
2585 }
2586
2587 // For API
msVifTopAdjust(void)2588 void msVifTopAdjust(void)
2589 {
2590 HALVIFDBG(printf("\r\nmsVifTopAdjust() "));
2591
2592 if (!_hal_VIF.bBaseAddrInitialized) return ;
2593
2594 if (VIFInitialIn_inst.VifTunerType == 0)
2595 {
2596 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifTop, 0x1F); // pga2 min
2597 msWriteByteMask(AGC_PGA2_OV, VIFInitialIn_inst.VifTop, 0x1F);
2598 msWriteBit(AGC_PGA2_OREN, 1, _BIT1);
2599 msWriteBit(AGC_PGA2_OREN, 0, _BIT1);
2600 }
2601 }
2602
msVifDynamicTopAdjust(void)2603 void msVifDynamicTopAdjust(void)
2604 {
2605 HALVIFDBG(printf("\r\nmsVifDynamicTopAdjust() "));
2606
2607 if (!_hal_VIF.bBaseAddrInitialized) return ;
2608
2609 BYTE mean256=0, agc_pga2=0, ref=0, diff=0;
2610 WORD vga=0;
2611
2612 if (VIFInitialIn_inst.VifTunerType == 0)
2613 {
2614 vga = msRead2Bytes(AGC_VGA);
2615 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
2616 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
2617 ref = msReadByte(AGC_REF); // AGC ref
2618
2619 if (g_bCheckModulationType == 0)
2620 {
2621 diff = 0x15; // negative modulation
2622 }
2623 else
2624 {
2625 diff = 0x0A; // positive modulation
2626 }
2627
2628 if ((vga == VIFInitialIn_inst.VifVgaMinimum) && (mean256 >= (ref+diff)) && (agc_pga2 == VIFInitialIn_inst.VifTop))
2629 {
2630 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifDynamicTopMin, 0x1F); // pga2 min
2631 }
2632 else if (((agc_pga2) < VIFInitialIn_inst.VifTop) && ((vga >= 0xF000) || (vga <= VIFInitialIn_inst.VifVgaMaximum)))
2633 {
2634 msVifTopAdjust();
2635 }
2636 }
2637 }
2638
msVifLoad(void)2639 void msVifLoad(void)
2640 {
2641 if (!_hal_VIF.bBaseAddrInitialized) return ;
2642
2643 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0);
2644 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0);
2645 RIU_WriteRegBit(DBB2_LOAD , 1 , _BIT0);
2646 RIU_WriteRegBit(DBB2_LOAD , 0, _BIT0);
2647 }
2648
2649 // For API
msVifInitial(void)2650 void msVifInitial(void)
2651 {
2652 HALVIFDBG(printf("\r\nmsVifInitial()"));
2653
2654 if (!_hal_VIF.bBaseAddrInitialized) return ;
2655
2656 // VifShiftClk : 0x1121_D3
2657 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
2658
2659 msWriteByteMask(VIF_SOFT_RSTZ, 0x00, 0x7F); // VIF software reset
2660 msWriteBit(CLAMPGAIN_RSTZ, 0, _BIT0); // clampgain software reset
2661 msWriteBit(VSYNC_RSTZ, 0, _BIT0); // vsync software reset
2662
2663 g_ucVifStatusStep = VIF_START;
2664
2665 //Serious_ACI_Det parameter
2666 AGC_Change_Index = 0;
2667 RIU_WriteByte(0x1286EL, 0x04); // ADC Setting Overflow value
2668
2669 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
2670 {
2671 g_bCheckModulationType = 1; // positive modulation
2672 g_bCheckIFFreq = (g_ucVifSoundSystemType == VIF_SOUND_L) ? 0 : 1; // 0: 38.9 MHz; 1: 33.9 MHz
2673 }
2674 else
2675 {
2676 g_bCheckModulationType = 0; // negative modulation
2677 g_bCheckIFFreq = 0; // 38.9 MHz
2678 }
2679
2680 if (g_bCheckModulationType == 1)
2681 {
2682 msWriteByteMask(MODULATION_TYPE, 0x0F, 0x0F); // positive modulation
2683 }
2684 else
2685 {
2686 msWriteByteMask(MODULATION_TYPE, 0x00, 0x0F); // negative modulation
2687 }
2688
2689 // AGC
2690 if (g_bCheckModulationType == 1)
2691 {
2692 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2693 msWriteByteMask(AGC_PEAK_CNT_H, 0x0B, 0x0F);
2694 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefPositive); // AGC ref
2695 }
2696 else
2697 {
2698 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2699 msWriteByteMask(AGC_PEAK_CNT_H, 0x0C, 0x0F);
2700 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
2701 }
2702 msWriteByteMask(AGC_MEAN_SEL, _BIT2, _BIT2|_BIT3); // mean16
2703 msWriteByte(AGC_LINE_CNT_L, 0x01); // AGC line cnt = 1
2704 msWriteByte(AGC_LINE_CNT_H, 0x00);
2705
2706 if (bEnableUsrNonSteadyAgcK)
2707 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
2708 else
2709 {
2710 if (VIFInitialIn_inst.VifTunerType == 1)
2711 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
2712 else
2713 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
2714 }
2715
2716 msWriteByteMask(AGC_PGA2_OREN, 0x00, 0x03);
2717 msWriteByte(AGC_VGA_MAX_L, VIFInitialIn_inst.VifVgaMaximum); // vga max
2718 msWriteByte(AGC_VGA_MAX_H, VIFInitialIn_inst.VifVgaMaximum>>8);
2719 msWriteByte(AGC_VGA_MIN_L, VIFInitialIn_inst.VifVgaMinimum); // vga min
2720 msWriteByte(AGC_VGA_MIN_H, VIFInitialIn_inst.VifVgaMinimum>>8);
2721 msWriteByteMask(AGC_PGA1_MAX, 0x00, 0x0F); // pga1 max
2722 if (VIFInitialIn_inst.VifTunerType == 1)
2723 msWriteByteMask(AGC_PGA2_MAX, 0x00, 0x1F); // pga2 max
2724 else
2725 msWriteByteMask(AGC_PGA2_MAX, 0x1F, 0x1F); // pga2 max
2726
2727 msWriteByte(VAGC_VGA2_OV_L, 0x00); // VGA2(IFAGC) output minimun
2728 msWriteByte(VAGC_VGA2_OV_H, 0x80);
2729 msWriteBit(VAGC_VGA2_OREN, 1, _BIT2);
2730
2731 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
2732 msWriteBit(VAGC_VGA_OUT_SEL, 1, _BIT0); // VGA1 -> IFAGC
2733
2734 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
2735 {
2736 msWriteBit(LEVEL_SENSE_BYPASS, 0, _BIT0); // Level_Sense not bypass
2737 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
2738 msWriteBit(BYPASS_V_ACI_BPF4AGC, 0, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
2739 }
2740 else
2741 {
2742 msWriteBit(LEVEL_SENSE_BYPASS, 1, _BIT0); // Level_Sense bypass
2743 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
2744 msWriteBit(BYPASS_V_ACI_BPF4AGC, 1, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
2745 }
2746
2747 msWriteBit(AGC_IN_SEL, 1, _BIT1); // AGC input 0: from SOS_out ; 1:from ACI_BPF out(can be bypassed)
2748
2749 // AGC gain distribution
2750 msWriteBit(AGC_DBB_VVGA_SEL, 0, _BIT3); // Vga gain force x1
2751 msWriteBit(AGC_DBB_AVGA_SEL, 0, _BIT4); // Avga gain force x1
2752
2753 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.VifVgaMaximum); // vga threshold
2754 msWriteByte(AGC_VGA_THR+1, (VIFInitialIn_inst.VifVgaMaximum - 0x1000)>>8);
2755 msWriteByte(AGC_VGA_BASE, (VIFInitialIn_inst.VifAgcVgaBase - 0x14)); // vga base
2756 msWriteByte(AGC_VGA_OFFS, VIFInitialIn_inst.VifAgcVgaOffs); // vga offset
2757
2758 msWriteBit(AGC_ENABLE, 1, _BIT0); // AGC enable
2759
2760 // CR
2761 msWriteByte(CR_DL_A, 0x16); // CR audio delay line
2762 msWriteByte(CR_PD_ERR_MAX_L, 0xFF); // CR pd error max
2763 msWriteByteMask(CR_PD_ERR_MAX_H, 0x3F, 0x3F);
2764 msWriteByte(CR_NOTCH_A1_L, 0x41); // CR notch filter coefficient
2765 msWriteByte(CR_NOTCH_A1_H, 0x0C);
2766 msWriteByte(CR_NOTCH_A2_L, 0xE9); // CR notch filter coefficient
2767 msWriteByte(CR_NOTCH_A2_H, 0x0B);
2768 msWriteByte(CR_NOTCH_B1_L, 0x58); // CR notch filter coefficient
2769 msWriteByte(CR_NOTCH_B1_H, 0x00);
2770 msWriteBit(CR_ANCO_SEL, 1, _BIT0); // audio nco select
2771 if (VIFInitialIn_inst.VifTunerType == 2)
2772 {
2773 msWriteByteMask(CR_KF1_HW, 0x00, 0x0F); // kf1 hardware mode
2774 msWriteByteMask(CR_KP1_HW, 0x00, 0x0F); // kp1 hardware mode
2775 msWriteByteMask(CR_KI1_HW, 0x00, 0xF0);// ki1 hardware mode
2776 msWriteByteMask(CR_KP2_HW, 0x00, 0x0F); // kp2 hardware mode
2777 msWriteByteMask(CR_KI2_HW, 0x00, 0xF0);// ki2 hardware mode
2778 msWriteBit(CR_K_SEL, 0, _BIT6); // hw mode
2779 }
2780 else
2781 {
2782 msWriteByteMask(CR_KF1_HW, VIFInitialIn_inst.VifCrKf1, 0x0F); // kf1 hardware mode
2783 msWriteByteMask(CR_KP1_HW, VIFInitialIn_inst.VifCrKp1, 0x0F); // kp1 hardware mode
2784 msWriteByteMask(CR_KI1_HW, VIFInitialIn_inst.VifCrKi1<<4, 0xF0);// ki1 hardware mode
2785 msWriteByteMask(CR_KP2_HW, VIFInitialIn_inst.VifCrKp2, 0x0F); // kp2 hardware mode
2786 msWriteByteMask(CR_KI2_HW, VIFInitialIn_inst.VifCrKi2<<4, 0xF0);// ki2 hardware mode
2787 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
2788 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1); // for > 150% overmodulation
2789 }
2790 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
2791 msWriteByteMask(CR_KP_SW, 0x00, 0x0F); // kp software mode
2792 msWriteByteMask(CR_KI_SW, 0x00, 0xF0); // ki software mode
2793 msWriteBit(CR_JTRDET_IN_SEL, 1, _BIT4); // carrier jitter detector input select CR_LF1
2794 msWriteBit(VNCO_INV_OREN, 0, _BIT1);
2795
2796 //locking range setting
2797 msWriteBit(CR_FD_IN_SEL, 0 , _BIT0); //0:IIR LPF2; 1:FIR
2798 msWriteBit(CR_IIR_SEL, 1 , _BIT1); //0:IIR LPF1; 1:IIR LPF2
2799
2800 if(VIFInitialIn_inst.VifCrPdModeSel == 0) // 0: imaginary part; 1: cordic
2801 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF1); // IIR LPF1 coefficients
2802 else
2803 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
2804
2805 msWriteBit(CR_LPF_SEL, VIFInitialIn_inst.VifCrLpfSel, _BIT4); // CR LPF 0: FIR LPF; 1: IIR LPF
2806 msWriteBit(CR_PD_MODE, VIFInitialIn_inst.VifCrPdModeSel, _BIT1); // 0: imaginary part; 1: cordic
2807 msWriteBit(LOCK_LEAKY_SEL, VIFInitialIn_inst.VifCrLockLeakySel, _BIT0);
2808 msWriteBit(CR_PD_X2, VIFInitialIn_inst.VifCrPdX2, _BIT2); // CR X2 0: lock 0 degree; 1: lock 0 or 180 degree
2809 msWriteByte(CR_LOCK_TH_L, VIFInitialIn_inst.VifCrLockThr); // CR lock threshold
2810 msWriteByteMask(CR_LOCK_TH_H, VIFInitialIn_inst.VifCrLockThr>>8, 0x03);
2811 msWriteByte(CR_UNLOCK_NUM, 0x00); // CR unlock num
2812 msWriteByte(CR_UNLOCK_NUM+1, 0x40);
2813 msWriteByteMask(CR_UNLOCK_NUM+2, 0x00, 0x0F);
2814 msWriteByte(CR_LOCK_NUM, VIFInitialIn_inst.VifCrLockNum); // CR lock num
2815 msWriteByte(CR_LOCK_NUM+1, VIFInitialIn_inst.VifCrLockNum>>8);
2816 msWriteByteMask(CR_LOCK_NUM+2, VIFInitialIn_inst.VifCrLockNum>>16, 0x0F);
2817 msWriteByte(CR_CODIC_TH, VIFInitialIn_inst.VifCrThr); // CR cordic threshold
2818 msWriteByteMask(CR_CODIC_TH+1, VIFInitialIn_inst.VifCrThr>>8, 0x3F);
2819
2820 if (VIFInitialIn_inst.VifTunerType == 0)
2821 {
2822 if (VifShiftClk/*g_VifShiftClk*/ == 1)
2823 {
2824 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
2825 msWriteByte(CR_RATE+1, 0xDB);
2826 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
2827 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2828 }
2829 else if(VifShiftClk/*g_VifShiftClk*/ == 2)
2830 {
2831 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
2832 msWriteByte(CR_RATE+1, 0x9F);
2833 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
2834 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2835 }
2836 else
2837 {
2838 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
2839 msWriteByte(CR_RATE+1, 0x38);
2840 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
2841 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
2842 }
2843 }
2844
2845 // tuner step size
2846 VIFInitialIn_inst.VifTunerStepSize = FREQ_STEP_62_5KHz;
2847 if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_62_5KHz) // 62.5KHz
2848 {
2849 if (g_bCheckIFFreq == 0)
2850 {
2851 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xB3); // foe scaling factor
2852 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x02, 0x0F);
2853 }
2854 else
2855 { // SECAM L'
2856 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x4D); // foe scaling factor
2857 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0D, 0x0F);
2858 }
2859 }
2860 else if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_50KHz) // 50KHz
2861 {
2862 if (g_bCheckIFFreq == 0)
2863 {
2864 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x60); // foe scaling factor
2865 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x03, 0x0F);
2866 }
2867 else
2868 { // SECAM L'
2869 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xA0); // foe scaling factor
2870 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0C, 0x0F);
2871 }
2872 }
2873
2874 // Filter
2875 msWriteBit(DEBUG_V_A, 1, _BIT5); // single ADC
2876 if (VIFInitialIn_inst.ChinaDescramblerBox !=0)
2877 {
2878 msWriteByteMask(IMAGE_REJ_IIR_SEL, _BIT3, _BIT2|_BIT3); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
2879 }
2880 msWriteByteMask(IMAGE_REJ1_SEL, _BIT0, _BIT0|_BIT1); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
2881 msWriteBit(BYPASS_CO_A_REJ, 0, _BIT4); // CO_A_REJ not bypass
2882
2883 msWriteBit(IMAGE_REJ_OUT_SEL, 0, _BIT7); // 0: IMAGE_REJ1; 1: IMAGE_REJ_IIR
2884 msWriteBit(A_BP_OUT_X2, 1, _BIT7); // A_BP output x2
2885 msWriteBit(A_DAGC_SEL, 1, _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
2886 msWriteBit(BYPASS_A_NOTCH, 1, _BIT6); // A_NOTCH bypass
2887 msWriteBit(BYPASS_A_SOS, 1, _BIT7); // A_SOS bypass
2888 msWriteBit(BYPASS_SOS21, 0, _BIT2); // SOS21 not bypass
2889 msWriteBit(BYPASS_SOS22, 0, _BIT3); // SOS22 not bypass
2890 msWriteBit(BYPASS_SOS31, 0, _BIT4); // SOS31 not bypass
2891 msWriteBit(BYPASS_SOS32, 0, _BIT5); // SOS32 not bypass
2892
2893 // silicon tuner
2894 if (VIFInitialIn_inst.VifTunerType == 1)
2895 {
2896 msWriteBit(BYPASS_V_ACI_BPF4LS, 1, _BIT5); // VACI_BPF bypass
2897 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
2898 msWriteBit(BYPASS_VSPUR_REJ, 1, _BIT2); // VSPUR_REJ bypass
2899 msWriteBit(BYPASS_ASPUR_REJ, 1, _BIT3); // ASPUR_REJ bypass
2900
2901 if ((msReadByte(CR_RATE_INV) & 0x01) != 0)
2902 msWriteBit(BYPASS_SOS11, 1, _BIT0); // SOS11 bypass
2903 }
2904 else
2905 {
2906 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
2907 }
2908
2909 // DAGC1
2910 if (_bit1_(VIFInitialIn_inst.VifDelayReduce))
2911 {
2912 msWriteBit(DAGC1_DL_BYPASS, 1, _BIT3); // DAGC1 delay line bypass
2913 }
2914 else
2915 {
2916 msWriteBit(DAGC1_DL_BYPASS, 0, _BIT3); // DAGC1 delay line not bypass
2917 }
2918 msWriteBit(DAGC1_BYPASS, 0, _BIT1); // DAGC1 not bypass
2919
2920 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
2921 msWriteBit(DAGC1_OREN, 0, _BIT6); // DAGC1 gain_overwrite = 0
2922
2923 msWriteBit(DAGC1_GAIN0_FB_EN, 0, _BIT2); // DAGC1 gain_update = 1
2924
2925 if (g_bCheckModulationType == 1)
2926 {
2927 msWriteByteMask(DAGC1_REF, 0x0B, 0x3F); // DAGC1 ref
2928 msWriteByteMask(DAGC1_RATIO, 0x03, 0x07); // DAGC1 ratio
2929 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
2930 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0B, 0x0F);
2931 msWriteByte(DAGC1_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc1GainOv);
2932 msWriteByteMask(DAGC1_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc1GainOv>>8, 0x3F);
2933 }
2934 else
2935 {
2936 msWriteByteMask(DAGC1_REF, VIFInitialIn_inst.VifDagc1Ref, 0x3F); // DAGC1 ref
2937 msWriteByteMask(DAGC1_RATIO, 0x00, 0x07); // DAGC1 ratio
2938 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
2939 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0C, 0x0F);
2940 }
2941 msWriteBit(DAGC1_ENABLE, 1, _BIT0); // DAGC1 enable
2942
2943 // DAGC2
2944 if (_bit2_(VIFInitialIn_inst.VifDelayReduce))
2945 {
2946 msWriteBit(DAGC2_DL_BYPASS, 1, _BIT3); // DAGC2 delay line bypass
2947 }
2948 else
2949 {
2950 msWriteBit(DAGC2_DL_BYPASS, 0, _BIT3); // DAGC2 delay line not bypass
2951 }
2952 msWriteBit(DAGC2_BYPASS, 0, _BIT1); // DAGC2 not bypass
2953
2954 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
2955 msWriteBit(DAGC2_OREN, 0, _BIT6); // DAGC2 gain_overwrite = 0
2956
2957 msWriteBit(DAGC2_GAIN0_FB_EN, 0, _BIT2); // DAGC2 gain_update = 1
2958
2959 if (g_bCheckModulationType == 1)
2960 {
2961 msWriteByteMask(DAGC2_REF, 0x0B, 0x3F); // DAGC2 ref
2962 msWriteByteMask(DAGC2_RATIO, 0x03, 0x07); // DAGC2 ratio
2963 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
2964 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0B, 0x0F);
2965 msWriteByte(DAGC2_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc2GainOv);
2966 msWriteByteMask(DAGC2_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc2GainOv>>8, 0x3F);
2967 }
2968 else
2969 {
2970 msWriteByteMask(DAGC2_REF, VIFInitialIn_inst.VifDagc2Ref, 0x3F); // DAGC2 ref
2971 msWriteByteMask(DAGC2_RATIO, 0x00, 0x07); // DAGC2 ratio
2972 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
2973 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0C, 0x0F);
2974 }
2975 msWriteBit(DAGC2_ENABLE, 1, _BIT0); // DAGC2 enable
2976
2977 // clampgain
2978 if (g_bCheckModulationType == 1)
2979 {
2980 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvPositive); // clampgain clamp overwrite value
2981 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvPositive>>8, 0x07);
2982 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvPositive); // clampgain gain overwrite value
2983 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvPositive>>8, 0x07);
2984 }
2985 else
2986 {
2987 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvNegative); // clampgain clamp overwrite value
2988 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvNegative>>8, 0x07);
2989 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvNegative); // clampgain gain overwrite value
2990 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvNegative>>8, 0x07);
2991 }
2992 msWriteBit(CLAMPGAIN_BYPASS, 0, _BIT1); // clampgain not bypass
2993 msWriteBit(CLAMPGAIN_SEL, VIFInitialIn_inst.VifClampgainClampSel, _BIT3); // 0: clamp select sync bottom; 1: clamp select porch
2994 msWriteByte(CLAMPGAIN_SYNCBOTT_REF, VIFInitialIn_inst.VifClampgainSyncbottRef); // porch or syncbottom ref
2995 msWriteByte(CLAMPGAIN_SYNCHEIGHT_REF, VIFInitialIn_inst.VifClampgainSyncheightRef); // syncheight ref
2996 msWriteByteMask(CLAMPGAIN_KC, VIFInitialIn_inst.VifClampgainKc, 0x07); // kc
2997 msWriteByteMask(CLAMPGAIN_KG, VIFInitialIn_inst.VifClampgainKg<<4, 0x70); // kg
2998 msWriteByte(CLAMPGAIN_PORCH_CNT, VIFInitialIn_inst.VifClampgainPorchCnt); // clampgain porch cnt for NTSC
2999 msWriteByteMask(CLAMPGAIN_PORCH_CNT+1, VIFInitialIn_inst.VifClampgainPorchCnt>>8, 0x01);
3000 msWriteByte(CLAMPGAIN_CLAMP_MIN, VIFInitialIn_inst.VifClampgainClampMin); // clampgain clamp min
3001 msWriteByte(CLAMPGAIN_CLAMP_MAX, VIFInitialIn_inst.VifClampgainClampMax); // clampgain clamp max
3002 msWriteByte(CLAMPGAIN_GAIN_MIN, VIFInitialIn_inst.VifClampgainGainMin); // clampgain gain min
3003 msWriteByte(CLAMPGAIN_GAIN_MAX, VIFInitialIn_inst.VifClampgainGainMax); // clampgain gain max
3004 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainClampOren, _BIT0); // clampgain clamp overwrite enable
3005 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainGainOren, _BIT1); // clampgain gain overwrite enable
3006 msWriteBit(CLAMPGAIN_EN, 1, _BIT2); // clampgain enable
3007
3008 // vsync
3009 msWriteBit(VSYNC_ENABLE, 1, _BIT1); // vsync enable
3010
3011 // ADAGC
3012 if (g_bCheckModulationType == 1)
3013 {
3014 msWriteBit(ADAGC_BYPASS, 1, _BIT1); // ADAGC bypass
3015 msWriteByteMask(ADAGC_K, 0x00, 0x07); // ADAGC k
3016 msWriteBit(ADAGC_ENABLE, 0, _BIT0); // ADAGC disable
3017 }
3018 else
3019 {
3020 msWriteBit(ADAGC_BYPASS, 0, _BIT1); // ADAGC not bypass
3021 msWriteByteMask(ADAGC_K, 0x04, 0x07); // ADAGC k
3022 msWriteBit(ADAGC_ENABLE, 1, _BIT0); // ADAGC enable
3023 }
3024
3025 if(VIFInitialIn_inst.VifSeriousACIDetect == 1) //ACI_Functions_Selective
3026 {
3027 VIFInitialIn_inst.VifACIDetect = 0;
3028 }
3029
3030 // zero detector
3031 msWriteBit(ZERO_IN_SEL, 1 , _BIT1); // 0: from dagc_in; 1: from dagc_out
3032 msWriteByteMask(ZERO_TH, 0x20, 0x7F);
3033 msWriteByte(ZERO_CNT_NUM, 0x0A);
3034 msWriteByteMask(ZERO_CNT_NUM+1, 0x00, 0x0F);
3035 msWriteByte(ZERO_ZERO_NUM, 0x20);
3036 msWriteByte(ZERO_ZERO_NUM+1, 0x00);
3037 msWriteBit(ZERO_ENABLE, 0 , _BIT0); // zero detector disable
3038
3039 // Level Sense setting
3040 msWriteByte(LEVEL_SENSE_LOCK_CNT, 0x00);
3041 msWriteByte(LEVEL_SENSE_LOCK_CNT+1, 0x01);
3042
3043 msWriteByte(LEVEL_SENSE_DIFF_AVG_TH, 0x28);
3044 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_TH+1, 0x00, 0x0F);
3045
3046 msWriteBit(LEVEL_SENSE_EN, 1, _BIT0);
3047 msWriteBit(LEVLE_SENSE_MOD_TYPE, 0, _BIT4); // 0: negedge; 1: posedge
3048 msWriteBit(LEVEL_SENSE_MODE, 0, _BIT0); // 0: porch; 1: sync height
3049 msWriteBit(LEVEL_SENSE_VGA_OREN, 0, _BIT4);
3050
3051 msWriteByteMask(LEVEL_SENSE_MEAN_SEL, 0x01, 0x03); // 0: 1 line; 1: 16 lines; 2, 3: 256 lines
3052 msWriteBit(LEVEL_SENSE_DVGA_OREN_SEL, 1 , _BIT4); // 0: SW; 1: HW
3053
3054 msWriteByte(LEVEL_SENSE_REF, 0x59);
3055 msWriteByte(LEVEL_SENSE_REF+1, 0x00);
3056
3057 msWriteByte(LEVEL_SENSE_LINE_CNT, 0x04);
3058 msWriteByte(LEVEL_SENSE_LINE_CNT+1, 0x00);
3059
3060 msWriteByte(LEVEL_SENSE_PORCH_CNT, 0xE0);
3061 msWriteByteMask(LEVEL_SENSE_PORCH_CNT+1, 0x00, 0x01);
3062
3063 msWriteByte(LEVEL_SENSE_PEAK_CNT , 0x00);
3064 msWriteByteMask(LEVEL_SENSE_PEAK_CNT +1, 0x0C, 0x0F);
3065
3066 msWriteByteMask(LEVEL_SENSE_K, 0x04, 0x07); // 0~7: 0, 2^-2 ~ 2^-8
3067 msWriteByteMask(LEVEL_SENSE_K+1, 0x00, 0x00);
3068
3069 msWriteByte(LEVEL_SENSE_VGA_OV, 0x80);
3070 msWriteByte(LEVEL_SENSE_VGA_OV+1, 0x00);
3071
3072 msWriteByte(LEVEL_SENSE_DIFF_AVG_INI, 0xFF); // level_sense diff_avg initial value
3073 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_INI+1, 0x0F, 0x0F);
3074
3075 //AM Hum detection setting
3076 msWriteByteMask(AGC_HUM_CNT_MAX , _BIT5 , _BIT4|_BIT5|_BIT6); // 0->128 ,1->256, 2->512 samples
3077 msWriteByte(AGC_HUM_ERR_THR , 0x20); // format <8,8> => 0.125 = 0x20
3078 msWriteByte(AGC_HUM_DET_LIM , 0x20); // format <8,-2> => 128 samples
3079
3080 //CR_Ki/Kp speed up setting
3081 msWriteBit(CR_KPKI_SPEEDUP_EN , 0 , _BIT0); //0:disable , 1:enable
3082 msWriteBit(CR_INV2_EN , 0 , _BIT4); //0:disable , 1:enable
3083 msWriteByteMask(CR_KP_SPEED, _BIT2 , _BIT0|_BIT1|_BIT2|_BIT3);
3084 msWriteByteMask(CR_KI_SPEED, _BIT6 , _BIT4|_BIT5|_BIT6|_BIT7);
3085
3086 if(VIF_IS_ADC_48MHz == 0)
3087 {
3088 // VIF ADC clock setting
3089 msWriteBit(VIF_ADC_48M, 0, _BIT4); // 0:144MHz , 1:48MHz
3090
3091 // VIF DECI_filter coefficient selection
3092 msWriteBit(VIF_DECI_COEF_SEL, 0, _BIT4); // 0:old, 1:new
3093
3094 msWriteBit(HALVIFDBG2_BIT, 0, _BIT4); // 0:144MHz, 1:48MHz
3095 }
3096 else
3097 {
3098 // VIF ADC clock setting
3099 msWriteBit(VIF_ADC_48M, 1, _BIT4); // 0:144MHz , 1:48MHz
3100
3101 // VIF DECI_filter coefficient selection
3102 msWriteBit(VIF_DECI_COEF_SEL, 1, _BIT4); // 0:old, 1:new
3103
3104 msWriteBit(HALVIFDBG2_BIT, 1, _BIT4); // 0:144MHz, 1:48MHz
3105 }
3106
3107 // VIF ADC LSB mask
3108 msWriteByteMask(VIF_ADC_LSB_MASK, 0x00, _BIT0|_BIT1); // Un-mask ADC_LSB bits
3109
3110 // locking range +/- 500KHz -> +/- 1MHz setting
3111 //msWriteByteMask(CR_KF1_HW, 0x02, 0x0F); // kf1 hardware mode
3112 //msWriteByteMask(CR_KP1_HW, 0x43, 0x0F); // kp1 hardware mode
3113 //msWriteByteMask(CR_KI1_HW, 0x43, 0xF0); // ki1 hardware mode
3114 //msWriteByteMask(CR_FD_DELAY_SEL, _BIT5, _BIT4|_BIT5);
3115 //msWriteByteMask(CR_FD_MU, _BIT5, _BIT4|_BIT5);
3116
3117 //msWriteBit(BYPASS_SOS33, 1, _BIT6);
3118
3119 // real HW_KPKI_THR1_L
3120 msWriteByte(KPKI_ADJ_TH1_L, 0x50);
3121 msWriteByte(KPKI_ADJ_TH1_L+1, 0x00);
3122
3123 // real HW_KPKI_THR1_H
3124 msWriteByte(KPKI_ADJ_TH1_H, 0x50);
3125 msWriteByte(KPKI_ADJ_TH1_H+1, 0x00);
3126
3127 // real HW_KPKI_THR2_L
3128 msWriteByte(KPKI_ADJ_TH2_L, 0x00);
3129 msWriteByte(KPKI_ADJ_TH2_L+1, 0x01);
3130
3131 // real HW_KPKI_THR2_H
3132 msWriteByte(KPKI_ADJ_TH2_H, 0x00);
3133 msWriteByte(KPKI_ADJ_TH2_H+1, 0x01);
3134
3135 // real HW_KPKI_THR3_L
3136 msWriteByte(KPKI_ADJ_TH3_L, 0xFF);
3137 msWriteByte(KPKI_ADJ_TH3_L+1, 0xFF);
3138
3139 // real HW_KPKI_THR3_H
3140 msWriteByte(KPKI_ADJ_TH3_H, 0xFF);
3141 msWriteByte(KPKI_ADJ_TH3_H+1, 0xFF);
3142
3143 // real HW_KPKI setting
3144 msWriteByteMask(CR_KP_ADJ1, 0x05, 0x0F);
3145 msWriteByteMask(CR_KI_ADJ1, 0x80, 0xF0);
3146 msWriteByteMask(CR_KP_ADJ2, 0x04, 0x0F);
3147 msWriteByteMask(CR_KI_ADJ2, 0x70, 0xF0);
3148 msWriteByteMask(CR_KP_ADJ3, 0x03, 0x0F);
3149 msWriteByteMask(CR_KI_ADJ3, 0x60, 0xF0);
3150
3151 // real HW_KPKI_disable
3152 msWriteBit(KPKI_ADJ_EN, 0, _BIT0);
3153 g_VifHWKpKiFlag = 1; // 0:SW_Kp/Ki ; 1:Real HW_Kp/Ki
3154 msWriteBit(HALVIFDBG2_BIT, g_VifHWKpKiFlag, _BIT0);
3155
3156 // for China stream setting
3157 msWriteByte(CR_JTR_MAX_CNT, 0x00);
3158 msWriteByte(CR_JTR_MAX_CNT+1, 0x70);
3159 msWriteByteMask(JTR_DELTA_AVE_NUM, 0x20, 0x30);
3160
3161 msWriteBit(BYPASS_N_A1, 1, _BIT2);
3162 msWriteBit(BYPASS_N_A2, 1, _BIT3);
3163 msWriteBit(BYPASS_SOS11, 1, _BIT0);
3164 msWriteBit(BYPASS_SOS12, 1, _BIT1);
3165
3166 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7D); // VIF software reset
3167 msWriteBit(CLAMPGAIN_RSTZ, 1, _BIT0); // clampgain software reset
3168 msWriteBit(VSYNC_RSTZ, 1, _BIT0); // vsync software reset
3169
3170 // TOP
3171 msVifTopAdjust();
3172
3173 // version control
3174 msWriteByte(FIRMWARE_VERSION_L, 0x12); // 18(dd)
3175 msWriteByte(FIRMWARE_VERSION_H, 0x40); // 04/16 (mm/yy) firmware version control
3176
3177 HAL_VIF_Delay1ms(1);
3178 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7F);
3179 }
3180
3181 // For API
msVifExit(void)3182 void msVifExit(void)
3183 {
3184 if (!_hal_VIF.bBaseAddrInitialized) return ;
3185
3186 // RFAGC/IFAGC disable
3187 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0);
3188 RIU_WriteRegBit(IFAGC_ENABLE, 0, _BIT4);
3189
3190 // SRAM Power Control
3191 RIU_WriteByte(0x12090L, 0x00);
3192 RIU_WriteByte(0x12091L, 0x7F);
3193 }
3194
3195 // For API
msVifHandler(BOOL bVifDbbAcq)3196 void msVifHandler(BOOL bVifDbbAcq)
3197 {
3198 BYTE afc_foe;
3199 BYTE mean16;
3200 BYTE agc_pga2;
3201 WORD agc_vga;
3202 BYTE dagc1_var;
3203 BYTE kpki_gear;
3204 static BYTE crjtr_det_cnt = 0;
3205 static WORD kpki_cnt_idx = 0;
3206
3207 if (!_hal_VIF.bBaseAddrInitialized) return ;
3208
3209 MsOS_DelayTask(3);
3210
3211 switch(g_ucVifStatusStep)
3212 {
3213 case VIF_START:
3214 case VIF_AGC_STATUS:
3215 g_VifCrKpKiAdjLoopCnt = 0;
3216 kpki_cnt_idx = 0;
3217 crjtr_det_cnt = 0;
3218 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3219 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3220 agc_vga = msRead2Bytes(AGC_VGA);
3221 if (g_bCheckModulationType == 0)
3222 {
3223 if (((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3224 {
3225 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3226 msWriteByte(AGC_LINE_CNT_H, 0x00);
3227
3228 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1; kp2,ki2,kf2
3229 msWriteBit(CR_K_SEL2, 0, _BIT0);
3230
3231 g_ucVifStatusStep = VIF_AFC_STATUS;
3232 }
3233 }
3234 else
3235 {
3236 if (((mean16 < AGC_MEAN16_UPBOUND_SECAM) && (mean16 > AGC_MEAN16_LOWBOUND_SECAM)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3237 {
3238 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3239 msWriteByte(AGC_LINE_CNT_H, 0x00);
3240
3241 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3242
3243 g_ucVifStatusStep = VIF_AFC_STATUS;
3244 }
3245 }
3246
3247 // for No-SAW use
3248 if((VIFInitialIn_inst.VifSawArch == NO_SAW)&&(g_bCheckModulationType == 0))
3249 {
3250 if(bVifDbbAcq == 0)
3251 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative);
3252 else
3253 msWriteByte(AGC_REF, VIFInitialIn_inst.VifChanelScanAGCREF);
3254 }
3255
3256 break;
3257
3258 case VIF_AFC_STATUS:
3259 if (_bit0_(msReadByte(CR_LOCK_STATUS)))
3260 {
3261 // DAGC
3262 if (g_bCheckModulationType == 1)
3263 {
3264 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
3265 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
3266 }
3267 g_ucVifStatusStep = VIF_AFC_STATUS2;
3268 }
3269 else
3270 {
3271 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3272 HAL_VIF_Delay1us(1);
3273 msWriteBit(CR_NCO_FF_RSTZ, 0, _BIT2); // reset NCO_FF
3274 msWriteBit(CR_LF_FF_RSTZ, 0, _BIT5); // reset AFC integral part
3275 HAL_VIF_Delay1us(5);
3276 msWriteBit(CR_NCO_FF_RSTZ, 1, _BIT2);
3277 HAL_VIF_Delay1us(1);
3278 msWriteBit(CR_LF_FF_RSTZ, 1, _BIT5);
3279 }
3280 break;
3281
3282 case VIF_AFC_STATUS2:
3283 afc_foe = msReadByte(CR_FOE); // AFC_FOE
3284 if ((afc_foe <= 0x04) || (afc_foe >= 0xFC)) // |AFC_FOE|<=4
3285 {
3286 // AGC
3287 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.GainDistributionThr); // vga threshold
3288 msWriteByte(AGC_VGA_THR+1, VIFInitialIn_inst.GainDistributionThr>>8);
3289 msWriteByte(AGC_VGA_BASE, VIFInitialIn_inst.VifAgcVgaBase); // vga base
3290 if (bVifDbbAcq == 0) // 0: not channel scan; 1: channel scan
3291 {
3292 // AGC
3293 if (bEnableUsrSteadyAgcK)
3294 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3295 else
3296 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2);// k
3297
3298 msWriteByte(AGC_LINE_CNT_L, 0x10); // AGC line cnt = 16
3299 msWriteByte(AGC_LINE_CNT_H, 0x00);
3300
3301 // CR
3302 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
3303
3304 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3305 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3306 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3307 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3308
3309 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
3310 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
3311
3312 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3313 {
3314 //if(g_VifHWKpKiFlag == 1)
3315 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3316 {
3317 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3318 kpki_gear = msReadByte(CR_KPKI_GEAR) & 0x30;
3319 }
3320 }
3321
3322 msWriteByte(CR_PD_ERR_MAX_L, VIFInitialIn_inst.VifCrPdErrMax); // CR pd error max
3323 msWriteByteMask(CR_PD_ERR_MAX_H, VIFInitialIn_inst.VifCrPdErrMax>>8, 0x3F);
3324 msWriteByte(CR_UNLOCK_NUM, VIFInitialIn_inst.VifCrUnlockNum); // CR unlock num
3325 msWriteByte(CR_UNLOCK_NUM+1, VIFInitialIn_inst.VifCrUnlockNum>>8);
3326 msWriteByteMask(CR_UNLOCK_NUM+2, VIFInitialIn_inst.VifCrUnlockNum>>16, 0x0F);
3327
3328 // over modulation
3329 if ((VIFInitialIn_inst.VifOverModulation == 1) && (g_bCheckModulationType == 0))
3330 {
3331 msWriteBit(VNCO_INV_OREN, 1, _BIT1);
3332 msWriteBit(VNCO_INV_OV, 0, _BIT2);
3333 }
3334
3335 g_ucVifStatusStep = VIF_STEADY_STATUS;
3336 }
3337 }
3338
3339 if (!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3340 msVifInitial();
3341 break;
3342
3343 case VIF_STEADY_STATUS:
3344
3345 // for SAWless, ADC back-off for +20dB ACI
3346 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
3347 {
3348 if(VIFInitialIn_inst.VifSeriousACIDetect)
3349 msVifSeriousACIDetection();
3350 }
3351
3352 // Dynamic TOP adjust for strong signal
3353 if (VIFInitialIn_inst.VifDynamicTopAdjust)
3354 {
3355 msVifDynamicTopAdjust();
3356 }
3357
3358 // AM hum detector
3359 agc_vga = msRead2Bytes(AGC_VGA);
3360 dagc1_var = msReadByte(DAGC1_VAR+1);
3361 if ((VIFInitialIn_inst.VifAmHumDetection == 1) && ((agc_vga > VIFInitialIn_inst.VifVgaMinimum) || (agc_vga < (VIFInitialIn_inst.GainDistributionThr - 0x1000))))
3362 {
3363 if ((dagc1_var >= 0x18) && (g_bCheckModulationType == 0))
3364 {
3365 // 20% AM modulation
3366 msWriteByte(AGC_REF, 0x43); // AGC ref
3367 }
3368 else if ((dagc1_var <= 0x05) && (g_bCheckModulationType == 0))
3369 {
3370 // 10% AM modulation
3371 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
3372 }
3373 }
3374
3375 // AGC
3376 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3377 if (g_bCheckModulationType == 0)
3378 {
3379 if ((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND))
3380 {
3381 if (bEnableUsrSteadyAgcK)
3382 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3383 else
3384 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2); // k
3385 }
3386 else
3387 {
3388 if (bEnableUsrNonSteadyAgcK)
3389 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
3390 else
3391 {
3392 if (VIFInitialIn_inst.VifTunerType == 1)
3393 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
3394 else
3395 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
3396 }
3397 }
3398 }
3399
3400 // CR monitor
3401 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3402 if ((agc_pga2 >= 0x0F) && (VIFInitialIn_inst.VifCrPdModeSel == 1))
3403 {
3404 msWriteByteMask(CR_KP_SW, (VIFInitialIn_inst.VifCrKp)+0x01, 0x0F); // kp software mode
3405 msWriteByteMask(CR_KI_SW, (VIFInitialIn_inst.VifCrKi<<4)+0x10, 0xF0); // ki software mode
3406 }
3407 else
3408 {
3409 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3410 {
3411 //if(g_VifHWKpKiFlag == 1)
3412 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3413 {
3414 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3415 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3416 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3417 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3418
3419 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3420 kpki_gear = msReadByte(CR_KPKI_GEAR) & 0x30;
3421
3422 if(kpki_gear == 0)
3423 kpki_cnt_idx = 0;
3424 else
3425 {
3426 if(kpki_cnt_idx == 7000)
3427 {
3428 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1); // for > 150% overmodulation
3429 kpki_cnt_idx = 0;
3430 }
3431 kpki_cnt_idx++;
3432 }
3433 }
3434 else
3435 {
3436 msWriteBit(KPKI_ADJ_EN, 0, _BIT0); // real HW_KPKI_disable
3437
3438 if(crjtr_det_cnt < 6)
3439 {
3440 msVifCrKpKiAutoAdjust(VIFInitialIn_inst.VifCrKpKiAdjustThr1, VIFInitialIn_inst.VifCrKpKiAdjustThr2);
3441
3442 if(g_VifCrKpKiAdjLoopCnt == 0)
3443 {
3444 crjtr_det_cnt++;
3445 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3446 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3447
3448 if(g_VifCrKp != VIFInitialIn_inst.VifCrKp) // If carrier drift
3449 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1);
3450 else
3451 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1);
3452 }
3453 }
3454 }
3455 }
3456 else
3457 {
3458 msWriteByteMask(CR_KP_SW, VIFInitialIn_inst.VifCrKp, 0x0F); // kp software mode
3459 msWriteByteMask(CR_KI_SW, VIFInitialIn_inst.VifCrKi<<4, 0xF0); // ki software mode
3460 }
3461 }
3462
3463 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3464 {
3465 HAL_VIF_Delay1ms(50); // for Fluke 54200 50dBuV <-> 51dBuV switch
3466 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3467 {
3468 // for debug
3469 if (msReadByte(HALVIFDBG_BIT) & 0x08)
3470 {
3471 printf("VIF msVifInitial!!!");
3472 }
3473 msVifInitial();
3474 }
3475 }
3476
3477 // for debug
3478 if (msReadByte(HALVIFDBG_BIT) & 0x40)
3479 {
3480 if (VIFInitialIn_inst.VifCrKpKiAdjust==1 )
3481 {
3482 VIFInitialIn_inst.VifCrKpKiAdjust=0;
3483 }
3484 printf("\r\n Disable VIF KpKi auto adjust");
3485 }
3486
3487 // for debug
3488 if ((msReadByte(HALVIFDBG_BIT) & 0x80) || (VIFInitialIn_inst.VifReserve & _BIT3))
3489 {
3490 U8 ir_rate;
3491
3492 // IR Rate
3493 ir_rate = msReadByte(IF_RATE);
3494 if (ir_rate==0x49)
3495 printf("\r\n IF_FREQ_3395 IF_FREQ_3890");
3496 else if (ir_rate==0xE3)
3497 printf("\r\n IF_FREQ_3800");
3498 else if (ir_rate==0x8E)
3499 printf("\r\n IF_FREQ_3950");
3500 else if (ir_rate==0xAA)
3501 printf("\r\n IF_FREQ_4575");
3502 else if (ir_rate==0xC7)
3503 printf("\r\n IF_FREQ_5875");
3504 else
3505 printf("\r\n unknown");
3506
3507 printf(" IR_RATE=0x%x ", ir_rate);
3508
3509 // sound system
3510 if (g_ucVifSoundSystemType==0)
3511 printf("\r\n VIF_SOUND_B");
3512 else if (g_ucVifSoundSystemType==1)
3513 printf("\r\n VIF_SOUND_B_NICAM");
3514 else if (g_ucVifSoundSystemType==2)
3515 printf("\r\n VIF_SOUND_GH");
3516 else if (g_ucVifSoundSystemType==3)
3517 printf("\r\n VIF_SOUND_GH_NICAM");
3518 else if (g_ucVifSoundSystemType==4)
3519 printf("\r\n VIF_SOUND_I");
3520 else if (g_ucVifSoundSystemType==5)
3521 printf("\r\n VIF_SOUND_DK1");
3522 else if (g_ucVifSoundSystemType==6)
3523 printf("\r\n VIF_SOUND_DK2");
3524 else if (g_ucVifSoundSystemType==7)
3525 printf("\r\n VIF_SOUND_DK3");
3526 else if (g_ucVifSoundSystemType==8)
3527 printf("\r\n VIF_SOUND_DK_NICAM");
3528 else if (g_ucVifSoundSystemType==9)
3529 printf("\r\n VIF_SOUND_L");
3530 else if (g_ucVifSoundSystemType==10)
3531 printf("\r\n VIF_SOUND_LL");
3532 else if (g_ucVifSoundSystemType==11)
3533 printf("\r\n VIF_SOUND_MN");
3534 else
3535 printf("\r\n unknown");
3536
3537 printf(" sound system=%d", (BYTE)g_ucVifSoundSystemType);
3538
3539 // freq band select
3540 printf("\r\n band=%d", (BYTE)VIFInitialIn_inst.VifFreqBand);
3541 }
3542 break;
3543
3544 default:
3545 g_ucVifStatusStep++;
3546 break;
3547 }
3548
3549 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
3550 {
3551 if (g_bCheckModulationType == 0)
3552 msVifInitial();
3553 if ((g_ucVifSoundSystemType == VIF_SOUND_L) && (g_bCheckIFFreq == 1))
3554 msVifInitial();
3555 if ((g_ucVifSoundSystemType == VIF_SOUND_LL) && (g_bCheckIFFreq == 0))
3556 msVifInitial();
3557 }
3558 else
3559 {
3560 if (g_bCheckModulationType == 1)
3561 msVifInitial();
3562 }
3563 }
3564
msVifSeriousACIDetection(void)3565 void msVifSeriousACIDetection(void)
3566 {
3567 BYTE AGC_Ref, AGC_Mean256, temp;
3568 BYTE PGA = 0, ADC_Index = 0, ADC_Underflow_Index = 0, ADC_Overflow_Index = 0;
3569 WORD VGA = 0;
3570
3571 temp = msReadByte(AGC_REF);
3572 AGC_Ref =(temp << 1);
3573 AGC_Mean256 = msReadByte(AGC_MEAN256);
3574
3575 if(SeriousACI_Index == 1)
3576 {
3577 VGA = msRead2Bytes(AGC_VGA);
3578 PGA = msReadByte(AGC_PGA2C);
3579 ADC_Index = RIU_ReadByte(0x12870L);
3580 ADC_Underflow_Index = ADC_Index & 0x02;
3581 ADC_Overflow_Index = ADC_Index & 0x04;
3582
3583 if((ADC_Underflow_Index == 0x02 ||ADC_Overflow_Index == 0x04)&&(VGA == 0x7000)&&(PGA == 0x1F)&&(AGC_Change_Index == 0)
3584 &&(AGC_Ref - AGC_Mean256 > 5))
3585 {
3586 msWriteByte(AGC_REF, VIFInitialIn_inst.VifADCOverflowAGCREF);
3587 msWriteBit(BYPASS_SOS21, 1 , _BIT2);
3588 msWriteBit(BYPASS_SOS22, 1 , _BIT3);
3589 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, 0x00);
3590 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE+1, 0x04);
3591 AGC_Change_Index = 1;
3592 }
3593 SeriousACI_Index = 0;
3594 }
3595 SeriousACI_Index = SeriousACI_Index + 1;
3596 }
3597
msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1,BYTE VifCrKpKiAdjustThr2)3598 void msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1, BYTE VifCrKpKiAdjustThr2)
3599 {
3600 MS_S16 CrJtrMax, CrJtrMin;
3601 static DWORD CrJtrDelta;
3602
3603 HALVIFDBG(printf("\r\msVifCrKpKiAutoAdjust()"));
3604
3605 msWriteBit(CR_STATUS_LATCH_EN, 1, _BIT4); // latch CR loop-filter
3606
3607 msWriteByteMask(CR_JTR_SEL, 0, _BIT3|_BIT2|_BIT1|_BIT0); // 0: max
3608 CrJtrMax = msRead2Bytes(CR_JTR_OUT);
3609
3610 msWriteByteMask(CR_JTR_SEL, _BIT0, _BIT3|_BIT2|_BIT1|_BIT0); // 1: min
3611 CrJtrMin = msRead2Bytes(CR_JTR_OUT);
3612
3613 msWriteBit(CR_STATUS_LATCH_EN, 0, _BIT4); // un-latch CR loop-filter status
3614
3615 if(g_VifCrKpKiAdjLoopCnt == 0) // reset delta value
3616 CrJtrDelta = 0;
3617
3618 CrJtrDelta += (DWORD)(CrJtrMax - CrJtrMin);
3619
3620 if (++g_VifCrKpKiAdjLoopCnt == 32) // 32 samples
3621 {
3622 CrJtrDelta = CrJtrDelta >> 5; // divided by 32
3623 CrJtrDelta = CrJtrDelta >> 7;
3624 if (g_VifCrKp >= VIFInitialIn_inst.VifCrKp)
3625 {
3626 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3627 {
3628 g_VifCrKp -= 0x02;
3629 g_VifCrKi -= 0x02;
3630 }
3631 else if ((CrJtrDelta < VifCrKpKiAdjustThr2) && (CrJtrDelta >= VifCrKpKiAdjustThr1))
3632 {
3633 g_VifCrKp -= 0x01;
3634 g_VifCrKi -= 0x01;
3635 }
3636 }
3637 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 1)
3638 {
3639 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3640 {
3641 g_VifCrKp -= 0x01;
3642 g_VifCrKi -= 0x01;
3643 }
3644 else if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3645 {
3646 g_VifCrKp += 0x01 ;
3647 g_VifCrKi += 0x01;
3648 }
3649 }
3650 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 2)
3651 {
3652 if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3653 {
3654 g_VifCrKp += 0x02;
3655 g_VifCrKi += 0x02;
3656 }
3657 else if (CrJtrDelta < VifCrKpKiAdjustThr2 - 3)
3658 {
3659 g_VifCrKp += 0x01;
3660 g_VifCrKi += 0x01;
3661 }
3662 }
3663
3664 g_VifCrKpKiAdjLoopCnt = 0;
3665 if (msReadByte(HALVIFDBG_BIT) & 0x20)
3666 {
3667 printf("\r\ng_ucVifStatusStep = %d", g_ucVifStatusStep);
3668 printf("\nKi/Kp = %x%x", g_VifCrKi, g_VifCrKp);
3669 printf("\nCrJtrMax = %x", CrJtrMax >> 7);
3670 printf("\nCrJtrMin = %x", CrJtrMin >> 7);
3671 printf("\r\nCrJtrDelta = %x", (WORD)((CrJtrDelta & 0xFFFF0000) >> 16));
3672 printf("%x\r\n",(WORD)(CrJtrDelta & 0x0000FFFF));
3673 }
3674 }
3675 }
3676
msVifReadCRFOE(void)3677 U8 msVifReadCRFOE(void)
3678 {
3679 HALVIFDBG(printf("\r\nmsVifReadCRFOE()"));
3680
3681 if (!_hal_VIF.bBaseAddrInitialized) return 0;
3682
3683 return msReadByte(CR_FOE);
3684 }
3685
msVifReadLockStatus(void)3686 U8 msVifReadLockStatus(void)
3687 {
3688 HALVIFDBG(printf("\r\nmsVifReadLockStatus()"));
3689
3690 if (!_hal_VIF.bBaseAddrInitialized) return 0;
3691
3692 return msReadByte(CR_LOCK_STATUS);
3693 }
3694
msVifLoadEQCoeff(BYTE VifSoundStandard)3695 void msVifLoadEQCoeff(BYTE VifSoundStandard)
3696 {
3697 U8 u8index;
3698
3699 HALVIFDBG(printf("\r\n msVifLoadEQCoeff()"));
3700
3701 // set coef
3702 RIU_WriteByte(0x120A0L, 0x01); // VIF use DVB SRAM and FIR
3703 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl
3704 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl
3705 msWriteBit(BYPASS_EQFIR, 1, _BIT0); // EQ BYPASS
3706
3707 if(VifSoundStandard == VIF_SOUND_MN)
3708 {
3709 for(u8index = 0; u8index < 46; ++u8index)
3710 {
3711 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]+0x8000);
3712 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]);
3713 }
3714 }
3715 else
3716 {
3717 for(u8index = 0; u8index < 46; ++u8index)
3718 {
3719 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]+0x8000);
3720 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]);
3721 }
3722 }
3723 msWriteBit(BYPASS_EQFIR , 0 , _BIT0); // EQ not BYPASS
3724 }
3725
msVifShiftClk(BYTE VifShiftClk)3726 void msVifShiftClk(BYTE VifShiftClk)
3727 {
3728 if(VIF_IS_ADC_48MHz == 0)
3729 {
3730 if (VifShiftClk == 1)
3731 {
3732 //g_VifShiftClk = 1; // 0x1121_D3
3733 msWriteByte(VIF_RF_RESERVED_1+1, 0x01);
3734
3735 msWriteByte(0x12866L, 0x00);//loop divider
3736 msWriteByte(0x12867L, 0x23);
3737 if (VIFInitialIn_inst.VifTunerType == 0)
3738 {
3739 // move to clk 42 Mhz
3740 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
3741 msWriteByte(CR_RATE+1, 0xDB);
3742 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3743 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3744
3745 // move to clk 140 Mhz
3746 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
3747 msWriteByte(IF_RATE+1, 0x83);
3748 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
3749 }
3750 }
3751 else if(VifShiftClk == 2)
3752 {
3753 //g_VifShiftClk = 2; // 0x1121_D3
3754 msWriteByte(VIF_RF_RESERVED_1+1, 0x02);
3755
3756 msWriteByte(0x12866L, 0x00);//loop divider
3757 msWriteByte(0x12867L, 0x25);
3758 if (VIFInitialIn_inst.VifTunerType == 0)
3759 {
3760 // move to clk 44.4 Mhz
3761 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
3762 msWriteByte(CR_RATE+1, 0x9F);
3763 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
3764 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3765
3766 // move to clk 148 Mhz
3767 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
3768 msWriteByte(IF_RATE+1, 0xF2);
3769 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
3770 }
3771 }
3772 else
3773 {
3774 //g_VifShiftClk = 0; // 0x1121_D3
3775 msWriteByte(VIF_RF_RESERVED_1+1, 0x00);
3776
3777 msWriteByte(0x12866L, 0x00);//loop divider
3778 msWriteByte(0x12867L, 0x24);
3779 if (VIFInitialIn_inst.VifTunerType == 0)
3780 {
3781 // move to clk 43.2 Mhz
3782 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
3783 msWriteByte(CR_RATE+1, 0x38);
3784 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3785 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3786
3787 // move to clk 142 Mhz
3788 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
3789 msWriteByte(IF_RATE+1, 0x38);
3790 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
3791 }
3792 }
3793 }
3794 }
3795
HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)3796 void HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)
3797 {
3798 HALVIFDBG(printf("HAL_VIF_BypassDBBAudioFilter() bEnableq=%d\n",bEnable));
3799 msWriteBit(A_DAGC_SEL, (!bEnable), _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
3800 }
3801
HAL_VIF_GetInputLevelIndicator(void)3802 BOOL HAL_VIF_GetInputLevelIndicator(void)
3803 {
3804 BYTE ref, mean256, diff;
3805
3806 HALVIFDBG(printf("\r\nHAL_VIF_GetInputLevelIndicator()"));
3807
3808 ref = msReadByte(AGC_REF); // AGC ref
3809 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
3810
3811 if (g_bCheckModulationType == 0)
3812 diff = 0x15; // negative modulation
3813 else
3814 diff = 0x0A; // positive modulation
3815
3816 if (mean256 >= (ref-diff))
3817 return 1;
3818 else
3819 return 0;
3820 }
3821
HAL_VIF_GetCrPDInverse(void)3822 U8 HAL_VIF_GetCrPDInverse(void)
3823 {
3824 HALVIFDBG(printf("HAL_VIF_GetCrPDInverse() %d \n", 0));
3825 if ((HAL_VIF_ReadByte(CR_PD_IMAG_INV) & _BIT1)!=0)
3826 return 1;
3827 else
3828 return 0;
3829 }
3830
HAL_VIF_SetCrPDInverse(BOOL bEnable)3831 void HAL_VIF_SetCrPDInverse(BOOL bEnable)
3832 {
3833 HALVIFDBG(printf("HAL_VIF_SetCrPDInverse() bEnableq=%d\n",bEnable));
3834 msWriteBit(CR_PD_IMAG_INV, (bEnable), _BIT1); // 0: disable; 1: enable
3835 }
3836
3837 #endif //_HALVIF_C_
3838
3839