Lines Matching refs:RIU_WriteRegBit
142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
2933 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
3128 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3134 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3167 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3173 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3214 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3215 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
3431 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3433 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3472 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
3482 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
3483 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
3484 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
3488 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
3489 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
3506 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
3508 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
3509 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
3529 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
3589 RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5)); in HAL_AVD_AFEC_SetPatchFlag()
3642 RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6] in HAL_AVD_AFEC_SetInput()
3656 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3661 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3676 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3681 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3698 RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3703 RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C in HAL_AVD_AFEC_SetInput()
3717 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
3722 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
3736 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD in HAL_AVD_AFEC_SetInput()
3756 RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3760 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3765 RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3766 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3767 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move … in HAL_AVD_AFEC_SetInput()
3768 RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware in HAL_AVD_AFEC_SetInput()
3775 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3776 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3777 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3778 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3787 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
3791 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
3792 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
3793 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
3794 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
3881 RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7))); in HAL_AVD_AFEC_SetHTotal()
3899 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
3903 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
3938 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
3972 RIU_WriteRegBit( BK_AFEC_CE, bEnable, BIT(0)); in HAL_AVD_AFEC_EnableForceMode()
4023 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
4024 RIU_WriteRegBit(BK_AFEC_CF, bEnable, BIT(2)); in HAL_AVD_AFEC_EnableCVBSLPF()
4065 RIU_WriteRegBit(BK_AFEC_D4, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableVBIDPLSpeedup()
4084 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4086 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
4105 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4107 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
4126 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4128 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
4272 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); // BK_COMB_4C[7] COMB memory prote… in HAL_AVD_COMB_SetMemoryProtect()
4292 RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
4293 RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
4297 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
4298 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
4319 … RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
4331 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
4558 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
4565 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
4571 RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
4578 RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
4653 RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
4657 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
4726 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4728 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
4753 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()
4771 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()