1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 #ifndef _HALVIF_C_
95 #define _HALVIF_C_
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #include "MsCommon.h"
102 #include "MsIRQ.h"
103 #include "MsOS.h"
104 #include "MsTypes.h"
105 #include "drvMMIO.h"
106
107 // Internal Definition
108 #include "regVIF.h"
109 #include "VIF.h"
110 #include "halVIF.h"
111 #include "halVIF_Customer.h"
112 #include "asmCPU.h"
113 //-------------------------------------------------------------------------------------------------
114 // Driver Compiler Options
115 //-------------------------------------------------------------------------------------------------
116 #define HALVIFDBG(x) //x
117 #define HALVIFDBG_BIT (DBB1_REG_BASE+0x06) // Bit 4~7
118 #define HALVIFDBG1_BIT (DBB1_REG_BASE+0x04) // Bit 1
119 #define HALVIFDBG2_BIT (DBB1_REG_BASE+0xF6) // Bit 0~1
120 //-------------------------------------------------------------------------------------------------
121 // extern function
122 //-------------------------------------------------------------------------------------------------
123 #define HAL_VIF_Delay1ms(x) MAsm_CPU_DelayMs(x)
124 #define HAL_VIF_Delay1us(x) MAsm_CPU_DelayUs(x)
125 #define HAL_VIF_GetSystemTime() MsOS_GetSystemTime()
126 //-------------------------------------------------------------------------------------------------
127 // Local Defines
128 //-------------------------------------------------------------------------------------------------
129 #define __CHIP_VERSION 0x1ECF
130
131 #ifndef _END_OF_TBL_
132 #define _END_OF_TBL_ 0xFFFF
133 #endif
134
135 #define msRead2Bytes(x) RIU_Read2Byte(x)
136 #define msReadByte(x) RIU_ReadByte(x)
137
138 // Base address should be initial.
139 #if defined (__aeon__) // Non-OS
140 #define BASEADDR_RIU 0xA0000000UL
141 #else // ecos
142 #define BASEADDR_RIU 0xBF800000UL
143 #endif
144
145 #define RIU_MACRO_START do {
146 #define RIU_MACRO_END } while (0)
147
148 // Address bus of RIU is 16 bits.
149 #define RIU_READ_BYTE(addr) ( READ_BYTE( _hal_VIF.virtVIFBaseAddr + (addr) ) )
150 #define RIU_READ_2BYTE(addr) ( READ_WORD( _hal_VIF.virtVIFBaseAddr + (addr) ) )
151 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _hal_VIF.virtVIFBaseAddr + (addr), val) }
152 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _hal_VIF.virtVIFBaseAddr + (addr), val) }
153
154 // Standard Form
155
156 #define RIU_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
157
158 #define RIU_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1))
159
160 #define RIU_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
161
162 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
163 RIU_MACRO_START \
164 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
165 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
166 RIU_MACRO_END
167
168 #define RIU_WriteByte( u32Reg, u8Val ) \
169 RIU_MACRO_START \
170 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
171 RIU_MACRO_END
172
173 #define RIU_Write2Byte( u32Reg, u16Val ) \
174 RIU_MACRO_START \
175 if ( ((u32Reg) & 0x01) ) \
176 { \
177 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
178 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
179 } \
180 else \
181 { \
182 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
183 } \
184 RIU_MACRO_END
185
186 #define RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
187 RIU_MACRO_START \
188 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
189 RIU_MACRO_END
190
191 // Address bus of RIU is 16 bits for PM bank.
192 #define PM_RIU_READ_BYTE(addr) ( READ_BYTE(virtPMBank + (addr) ) )
193 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD(virtPMBank+ (addr) ) )
194 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE(virtPMBank + (addr), val) }
195 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD(virtPMBank + (addr), val) }
196
197 // Standard Form for PM bank
198 #define PM_RIU_ReadByte( u32Reg ) PM_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1))
199
200 #define PM_RIU_Read2Byte( u32Reg ) (PM_RIU_READ_2BYTE((u32Reg)<<1))
201
202 #define PM_RIU_ReadRegBit( u32Reg, u8Mask ) (PM_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask))
203
204 #define PM_RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \
205 RIU_MACRO_START \
206 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \
207 (PM_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \
208 RIU_MACRO_END
209
210 #define PM_RIU_WriteByte( u32Reg, u8Val ) \
211 RIU_MACRO_START \
212 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \
213 RIU_MACRO_END
214
215 #define PM_RIU_Write2Byte( u32Reg, u16Val ) \
216 RIU_MACRO_START \
217 if ( ((u32Reg) & 0x01) ) \
218 { \
219 PM_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \
220 PM_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \
221 } \
222 else \
223 { \
224 PM_RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \
225 } \
226 RIU_MACRO_END
227
228 #define PM_RIU_WriteByteMask( u32Reg, u8Val, u8Msk ) \
229 RIU_MACRO_START \
230 PM_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (PM_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \
231 RIU_MACRO_END
232
233 //-------------------------------------------------------------------------------------------------
234 // Local Structures
235 //-------------------------------------------------------------------------------------------------
236 typedef struct
237 {
238 MS_VIRT virtVIFBaseAddr;
239 BOOL bBaseAddrInitialized;
240 } hal_VIF_t;
241
242 //-------------------------------------------------------------------------------------------------
243 // Local Variables
244 //-------------------------------------------------------------------------------------------------
245 static hal_VIF_t _hal_VIF ={BASEADDR_RIU, 0};
246 extern VIFInitialIn VIFInitialIn_inst;
247 //extern VIFSOS33 sVIFSOS33;
248 extern BOOL bEnableUsrSteadyAgcK;
249 extern U8 u8UsrSteadyAgcK;
250 extern BOOL bEnableUsrNonSteadyAgcK;
251 extern U8 u8UsrNonSteadyAgcK;
252 /////////////////////////////////////////////////////
253 BOOL AGC_Change_Index; //for Serious ACI Parameter
254 U16 SeriousACI_Index = 0;
255 ////////////////////////////////////////////////////
256 BYTE g_ucVifStatusStep;
257 BOOL g_bCheckIFFreq; // 0: 38.9 MHz (PAL/SECAM L); 1: 33.9 MHz (SECAM L')
258 BOOL g_VifHWKpKiFlag;
259 BYTE g_VifCrKp;
260 BYTE g_VifCrKi;
261 BYTE g_VifCrKpKiAdjLoopCnt;
262 BOOL g_bCheckModulationType; // 0: negative; 1: positive
263 BYTE g_ucVifSoundSystemType;
264 ////////////////////////////////////////////////////
265
266 #define VIF_IS_ADC_48MHz 1 // 0:144MHz ; 1:48MHz
267 #define VIF_IS_EQ_IIR 0 // 0:FIR ; 1:IIR
268
269 //-------------------------------------------------------------------------------------------------
270 // Local code data
271 //-------------------------------------------------------------------------------------------------
272 MS_VIF_REG_TYPE VIF_GDE_PEAKING_1dB[]=
273 {
274 {SOS21_C0_L,0xc1}, // SOS21 peaking
275 {SOS21_C0_H,0x02},
276 {SOS21_C1_L,0x87},
277 {SOS21_C1_H,0x06},
278 {SOS21_C2_L,0x08},
279 {SOS21_C2_H,0x02},
280 {SOS21_C3_L,0x3f},
281 {SOS21_C3_H,0x05},
282 {SOS21_C4_L,0x70},
283 {SOS21_C4_H,0x01},
284 {_END_OF_TBL_,0x00},
285 };
286 MS_VIF_REG_TYPE VIF_GDE_PEAKING_2dB[]=
287 {
288 {SOS21_C0_L,0xa4}, // SOS21 peaking
289 {SOS21_C0_H,0x02},
290 {SOS21_C1_L,0x8e},
291 {SOS21_C1_H,0x06},
292 {SOS21_C2_L,0x12},
293 {SOS21_C2_H,0x02},
294 {SOS21_C3_L,0x5c},
295 {SOS21_C3_H,0x05},
296 {SOS21_C4_L,0x60},
297 {SOS21_C4_H,0x01},
298 {_END_OF_TBL_,0x00},
299 };
300 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB[]=
301 {
302 {SOS21_C0_L,0xc1}, // SOS21 peaking
303 {SOS21_C0_H,0x02},
304 {SOS21_C1_L,0x87},
305 {SOS21_C1_H,0x06},
306 {SOS21_C2_L,0x1c},
307 {SOS21_C2_H,0x02},
308 {SOS21_C3_L,0x3f},
309 {SOS21_C3_H,0x05},
310 {SOS21_C4_L,0x5d},
311 {SOS21_C4_H,0x01},
312 {_END_OF_TBL_,0x00},
313 };
314 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB[]=
315 {
316 {SOS21_C0_L,0xc1}, // SOS21 peaking
317 {SOS21_C0_H,0x02},
318 {SOS21_C1_L,0x87},
319 {SOS21_C1_H,0x06},
320 {SOS21_C2_L,0x28},
321 {SOS21_C2_H,0x02},
322 {SOS21_C3_L,0x3f},
323 {SOS21_C3_H,0x05},
324 {SOS21_C4_L,0x51},
325 {SOS21_C4_H,0x01},
326 {_END_OF_TBL_,0x00},
327 };
328 MS_VIF_REG_TYPE VIF_GDE_PEAKING_3dB_VSB[]=
329 {
330 {SOS21_C0_L,0xf5}, // SOS21 peaking
331 {SOS21_C0_H,0x02},
332 {SOS21_C1_L,0x23},
333 {SOS21_C1_H,0x06},
334 {SOS21_C2_L,0x07},
335 {SOS21_C2_H,0x02},
336 {SOS21_C3_L,0x0b},
337 {SOS21_C3_H,0x05},
338 {SOS21_C4_L,0xd5},
339 {SOS21_C4_H,0x01},
340 {_END_OF_TBL_,0x00},
341 };
342 MS_VIF_REG_TYPE VIF_GDE_PEAKING_4dB_VSB[]=
343 {
344 {SOS21_C0_L,0xf5}, // SOS21 peaking
345 {SOS21_C0_H,0x02},
346 {SOS21_C1_L,0x23},
347 {SOS21_C1_H,0x06},
348 {SOS21_C2_L,0x0a},
349 {SOS21_C2_H,0x02},
350 {SOS21_C3_L,0x0b},
351 {SOS21_C3_H,0x05},
352 {SOS21_C4_L,0xd2},
353 {SOS21_C4_H,0x01},
354 {_END_OF_TBL_,0x00},
355 };
356 MS_VIF_REG_TYPE VIF_GDE_PEAKING_5dB_VSB[]=
357 {
358 {SOS21_C0_L,0xf5}, // SOS21 peaking
359 {SOS21_C0_H,0x02},
360 {SOS21_C1_L,0x23},
361 {SOS21_C1_H,0x06},
362 {SOS21_C2_L,0x0e},
363 {SOS21_C2_H,0x02},
364 {SOS21_C3_L,0x0b},
365 {SOS21_C3_H,0x05},
366 {SOS21_C4_L,0xcf},
367 {SOS21_C4_H,0x01},
368 {_END_OF_TBL_,0x00},
369 };
370 MS_VIF_REG_TYPE VIF_GDE_PEAKING_NULL[]=
371 {
372 {SOS21_C0_L,0x00}, // SOS21
373 {SOS21_C0_H,0x00},
374 {SOS21_C1_L,0x00},
375 {SOS21_C1_H,0x00},
376 {SOS21_C2_L,0x00},
377 {SOS21_C2_H,0x00},
378 {SOS21_C3_L,0x00},
379 {SOS21_C3_H,0x00},
380 {SOS21_C4_L,0x00},
381 {SOS21_C4_H,0x02},
382 {_END_OF_TBL_,0x00},
383 };
384 MS_VIF_REG_TYPE VIF_GDE_YCDelay_VSB[]=
385 {
386 {SOS22_C0_L,0x15}, // SOS22 Y/C delay
387 {SOS22_C0_H,0x02},
388 {SOS22_C1_L,0x84},
389 {SOS22_C1_H,0x06},
390 {SOS22_C2_L,0x7c},
391 {SOS22_C2_H,0x01},
392 {SOS22_C3_L,0xeb},
393 {SOS22_C3_H,0x05},
394 {SOS22_C4_L,0x00},
395 {SOS22_C4_H,0x02},
396 {_END_OF_TBL_,0x00},
397 };
398 MS_VIF_REG_TYPE VIF_GDE_YCDelay_NULL[]=
399 {
400 {SOS22_C0_L,0x00}, // SOS22
401 {SOS22_C0_H,0x00},
402 {SOS22_C1_L,0x00},
403 {SOS22_C1_H,0x00},
404 {SOS22_C2_L,0x00},
405 {SOS22_C2_H,0x00},
406 {SOS22_C3_L,0x00},
407 {SOS22_C3_H,0x00},
408 {SOS22_C4_L,0x00},
409 {SOS22_C4_H,0x02},
410 {_END_OF_TBL_,0x00},
411 };
412 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_R[]=
413 {
414 {SOS31_C0_L,0xcc}, // SOS31
415 {SOS31_C0_H,0x00},
416 {SOS31_C1_L,0x6c},
417 {SOS31_C1_H,0x07},
418 {SOS31_C2_L,0x94},
419 {SOS31_C2_H,0x00},
420 {SOS31_C3_L,0x34},
421 {SOS31_C3_H,0x07},
422 {SOS31_C4_L,0x00},
423 {SOS31_C4_H,0x02},
424 {SOS32_C0_L,0xb4}, // SOS32
425 {SOS32_C0_H,0x02},
426 {SOS32_C1_L,0xf8},
427 {SOS32_C1_H,0x06},
428 {SOS32_C2_L,0x08},
429 {SOS32_C2_H,0x01},
430 {SOS32_C3_L,0x4c},
431 {SOS32_C3_H,0x05},
432 {SOS32_C4_L,0x00},
433 {SOS32_C4_H,0x02},
434 {_END_OF_TBL_,0x00},
435 };
436 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_Low_L[]=
437 {
438 {SOS31_C0_L,0x3c}, // SOS31
439 {SOS31_C0_H,0x02},
440 {SOS31_C1_L,0xb8},
441 {SOS31_C1_H,0x06},
442 {SOS31_C2_L,0x48},
443 {SOS31_C2_H,0x01},
444 {SOS31_C3_L,0xc4},
445 {SOS31_C3_H,0x05},
446 {SOS31_C4_L,0x00},
447 {SOS31_C4_H,0x02},
448 {SOS32_C0_L,0xd9}, // SOS32
449 {SOS32_C0_H,0x02},
450 {SOS32_C1_L,0xf7},
451 {SOS32_C1_H,0x06},
452 {SOS32_C2_L,0x0a},
453 {SOS32_C2_H,0x01},
454 {SOS32_C3_L,0x28},
455 {SOS32_C3_H,0x05},
456 {SOS32_C4_L,0x00},
457 {SOS32_C4_H,0x02},
458 {_END_OF_TBL_,0x00},
459 };
460 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_R[]=
461 {
462 {SOS31_C0_L,0xcc}, // SOS31
463 {SOS31_C0_H,0x00},
464 {SOS31_C1_L,0x6c},
465 {SOS31_C1_H,0x07},
466 {SOS31_C2_L,0x94},
467 {SOS31_C2_H,0x00},
468 {SOS31_C3_L,0x34},
469 {SOS31_C3_H,0x07},
470 {SOS31_C4_L,0x00},
471 {SOS31_C4_H,0x02},
472 {SOS32_C0_L,0xc7}, // SOS32
473 {SOS32_C0_H,0x02},
474 {SOS32_C1_L,0xd8},
475 {SOS32_C1_H,0x06},
476 {SOS32_C2_L,0x28},
477 {SOS32_C2_H,0x01},
478 {SOS32_C3_L,0x39},
479 {SOS32_C3_H,0x05},
480 {SOS32_C4_L,0x00},
481 {SOS32_C4_H,0x02},
482 {_END_OF_TBL_,0x00},
483 };
484 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_High_L[]=
485 {
486 {SOS31_C0_L,0xcc}, // SOS31
487 {SOS31_C0_H,0x00},
488 {SOS31_C1_L,0x6c},
489 {SOS31_C1_H,0x07},
490 {SOS31_C2_L,0x94},
491 {SOS31_C2_H,0x00},
492 {SOS31_C3_L,0x34},
493 {SOS31_C3_H,0x07},
494 {SOS31_C4_L,0x00},
495 {SOS31_C4_H,0x02},
496 {SOS32_C0_L,0xb0}, // SOS32
497 {SOS32_C0_H,0x02},
498 {SOS32_C1_L,0x13},
499 {SOS32_C1_H,0x07},
500 {SOS32_C2_L,0xed},
501 {SOS32_C2_H,0x00},
502 {SOS32_C3_L,0x50},
503 {SOS32_C3_H,0x05},
504 {SOS32_C4_L,0x00},
505 {SOS32_C4_H,0x02},
506 {_END_OF_TBL_,0x00},
507 };
508 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_LG[]=
509 {
510 {SOS31_C0_L,0xab}, // SOS31
511 {SOS31_C0_H,0x02},
512 {SOS31_C1_L,0x9b},
513 {SOS31_C1_H,0x06},
514 {SOS31_C2_L,0x65},
515 {SOS31_C2_H,0x01},
516 {SOS31_C3_L,0x55},
517 {SOS31_C3_H,0x05},
518 {SOS31_C4_L,0x00},
519 {SOS31_C4_H,0x02},
520 {SOS32_C0_L,0xe1}, // SOS32
521 {SOS32_C0_H,0x02},
522 {SOS32_C1_L,0xf7},
523 {SOS32_C1_H,0x06},
524 {SOS32_C2_L,0x0a},
525 {SOS32_C2_H,0x01},
526 {SOS32_C3_L,0x1f},
527 {SOS32_C3_H,0x05},
528 {SOS32_C4_L,0x00},
529 {SOS32_C4_H,0x02},
530 {_END_OF_TBL_,0x00},
531 };
532 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_VSB_Philips[]=
533 {
534 {SOS31_C0_L,0x9f}, // SOS31
535 {SOS31_C0_H,0x02},
536 {SOS31_C1_L,0xa8},
537 {SOS31_C1_H,0x06},
538 {SOS31_C2_L,0x58},
539 {SOS31_C2_H,0x01},
540 {SOS31_C3_L,0x62},
541 {SOS31_C3_H,0x05},
542 {SOS31_C4_L,0x00},
543 {SOS31_C4_H,0x02},
544 {SOS32_C0_L,0xcd}, // SOS32
545 {SOS32_C0_H,0x02},
546 {SOS32_C1_L,0x05},
547 {SOS32_C1_H,0x07},
548 {SOS32_C2_L,0xfb},
549 {SOS32_C2_H,0x00},
550 {SOS32_C3_L,0x33},
551 {SOS32_C3_H,0x05},
552 {SOS32_C4_L,0x00},
553 {SOS32_C4_H,0x02},
554 {_END_OF_TBL_,0x00},
555 };
556 MS_VIF_REG_TYPE VIF_GDE_GroupDelay_NULL[]=
557 {
558 {SOS31_C0_L,0x00}, // SOS31
559 {SOS31_C0_H,0x00},
560 {SOS31_C1_L,0x00},
561 {SOS31_C1_H,0x00},
562 {SOS31_C2_L,0x00},
563 {SOS31_C2_H,0x00},
564 {SOS31_C3_L,0x00},
565 {SOS31_C3_H,0x00},
566 {SOS31_C4_L,0x00},
567 {SOS31_C4_H,0x02},
568 {SOS32_C0_L,0x00}, // SOS32
569 {SOS32_C0_H,0x00},
570 {SOS32_C1_L,0x00},
571 {SOS32_C1_H,0x00},
572 {SOS32_C2_L,0x00},
573 {SOS32_C2_H,0x00},
574 {SOS32_C3_L,0x00},
575 {SOS32_C3_H,0x00},
576 {SOS32_C4_L,0x00},
577 {SOS32_C4_H,0x02},
578 {_END_OF_TBL_,0x00},
579 };
580 MS_VIF_REG_TYPE VIF_PAL_B_A2[]=
581 {
582 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
583 {N_A1_C0_H,0x02},
584 {N_A1_C1_L,0x3c},
585 {N_A1_C1_H,0x06},
586 {N_A1_C2_L,0x37},
587 {N_A1_C2_H,0x05},
588 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
589 {N_A2_C0_H,0x02},
590 {N_A2_C1_L,0x3c},
591 {N_A2_C1_H,0x06},
592 {N_A2_C2_L,0x51},
593 {N_A2_C2_H,0x05},
594 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
595 {SOS12_C0_H,0x02},
596 {SOS12_C1_L,0x3c},
597 {SOS12_C1_H,0x06},
598 {SOS12_C2_L,0x00},
599 {SOS12_C2_H,0x02},
600 {SOS12_C3_L,0x37},
601 {SOS12_C3_H,0x05},
602 {SOS12_C4_L,0x00},
603 {SOS12_C4_H,0x02},
604 {_END_OF_TBL_,0x00}, // PAL B/G A2
605 };
606 MS_VIF_REG_TYPE VIF_PAL_B_NICAM[]=
607 {
608 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
609 {N_A1_C0_H,0x02},
610 {N_A1_C1_L,0x3c},
611 {N_A1_C1_H,0x06},
612 {N_A1_C2_L,0x37},
613 {N_A1_C2_H,0x05},
614 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
615 {N_A2_C0_H,0x02},
616 {N_A2_C1_L,0x3c},
617 {N_A2_C1_H,0x06},
618 {N_A2_C2_L,0x5d},
619 {N_A2_C2_H,0x05},
620 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
621 {SOS12_C0_H,0x02},
622 {SOS12_C1_L,0x3c},
623 {SOS12_C1_H,0x06},
624 {SOS12_C2_L,0x00},
625 {SOS12_C2_H,0x02},
626 {SOS12_C3_L,0x37},
627 {SOS12_C3_H,0x05},
628 {SOS12_C4_L,0x00},
629 {SOS12_C4_H,0x02},
630 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
631 };
632 MS_VIF_REG_TYPE VIF_PAL_GH_A2[]=
633 {
634 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
635 {N_A1_C0_H,0x02},
636 {N_A1_C1_L,0x3c},
637 {N_A1_C1_H,0x06},
638 {N_A1_C2_L,0x37},
639 {N_A1_C2_H,0x05},
640 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
641 {N_A2_C0_H,0x02},
642 {N_A2_C1_L,0x3c},
643 {N_A2_C1_H,0x06},
644 {N_A2_C2_L,0x51},
645 {N_A2_C2_H,0x05},
646 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
647 {SOS12_C0_H,0x02},
648 {SOS12_C1_L,0x3c},
649 {SOS12_C1_H,0x06},
650 {SOS12_C2_L,0x00},
651 {SOS12_C2_H,0x02},
652 {SOS12_C3_L,0x37},
653 {SOS12_C3_H,0x05},
654 {SOS12_C4_L,0x00},
655 {SOS12_C4_H,0x02},
656 {_END_OF_TBL_,0x00}, // PAL B/G A2
657 };
658 MS_VIF_REG_TYPE VIF_PAL_GH_NICAM[]=
659 {
660 {N_A1_C0_L,0x9f}, // Notch_A1, R = 0.94
661 {N_A1_C0_H,0x02},
662 {N_A1_C1_L,0x3c},
663 {N_A1_C1_H,0x06},
664 {N_A1_C2_L,0x37},
665 {N_A1_C2_H,0x05},
666 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
667 {N_A2_C0_H,0x02},
668 {N_A2_C1_L,0x3c},
669 {N_A2_C1_H,0x06},
670 {N_A2_C2_L,0x5d},
671 {N_A2_C2_H,0x05},
672 {SOS12_C0_L,0x9f}, // SOS12, R = 0.94
673 {SOS12_C0_H,0x02},
674 {SOS12_C1_L,0x3c},
675 {SOS12_C1_H,0x06},
676 {SOS12_C2_L,0x00},
677 {SOS12_C2_H,0x02},
678 {SOS12_C3_L,0x37},
679 {SOS12_C3_H,0x05},
680 {SOS12_C4_L,0x00},
681 {SOS12_C4_H,0x02},
682 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
683 };
684 MS_VIF_REG_TYPE VIF_SECAM_L_NICAM[]=
685 {
686 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
687 {N_A1_C0_H,0x02},
688 {N_A1_C1_L,0x3c},
689 {N_A1_C1_H,0x06},
690 {N_A1_C2_L,0xa9},
691 {N_A1_C2_H,0x05},
692 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
693 {N_A2_C0_H,0x02},
694 {N_A2_C1_L,0x3c},
695 {N_A2_C1_H,0x06},
696 {N_A2_C2_L,0x5d},
697 {N_A2_C2_H,0x05},
698 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
699 {SOS12_C0_H,0x02},
700 {SOS12_C1_L,0x3c},
701 {SOS12_C1_H,0x06},
702 {SOS12_C2_L,0x00},
703 {SOS12_C2_H,0x02},
704 {SOS12_C3_L,0xa9},
705 {SOS12_C3_H,0x05},
706 {SOS12_C4_L,0x00},
707 {SOS12_C4_H,0x02},
708 {_END_OF_TBL_,0x00}, // SECAM L NICAM
709 };
710
711 MS_VIF_REG_TYPE VIF_PAL_I_NICAM[]=
712 {
713 {N_A1_C0_L,0x6b}, // Notch_A1, R = 0.94
714 {N_A1_C0_H,0x02},
715 {N_A1_C1_L,0x3c},
716 {N_A1_C1_H,0x06},
717 {N_A1_C2_L,0x6e},
718 {N_A1_C2_H,0x05},
719 {N_A2_C0_L,0x2e}, // Notch_A2, R = 0.94
720 {N_A2_C0_H,0x02},
721 {N_A2_C1_L,0x3c},
722 {N_A2_C1_H,0x06},
723 {N_A2_C2_L,0xaf},
724 {N_A2_C2_H,0x05},
725 {SOS12_C0_L,0x6b}, // SOS12, R = 0.94
726 {SOS12_C0_H,0x02},
727 {SOS12_C1_L,0x3c},
728 {SOS12_C1_H,0x06},
729 {SOS12_C2_L,0x00},
730 {SOS12_C2_H,0x02},
731 {SOS12_C3_L,0x6e},
732 {SOS12_C3_H,0x05},
733 {SOS12_C4_L,0x00},
734 {SOS12_C4_H,0x02},
735 {_END_OF_TBL_,0x00}, // PAL I NICAM
736 };
737
738 MS_VIF_REG_TYPE VIF_SECAM_DK1_A2[]=
739 {
740 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
741 {N_A1_C0_H,0x02},
742 {N_A1_C1_L,0x3c},
743 {N_A1_C1_H,0x06},
744 {N_A1_C2_L,0xa9},
745 {N_A1_C2_H,0x05},
746 {N_A2_C0_L,0x4f}, // Notch_A2, R = 0.94
747 {N_A2_C0_H,0x02},
748 {N_A2_C1_L,0x3c},
749 {N_A2_C1_H,0x06},
750 {N_A2_C2_L,0x8c},
751 {N_A2_C2_H,0x05},
752 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
753 {SOS12_C0_H,0x02},
754 {SOS12_C1_L,0x3c},
755 {SOS12_C1_H,0x06},
756 {SOS12_C2_L,0x00},
757 {SOS12_C2_H,0x02},
758 {SOS12_C3_L,0xa9},
759 {SOS12_C3_H,0x05},
760 {SOS12_C4_L,0x00},
761 {SOS12_C4_H,0x02},
762 {_END_OF_TBL_,0x00}, // PAL DK1 A2
763 };
764
765 MS_VIF_REG_TYPE VIF_PAL_DK2_A2[]=
766 {
767 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
768 {N_A1_C0_H,0x02},
769 {N_A1_C1_L,0x3c},
770 {N_A1_C1_H,0x06},
771 {N_A1_C2_L,0xa9},
772 {N_A1_C2_H,0x05},
773 {N_A2_C0_L,0x18}, // Notch_A2, R = 0.94
774 {N_A2_C0_H,0x02},
775 {N_A2_C1_L,0x3c},
776 {N_A2_C1_H,0x06},
777 {N_A2_C2_L,0xc6},
778 {N_A2_C2_H,0x05},
779 {SOS12_C0_L,0x34}, // SOS12, R = 0.96
780 {SOS12_C0_H,0x02},
781 {SOS12_C1_L,0x3c},
782 {SOS12_C1_H,0x06},
783 {SOS12_C2_L,0x00},
784 {SOS12_C2_H,0x02},
785 {SOS12_C3_L,0xa9},
786 {SOS12_C3_H,0x05},
787 {SOS12_C4_L,0x00},
788 {SOS12_C4_H,0x02},
789 {_END_OF_TBL_,0x00}, // PAL DK2 A2
790 };
791
792 MS_VIF_REG_TYPE VIF_PAL_DK2_NICAM[]=
793 {
794 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
795 {N_A1_C0_H,0x02},
796 {N_A1_C1_L,0x3c},
797 {N_A1_C1_H,0x06},
798 {N_A1_C2_L,0xa9},
799 {N_A1_C2_H,0x05},
800 {N_A2_C0_L,0x7b}, // Notch_A2, R = 0.94
801 {N_A2_C0_H,0x02},
802 {N_A2_C1_L,0x3c},
803 {N_A2_C1_H,0x06},
804 {N_A2_C2_L,0x5d},
805 {N_A2_C2_H,0x05},
806 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
807 {SOS12_C0_H,0x02},
808 {SOS12_C1_L,0x3c},
809 {SOS12_C1_H,0x06},
810 {SOS12_C2_L,0x00},
811 {SOS12_C2_H,0x02},
812 {SOS12_C3_L,0xa9},
813 {SOS12_C3_H,0x05},
814 {SOS12_C4_L,0x00},
815 {SOS12_C4_H,0x02},
816 {_END_OF_TBL_,0x00}, // PAL DK NICAM
817 };
818
819 MS_VIF_REG_TYPE VIF_SECAM_DK3_A2[]=
820 {
821 {N_A1_C0_L,0x34}, // Notch_A1, R = 0.94
822 {N_A1_C0_H,0x02},
823 {N_A1_C1_L,0x3c},
824 {N_A1_C1_H,0x06},
825 {N_A1_C2_L,0xa9},
826 {N_A1_C2_H,0x05},
827 {N_A2_C0_L,0x86}, // Notch_A2, R = 0.94
828 {N_A2_C0_H,0x02},
829 {N_A2_C1_L,0x3c},
830 {N_A2_C1_H,0x06},
831 {N_A2_C2_L,0x51},
832 {N_A2_C2_H,0x05},
833 {SOS12_C0_L,0x34}, // SOS12, R = 0.94
834 {SOS12_C0_H,0x02},
835 {SOS12_C1_L,0x3c},
836 {SOS12_C1_H,0x06},
837 {SOS12_C2_L,0x00},
838 {SOS12_C2_H,0x02},
839 {SOS12_C3_L,0xa9},
840 {SOS12_C3_H,0x05},
841 {SOS12_C4_L,0x00},
842 {SOS12_C4_H,0x02},
843 {_END_OF_TBL_,0x00}, // PAL DK3 A2
844 };
845
846 MS_VIF_REG_TYPE VIF_GDE_BG_A2_NOTCH[]=
847 {
848 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
849 {N_A3_C0_H,0x02},
850 {N_A3_C1_L,0x3c},
851 {N_A3_C1_H,0x06},
852 {N_A3_C2_L,0x37},
853 {N_A3_C2_H,0x05},
854 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
855 {N_A4_C0_H,0x02},
856 {N_A4_C1_L,0x3c},
857 {N_A4_C1_H,0x06},
858 {N_A4_C2_L,0x51},
859 {N_A4_C2_H,0x05},
860 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
861 {N_A5_C0_H,0x01},
862 {N_A5_C1_L,0x1c},
863 {N_A5_C1_H,0x06},
864 {N_A5_C2_L,0xf7},
865 {N_A5_C2_H,0x06},
866 {_END_OF_TBL_,0x00}, // PAL B/G A2
867 };
868
869 MS_VIF_REG_TYPE VIF_GDE_BG_NICAM_NOTCH[]=
870 {
871 {N_A3_C0_L,0x9f}, // Notch_A3, R = 0.94
872 {N_A3_C0_H,0x02},
873 {N_A3_C1_L,0x3c},
874 {N_A3_C1_H,0x06},
875 {N_A3_C2_L,0x37},
876 {N_A3_C2_H,0x05},
877 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
878 {N_A4_C0_H,0x02},
879 {N_A4_C1_L,0x3c},
880 {N_A4_C1_H,0x06},
881 {N_A4_C2_L,0x5d},
882 {N_A4_C2_H,0x05},
883 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
884 {N_A5_C0_H,0x01},
885 {N_A5_C1_L,0x1c},
886 {N_A5_C1_H,0x06},
887 {N_A5_C2_L,0xf7},
888 {N_A5_C2_H,0x06},
889 {_END_OF_TBL_,0x00}, // PAL B/G NICAM
890 };
891
892 MS_VIF_REG_TYPE VIF_GDE_I_NOTCH[]=
893 {
894 {N_A3_C0_L,0x6b}, // Notch_A3, R = 0.94
895 {N_A3_C0_H,0x02},
896 {N_A3_C1_L,0x3c},
897 {N_A3_C1_H,0x06},
898 {N_A3_C2_L,0x6e},
899 {N_A3_C2_H,0x05},
900 {N_A4_C0_L,0x2e}, // Notch_A4, R = 0.94
901 {N_A4_C0_H,0x02},
902 {N_A4_C1_L,0x3c},
903 {N_A4_C1_H,0x06},
904 {N_A4_C2_L,0xaf},
905 {N_A4_C2_H,0x05},
906 {N_A5_C0_L,0xbb}, // Notch_A5 at 9.5MHz, image of audio 1 (bw 3.5, Apass 0.05)
907 {N_A5_C0_H,0x00},
908 {N_A5_C1_L,0x1c},
909 {N_A5_C1_H,0x06},
910 {N_A5_C2_L,0x40},
911 {N_A5_C2_H,0x07},
912 {_END_OF_TBL_,0x00}, // PAL I NICAM
913 };
914
915 MS_VIF_REG_TYPE VIF_GDE_DK1_NOTCH[]=
916 {
917 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
918 {N_A3_C0_H,0x02},
919 {N_A3_C1_L,0x3c},
920 {N_A3_C1_H,0x06},
921 {N_A3_C2_L,0xa9},
922 {N_A3_C2_H,0x05},
923 {N_A4_C0_L,0x4f}, // Notch_A4, R = 0.94
924 {N_A4_C0_H,0x02},
925 {N_A4_C1_L,0x3c},
926 {N_A4_C1_H,0x06},
927 {N_A4_C2_L,0x8c},
928 {N_A4_C2_H,0x05},
929 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
930 {N_A5_C0_H,0x01},
931 {N_A5_C1_L,0x1c},
932 {N_A5_C1_H,0x06},
933 {N_A5_C2_L,0xf7},
934 {N_A5_C2_H,0x06},
935 {_END_OF_TBL_,0x00}, // PAL DK1 A2
936 };
937
938 MS_VIF_REG_TYPE VIF_GDE_DK2_NOTCH[]=
939 {
940 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
941 {N_A3_C0_H,0x02},
942 {N_A3_C1_L,0x3c},
943 {N_A3_C1_H,0x06},
944 {N_A3_C2_L,0xa9},
945 {N_A3_C2_H,0x05},
946 {N_A4_C0_L,0x18}, // Notch_A4, R = 0.94
947 {N_A4_C0_H,0x02},
948 {N_A4_C1_L,0x3c},
949 {N_A4_C1_H,0x06},
950 {N_A4_C2_L,0xc6},
951 {N_A4_C2_H,0x05},
952 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
953 {N_A5_C0_H,0x01},
954 {N_A5_C1_L,0x1c},
955 {N_A5_C1_H,0x06},
956 {N_A5_C2_L,0xf7},
957 {N_A5_C2_H,0x06},
958 {_END_OF_TBL_,0x00}, // PAL DK2 A2
959 };
960
961 MS_VIF_REG_TYPE VIF_GDE_DK3_NOTCH[]=
962 {
963 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
964 {N_A3_C0_H,0x02},
965 {N_A3_C1_L,0x3c},
966 {N_A3_C1_H,0x06},
967 {N_A3_C2_L,0xa9},
968 {N_A3_C2_H,0x05},
969 {N_A4_C0_L,0x86}, // Notch_A4, R = 0.94
970 {N_A4_C0_H,0x02},
971 {N_A4_C1_L,0x3c},
972 {N_A4_C1_H,0x06},
973 {N_A4_C2_L,0x51},
974 {N_A4_C2_H,0x05},
975 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
976 {N_A5_C0_H,0x01},
977 {N_A5_C1_L,0x1c},
978 {N_A5_C1_H,0x06},
979 {N_A5_C2_L,0xf7},
980 {N_A5_C2_H,0x06},
981 {_END_OF_TBL_,0x00}, // PAL DK3 A2
982 };
983
984 MS_VIF_REG_TYPE VIF_GDE_DK_NICAM_NOTCH[]=
985 {
986 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
987 {N_A3_C0_H,0x02},
988 {N_A3_C1_L,0x3c},
989 {N_A3_C1_H,0x06},
990 {N_A3_C2_L,0xa9},
991 {N_A3_C2_H,0x05},
992 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
993 {N_A4_C0_H,0x02},
994 {N_A4_C1_L,0x3c},
995 {N_A4_C1_H,0x06},
996 {N_A4_C2_L,0x5d},
997 {N_A4_C2_H,0x05},
998 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
999 {N_A5_C0_H,0x01},
1000 {N_A5_C1_L,0x1c},
1001 {N_A5_C1_H,0x06},
1002 {N_A5_C2_L,0xf7},
1003 {N_A5_C2_H,0x06},
1004 {_END_OF_TBL_,0x00}, // PAL DK NICAM
1005 };
1006
1007 MS_VIF_REG_TYPE VIF_GDE_L_NICAM_NOTCH[]=
1008 {
1009 {N_A3_C0_L,0x34}, // Notch_A3, R = 0.94
1010 {N_A3_C0_H,0x02},
1011 {N_A3_C1_L,0x3c},
1012 {N_A3_C1_H,0x06},
1013 {N_A3_C2_L,0xa9},
1014 {N_A3_C2_H,0x05},
1015 {N_A4_C0_L,0x7b}, // Notch_A4, R = 0.94
1016 {N_A4_C0_H,0x02},
1017 {N_A4_C1_L,0x3c},
1018 {N_A4_C1_H,0x06},
1019 {N_A4_C2_L,0x5d},
1020 {N_A4_C2_H,0x05},
1021 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
1022 {N_A5_C0_H,0x01},
1023 {N_A5_C1_L,0x1c},
1024 {N_A5_C1_H,0x06},
1025 {N_A5_C2_L,0xf7},
1026 {N_A5_C2_H,0x06},
1027 {_END_OF_TBL_,0x00}, // SECAM L NICAM
1028 };
1029
1030 MS_VIF_REG_TYPE VIF_GDE_MN_NOTCH[]=
1031 {
1032 {N_A3_C0_L,0x1c}, // Notch_A3 (0.98)
1033 {N_A3_C0_H,0x03},
1034 {N_A3_C1_L,0x14},
1035 {N_A3_C1_H,0x06},
1036 {N_A3_C2_L,0xd4},
1037 {N_A3_C2_H,0x04},
1038 {N_A4_C0_L,0xe8}, // Notch_A4, R = 0.94
1039 {N_A4_C0_H,0x02},
1040 {N_A4_C1_L,0x3c},
1041 {N_A4_C1_H,0x06},
1042 {N_A4_C2_L,0xe8},
1043 {N_A4_C2_H,0x04},
1044 {N_A5_C0_L,0x02}, // Notch_A5 at 9MHz, image of audio 1 (bw 3.5, Apass 0.05)
1045 {N_A5_C0_H,0x01},
1046 {N_A5_C1_L,0x1c},
1047 {N_A5_C1_H,0x06},
1048 {N_A5_C2_L,0xf7},
1049 {N_A5_C2_H,0x06},
1050 {_END_OF_TBL_,0x00}, // NTSC M/N
1051 };
1052 MS_VIF_REG_TYPE VIF_NTSC_MN_A2[]=
1053 {
1054 {N_A1_C0_L,0xfc}, // Notch_A1, R = 0.94
1055 {N_A1_C0_H,0x02},
1056 {N_A1_C1_L,0x3c},
1057 {N_A1_C1_H,0x06},
1058 {N_A1_C2_L,0xd4},
1059 {N_A1_C2_H,0x04},
1060 {N_A2_C0_L,0xe8}, // Notch_A2, R = 0.94
1061 {N_A2_C0_H,0x02},
1062 {N_A2_C1_L,0x3c},
1063 {N_A2_C1_H,0x06},
1064 {N_A2_C2_L,0xe8},
1065 {N_A2_C2_H,0x04},
1066 {SOS12_C0_L,0xfc}, // SOS12, R = 0.94
1067 {SOS12_C0_H,0x02},
1068 {SOS12_C1_L,0x3c},
1069 {SOS12_C1_H,0x06},
1070 {SOS12_C2_L,0x00},
1071 {SOS12_C2_H,0x02},
1072 {SOS12_C3_L,0xd4},
1073 {SOS12_C3_H,0x04},
1074 {SOS12_C4_L,0x00},
1075 {SOS12_C4_H,0x02},
1076 {_END_OF_TBL_,0x00}, // NTSC M/N
1077 };
1078 MS_VIF_REG_TYPE VIF_PAL_DK_LOWER_ACI[]=
1079 {
1080 {SOS11_C0_L,0x3a}, // SOS11 notch at 16.5MHz (0.94)
1081 {SOS11_C0_H,0x05},
1082 {SOS11_C1_L,0x3c},
1083 {SOS11_C1_H,0x06},
1084 {SOS11_C2_L,0x00},
1085 {SOS11_C2_H,0x02},
1086 {SOS11_C3_L,0xf3},
1087 {SOS11_C3_H,0x02},
1088 {SOS11_C4_L,0x00},
1089 {SOS11_C4_H,0x02},
1090 {_END_OF_TBL_,0x00},
1091 };
1092 MS_VIF_REG_TYPE VIF_PAL_I_LOWER_ACI[]=
1093 {
1094 {SOS11_C0_L,0x0d}, // SOS11 notch at 17MHz (0.94)
1095 {SOS11_C0_H,0x05},
1096 {SOS11_C1_L,0x3c},
1097 {SOS11_C1_H,0x06},
1098 {SOS11_C2_L,0x00},
1099 {SOS11_C2_H,0x02},
1100 {SOS11_C3_L,0x23},
1101 {SOS11_C3_H,0x03},
1102 {SOS11_C4_L,0x00},
1103 {SOS11_C4_H,0x02},
1104 {_END_OF_TBL_,0x00},
1105 };
1106 MS_VIF_REG_TYPE VIF_PAL_GH_LOWER_ACI[]=
1107 {
1108 {SOS11_C0_L,0xe4}, // SOS11 notch at 17.5MHz (0.94)
1109 {SOS11_C0_H,0x04},
1110 {SOS11_C1_L,0x3c},
1111 {SOS11_C1_H,0x06},
1112 {SOS11_C2_L,0x00},
1113 {SOS11_C2_H,0x02},
1114 {SOS11_C3_L,0x4f},
1115 {SOS11_C3_H,0x03},
1116 {SOS11_C4_L,0x00},
1117 {SOS11_C4_H,0x02},
1118 {_END_OF_TBL_,0x00},
1119 };
1120 MS_VIF_REG_TYPE VIF_PAL_B_LOWER_ACI[]=
1121 {
1122 {SOS11_C0_L,0x1C}, // SOS11 notch at 16.5MHz (0.98)
1123 {SOS11_C0_H,0x05},
1124 {SOS11_C1_L,0x14},
1125 {SOS11_C1_H,0x06},
1126 {SOS11_C2_L,0x00},
1127 {SOS11_C2_H,0x02},
1128 {SOS11_C3_L,0xF3},
1129 {SOS11_C3_H,0x02},
1130 {SOS11_C4_L,0x00},
1131 {SOS11_C4_H,0x02},
1132 {_END_OF_TBL_,0x00},
1133 };
1134
1135 MS_VIF_REG_TYPE VIF_NTSC_MN_LOWER_ACI[]=
1136 {
1137 {SOS11_C0_L,0x15}, // SOS11 notch at 16.5MHz
1138 {SOS11_C0_H,0x05},
1139 {SOS11_C1_L,0x0A},
1140 {SOS11_C1_H,0x06},
1141 {SOS11_C2_L,0x00},
1142 {SOS11_C2_H,0x02},
1143 {SOS11_C3_L,0xF3},
1144 {SOS11_C3_H,0x02},
1145 {SOS11_C4_L,0x00},
1146 {SOS11_C4_H,0x02},
1147 {_END_OF_TBL_,0x00},
1148 };
1149 MS_VIF_REG_TYPE VIF_PAL_DK_Audio_SingleSAW[]=
1150 {
1151 {SOS12_C0_L,0x0D}, // SOS12 notch at 8.5MHz
1152 {SOS12_C0_H,0x01},
1153 {SOS12_C1_L,0xB8},
1154 {SOS12_C1_H,0x06},
1155 {SOS12_C2_L,0x00},
1156 {SOS12_C2_H,0x02},
1157 {SOS12_C3_L,0xB0},
1158 {SOS12_C3_H,0x06},
1159 {SOS12_C4_L,0x00},
1160 {SOS12_C4_H,0x02},
1161 {_END_OF_TBL_,0x00},
1162 };
1163 MS_VIF_REG_TYPE VIF_PAL_GH_Audio_SingleSAW[]=
1164 {
1165 {SOS12_C0_L,0x9A}, // SOS12 notch at 9.5MHz
1166 {SOS12_C0_H,0x00},
1167 {SOS12_C1_L,0xB8},
1168 {SOS12_C1_H,0x06},
1169 {SOS12_C2_L,0x00},
1170 {SOS12_C2_H,0x02},
1171 {SOS12_C3_L,0x40},
1172 {SOS12_C3_H,0x07},
1173 {SOS12_C4_L,0x00},
1174 {SOS12_C4_H,0x02},
1175 {_END_OF_TBL_,0x00},
1176 };
1177 MS_VIF_REG_TYPE VIF_PAL_I_Audio_SingleSAW[]=
1178 {
1179 {SOS12_C0_L,0xD4}, // SOS12 notch at 9MHz
1180 {SOS12_C0_H,0x00},
1181 {SOS12_C1_L,0xB8},
1182 {SOS12_C1_H,0x06},
1183 {SOS12_C2_L,0x00},
1184 {SOS12_C2_H,0x02},
1185 {SOS12_C3_L,0xF7},
1186 {SOS12_C3_H,0x06},
1187 {SOS12_C4_L,0x00},
1188 {SOS12_C4_H,0x02},
1189 {_END_OF_TBL_,0x00},
1190 };
1191
1192 MS_VIF_REG_TYPE VIF_NULL_LOWER_ACI[]=
1193 {
1194 {SOS11_C0_L,0x00}, // SOS11
1195 {SOS11_C0_H,0x00},
1196 {SOS11_C1_L,0x00},
1197 {SOS11_C1_H,0x00},
1198 {SOS11_C2_L,0x00},
1199 {SOS11_C2_H,0x00},
1200 {SOS11_C3_L,0x00},
1201 {SOS11_C3_H,0x00},
1202 {SOS11_C4_L,0x00},
1203 {SOS11_C4_H,0x02},
1204 {_END_OF_TBL_,0x00},
1205 };
1206
1207 MS_VIF_REG_TYPE VIF_CR_IIR_LPF1[]=
1208 {
1209 {CR_IIR_COEF_G,0x02},
1210 {CR_IIR_COEF_G+1,0x00},
1211 {CR_IIR_COEF_A1,0xfc},
1212 {CR_IIR_COEF_A1+1,0x01},
1213 {CR_IIR_COEF_A2,0x00},
1214 {CR_IIR_COEF_A2+1,0x00},
1215 {CR_IIR_COEF_B1,0x00},
1216 {CR_IIR_COEF_B1+1,0x02},
1217 {CR_IIR_COEF_B2,0x00},
1218 {CR_IIR_COEF_B2+1,0x00},
1219 {_END_OF_TBL_,0x00},
1220 };
1221 MS_VIF_REG_TYPE VIF_CR_IIR_LPF2[]=
1222 {
1223 {CR_IIR_COEF_G,0x02},
1224 {CR_IIR_COEF_G+1,0x00},
1225 {CR_IIR_COEF_A1,0xd6},
1226 {CR_IIR_COEF_A1+1,0x03},
1227 {CR_IIR_COEF_A2,0x27},
1228 {CR_IIR_COEF_A2+1,0x06},
1229 {CR_IIR_COEF_B1,0x5b},
1230 {CR_IIR_COEF_B1+1,0x06},
1231 {CR_IIR_COEF_B2,0x00},
1232 {CR_IIR_COEF_B2+1,0x02},
1233 {_END_OF_TBL_,0x00},
1234 };
1235
1236
1237 U16 VIF_PAL_EQ_CO_A_REJ[]=
1238 {
1239 0x0009,
1240 0x0003,
1241 0x000B,
1242 0x1FE1,
1243 0x002F,
1244 0x1FD0,
1245 0x001F,
1246 0x1FF2,
1247 0x001A,
1248 0x1FB4,
1249 0x008A,
1250 0x1F5E,
1251 0x0077,
1252 0x1FDC,
1253 0x1FFC,
1254 0x1FBB,
1255 0x00F1,
1256 0x1E79,
1257 0x0165,
1258 0x1FC9,
1259 0x1E4C,
1260 0x037C,
1261 0x0BCA,
1262 0x037C,
1263 0x1E4C,
1264 0x1FC9,
1265 0x0165,
1266 0x1E79,
1267 0x00F1,
1268 0x1FBB,
1269 0x1FFC,
1270 0x1FDC,
1271 0x0077,
1272 0x1F5E,
1273 0x008A,
1274 0x1FB4,
1275 0x001A,
1276 0x1FF2,
1277 0x001F,
1278 0x1FD0,
1279 0x002F,
1280 0x1FE1,
1281 0x000B,
1282 0x0003,
1283 0x0009,
1284 0x0000,
1285
1286 0x0000,
1287 0x0000,
1288 0x0000,
1289 0x0000,
1290 0x0000,
1291 0x0000,
1292 0x0000,
1293 0x0000,
1294 0x0000,
1295 0x0000
1296 };
1297
1298 U16 VIF_NTSC_EQ_CO_A_REJ[]=
1299 {
1300 0x001B,
1301 0x1FEB,
1302 0x0001,
1303 0x0000,
1304 0x0024,
1305 0x1FBF,
1306 0x0027,
1307 0x1FFE,
1308 0x0025,
1309 0x1F87,
1310 0x0083,
1311 0x1FD6,
1312 0x0009,
1313 0x1F78,
1314 0x0106,
1315 0x1F5A,
1316 0x1FD9,
1317 0x1FEF,
1318 0x017E,
1319 0x1DF8,
1320 0x1FB4,
1321 0x044E,
1322 0x09AF,
1323 0x044E,
1324 0x1FB4,
1325 0x1DF8,
1326 0x017E,
1327 0x1FEF,
1328 0x1FD9,
1329 0x1F5A,
1330 0x0106,
1331 0x1F78,
1332 0x0009,
1333 0x1FD6,
1334 0x0083,
1335 0x1F87,
1336 0x0025,
1337 0x1FFE,
1338 0x0027,
1339 0x1FBF,
1340 0x0024,
1341 0x0000,
1342 0x0001,
1343 0x1FEB,
1344 0x001B,
1345 0x0000,
1346
1347 0x0000,
1348 0x0000,
1349 0x0000,
1350 0x0000,
1351 0x0000,
1352 0x0000,
1353 0x0000,
1354 0x0000,
1355 0x0000,
1356 0x0000
1357 };
1358
1359 U16 VIF_BG_EQ_IIR_BANDSTOP[]=
1360 {
1361 0x070B,
1362 0x0C15,
1363 0x0BBB,
1364 0x064E,
1365 0x070B,
1366 0x0B1A,
1367 0x070B,
1368 0x09F9,
1369 0x05F9,
1370
1371 0x07AF,
1372 0x0BB0,
1373 0x0A66,
1374 0x0765,
1375 0x07AF,
1376 0x0C6B,
1377 0x07AF,
1378 0x0D1B,
1379 0x078D
1380 };
1381
1382 U16 VIF_BG_NICAM_EQ_IIR_NOTCH[]=
1383 {
1384 0x0764,
1385 0x0BCC,
1386 0x0AE6,
1387 0x06C8,
1388 0x0764,
1389 0x0C4A,
1390 0x0764,
1391 0x0C4A,
1392 0x06C8,
1393
1394 0x0764,
1395 0x0BCC,
1396 0x0AE6,
1397 0x06C8,
1398 0x0764,
1399 0x0C4A,
1400 0x0764,
1401 0x0C4A,
1402 0x06C8
1403 };
1404
1405 U16 VIF_I_EQ_IIR_NOTCH[]=
1406 {
1407 0x0764,
1408 0x0DDB,
1409 0x0CCD,
1410 0x06C8,
1411 0x0764,
1412 0x0E30,
1413 0x0764,
1414 0x0E30,
1415 0x06C8,
1416
1417 0x0764,
1418 0x0DDB,
1419 0x0CCD,
1420 0x06C8,
1421 0x0764,
1422 0x0E30,
1423 0x0764,
1424 0x0E30,
1425 0x06C8
1426 };
1427
1428 U16 VIF_DK1_EQ_IIR_NOTCH[]=
1429 {
1430 0x0764,
1431 0x0F41,
1432 0x0E18,
1433 0x06C8,
1434 0x0764,
1435 0x0D87,
1436 0x0764,
1437 0x0D87,
1438 0x06C8,
1439
1440 0x0764,
1441 0x0F41,
1442 0x0E18,
1443 0x06C8,
1444 0x0764,
1445 0x0D87,
1446 0x0764,
1447 0x0D87,
1448 0x06C8
1449 };
1450
1451 U16 VIF_DK2_EQ_IIR_NOTCH[]=
1452 {
1453 0x0764,
1454 0x0F41,
1455 0x0E18,
1456 0x06C8,
1457 0x0764,
1458 0x0E7F,
1459 0x0764,
1460 0x0E7F,
1461 0x06C8,
1462
1463 0x0764,
1464 0x0F41,
1465 0x0E18,
1466 0x06C8,
1467 0x0764,
1468 0x0E7F,
1469 0x0764,
1470 0x0E7F,
1471 0x06C8
1472 };
1473
1474 U16 VIF_DK3_EQ_IIR_NOTCH[]=
1475 {
1476 0x0764,
1477 0x0F41,
1478 0x0E18,
1479 0x06C8,
1480 0x0764,
1481 0x0BEB,
1482 0x0764,
1483 0x0BEB,
1484 0x06C8,
1485
1486 0x0764,
1487 0x0F41,
1488 0x0E18,
1489 0x06C8,
1490 0x0764,
1491 0x0BEB,
1492 0x0764,
1493 0x0BEB,
1494 0x06C8
1495 };
1496
1497 U16 VIF_DK_NICAM_EQ_IIR_NOTCH[]=
1498 {
1499 0x0764,
1500 0x0F41,
1501 0x0E18,
1502 0x06C8,
1503 0x0764,
1504 0x0C4A,
1505 0x0764,
1506 0x0C4A,
1507 0x06C8,
1508
1509 0x0764,
1510 0x0F41,
1511 0x0E18,
1512 0x06C8,
1513 0x0764,
1514 0x0C4A,
1515 0x0764,
1516 0x0C4A,
1517 0x06C8
1518 };
1519
1520 U16 VIF_NTSC_MN_EQ_IIR_NOTCH[]=
1521 {
1522 0x079E,
1523 0x0620,
1524 0x05D5,
1525 0x073C,
1526 0x079E,
1527 0x072F,
1528 0x079E,
1529 0x072F,
1530 0x073C,
1531
1532 0x079E,
1533 0x0620,
1534 0x05D5,
1535 0x073C,
1536 0x079E,
1537 0x072F,
1538 0x079E,
1539 0x072F,
1540 0x073C
1541 };
1542
1543
msWriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1544 void msWriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1545 {
1546 RIU_WriteByteMask(u32Reg, u8Val, u8Mask);
1547 msVifLoad();
1548 }
1549
msWriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1550 void msWriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1551 {
1552 RIU_WriteRegBit(u32Reg, bEnable, u8Mask);
1553 msVifLoad();
1554 }
1555
msWriteByte(U32 u32Reg,U8 u8Val)1556 void msWriteByte(U32 u32Reg, U8 u8Val )
1557 {
1558 RIU_WriteByte(u32Reg,u8Val);
1559 msVifLoad();
1560 }
1561
HAL_VIF_WriteByteMask(U32 u32Reg,U8 u8Val,U8 u8Mask)1562 void HAL_VIF_WriteByteMask(U32 u32Reg, U8 u8Val, U8 u8Mask)
1563 {
1564 msWriteByteMask(u32Reg, u8Val, u8Mask);
1565 }
1566
HAL_VIF_WriteBit(U32 u32Reg,BOOL bEnable,U8 u8Mask)1567 void HAL_VIF_WriteBit(U32 u32Reg, BOOL bEnable, U8 u8Mask)
1568 {
1569 msWriteBit(u32Reg, bEnable, u8Mask);
1570 }
1571
HAL_VIF_WriteByte(U32 u32Reg,U8 u8Val)1572 void HAL_VIF_WriteByte(U32 u32Reg, U8 u8Val )
1573 {
1574 msWriteByte(u32Reg, u8Val);
1575 }
1576
HAL_VIF_ReadByte(U32 u32Reg)1577 U8 HAL_VIF_ReadByte(U32 u32Reg )
1578 {
1579 return msReadByte(u32Reg);
1580 }
1581
msWriteRegsTbl(MS_VIF_REG_TYPE * pRegTable)1582 void msWriteRegsTbl(MS_VIF_REG_TYPE *pRegTable)
1583 {
1584 U16 u16Dummy;
1585 U32 u32Address;
1586 U8 u8Value;
1587
1588 u16Dummy = 2000;
1589
1590 do
1591 {
1592 u32Address = pRegTable->u32Address;
1593 u8Value = pRegTable->u8Value;
1594 if (u32Address == 0xFFFF) // check end of table
1595 break;
1596 RIU_WriteByte(u32Address, u8Value);
1597 pRegTable++;
1598 } while (--u16Dummy > 0);
1599 msVifLoad();
1600 }
1601
HAL_VIF_RegInit(void)1602 void HAL_VIF_RegInit (void)
1603 {
1604 MS_PHY phyNonPMBankSize, phyPMBankSize;
1605 MS_VIRT virtNonPMBank, virtPMBank;
1606
1607 HALVIFDBG(printf("\r\nHAL_VIF_RegInit()"));
1608 if (!MDrv_MMIO_GetBASE( &virtNonPMBank, &phyNonPMBankSize, MS_MODULE_VIF))
1609 {
1610 printf("\r\nIOMap failure to get MAP_NONPM_BANK");
1611 virtNonPMBank = BASEADDR_RIU; // TODO what to do if failed??
1612 }
1613 else
1614 {
1615 HALVIFDBG(printf("\r\nMS_MODULE_VIF base = 0x%lX, length = %lu", virtNonPMBank, phyNonPMBankSize));
1616 }
1617
1618 _hal_VIF.virtVIFBaseAddr = virtNonPMBank;
1619 _hal_VIF.bBaseAddrInitialized = 1;
1620
1621 if (!MDrv_MMIO_GetBASE( &virtPMBank, &phyPMBankSize, MS_MODULE_PM))
1622 {
1623 printf("\r\nIOMap failure to get MAP_PM_BANK");
1624 virtPMBank = (VIRT)BASEADDR_RIU; // TODO what to do if failed??
1625 }
1626 else
1627 {
1628 HALVIFDBG(printf("\r\nMS_MODULE_PM base = 0x%lX, length = %lu", virtPMBank, phyPMBankSize));
1629 }
1630 }
1631
1632
HAL_VIF_SetClock(BOOL bEnable)1633 void HAL_VIF_SetClock(BOOL bEnable)
1634 {
1635 HALVIFDBG(printf("\r\nHAL_VIF_SetClock=%d",bEnable));
1636
1637 //bEnable = (bEnable) ? 0:1; // 0 means enable
1638 }
1639
msVifAdcInitial(void)1640 void msVifAdcInitial(void)
1641 {
1642 HALVIFDBG(printf("\r\nmsVifAdcInitial()"));
1643
1644 if (!_hal_VIF.bBaseAddrInitialized) return ;
1645
1646 RIU_WriteByteMask(0x1E39L, 0x00, 0x03); // DMDTOP/DMDANA_controlled by HK_MCU (0) or DMD_MCU (1)
1647
1648 // enable vif DAC clock
1649 // enable atsc_adcd_sync clock
1650 RIU_WriteByte(0x331AL, 0x04);
1651 RIU_WriteByte(0x331BL, 0x00);
1652
1653 // enable vif clock
1654 RIU_WriteByte(0x11F1CL, 0x00);
1655 RIU_WriteByte(0x11F1DL, 0x00);
1656
1657 // SRAM share clock
1658 RIU_WriteByte(0x11FE2L, 0x01); // ckg_dvbtm_sram_t14x_t24x_srd1x
1659 RIU_WriteByte(0x11FE3L, 0x10);
1660 RIU_WriteByte(0x11F78L, 0x00); // ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1661 RIU_WriteByte(0x11F79L, 0x00);
1662
1663 // ACIFIR clock
1664 RIU_WriteByte(0x11F24L, 0x01);
1665 RIU_WriteByte(0x11F25L, 0x08);
1666
1667 RIU_WriteByte(0x11F2AL, 0x00); // DAGC1/2 SRAM MUX
1668 RIU_WriteByte(0x11F2BL, 0x00);
1669
1670 RIU_WriteByte(0x52990L, 0x00); // ckg_dvbtm_sram_t14x_t24x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1671 RIU_WriteByte(0x52991L, 0x01); // ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1672
1673 RIU_WriteByte(0x127C0L, 0x00); // mulan_dvbt2_sram_share_en
1674 RIU_WriteByte(0x127C1L, 0x00);
1675 RIU_WriteByte(0x127C2L, 0x00);
1676 RIU_WriteByte(0x127C3L, 0x00);
1677 RIU_WriteByte(0x127C4L, 0x00);
1678 RIU_WriteByte(0x127C5L, 0x00);
1679 RIU_WriteByte(0x127C6L, 0x00);
1680 RIU_WriteByte(0x127C7L, 0x00);
1681 RIU_WriteByte(0x127C8L, 0x00);
1682 RIU_WriteByte(0x127C9L, 0x00);
1683
1684 // SRAM Power Control
1685 RIU_WriteByte(0x12090L, 0xB8);
1686 RIU_WriteByte(0x12091L, 0xBB);
1687 RIU_WriteByte(0x127E0L, 0x70); // SRAM_PWR_CTRL_SEL
1688 RIU_WriteByte(0x127E1L, 0x00);
1689 RIU_WriteByte(0x127E2L, 0x00);
1690 RIU_WriteByte(0x127E3L, 0x00);
1691 RIU_WriteByte(0x127E4L, 0x00);
1692 RIU_WriteByte(0x127E5L, 0x00);
1693 RIU_WriteByte(0x127E6L, 0x00);
1694 RIU_WriteByte(0x127E7L, 0x00);
1695 RIU_WriteByte(0x127E8L, 0x00);
1696 RIU_WriteByte(0x127E9L, 0x00);
1697
1698 // Enable VIF, DVBT, ATSC and VIF reset
1699 RIU_WriteByte(0x12002L, 0x74);
1700 RIU_WriteByte(0x12003L, 0x00);
1701 RIU_WriteByte(0x12002L, 0x14); // Enable VIF
1702 RIU_WriteByte(0x12003L, 0x00);
1703 RIU_WriteByte(0x12004L, 0x22);
1704 RIU_WriteByte(0x12005L, 0x00);
1705
1706 // DMD_ANA_ADC_SYNC CLK_W
1707 // [0] : disable clock = 1'b1
1708 // [1] : invert clock
1709 RIU_WriteByte(0x128D0L, 0x01);
1710
1711 // Disable ADC sign bit
1712 RIU_WriteByte(0x12060L, 0x04);
1713 RIU_WriteByte(0x12061L, 0x00);
1714
1715 // ADC I channel offset
1716 // Change unsin into sin
1717 // [11:0] reg_adc_offset_i
1718 RIU_WriteByte(0x12064L, 0x00);
1719 RIU_WriteByte(0x12065L, 0x00);
1720
1721 // ADC Q channel offset
1722 // Change unsin into sin
1723 // [11:0] reg_adc_offset_q
1724 RIU_WriteByte(0x12066L, 0x00);
1725 RIU_WriteByte(0x12067L, 0x00);
1726
1727 // VIF use DVB SRAM and FIR
1728 RIU_WriteByte(0x120A0L, 0x01);
1729
1730 // Enable LDOS
1731 RIU_WriteByte(0x128AEL, 0x00);
1732 RIU_WriteByte(0x128AFL, 0x00);
1733 RIU_WriteByte(0x128B0L, 0x00);
1734 RIU_WriteByte(0x128B1L, 0x00);
1735 RIU_WriteByte(0x128B2L, 0x11); // ana_setting_sel
1736 RIU_WriteByte(0x128B3L, 0x00);
1737
1738 // PLL power up
1739 RIU_WriteByte(0x1286AL, 0x03);
1740 RIU_WriteByte(0x1286BL, 0x00);
1741
1742 // VIF : 24*36/6 = 144 MHz
1743 // VIF : 24*36/18 = 48 MHz
1744 // Set MPLL_LOOP_DIV_FIRST and SECOND
1745 RIU_WriteByte(0x12866L, 0x01); // loop divider
1746 RIU_WriteByte(0x12867L, 0x12);
1747
1748 // Set MPLL_ADC_DIV_SE
1749 if(VIF_IS_ADC_48MHz == 0)
1750 {
1751 // 144MHz case
1752 RIU_WriteByte(0x12860L, 0x00); // DMPLL post divider
1753 RIU_WriteByte(0x12861L, 0x06);
1754 }
1755 else
1756 {
1757 // 48MHz case
1758 RIU_WriteByte(0x12860L, 0x00); // DMPLL post divider
1759 RIU_WriteByte(0x12861L, 0x12);
1760 }
1761
1762 // MPLL_output_div_second
1763 RIU_WriteByte(0x12864L, 0x00);
1764 RIU_WriteByte(0x12865L, 0x00);
1765
1766 // SIF CLK select
1767 RIU_WriteByte(0x1287EL, 0x00);
1768 RIU_WriteByte(0x1287FL, 0x00);
1769
1770 RIU_WriteRegBit(0x12834L, 1, _BIT4); // EN_VCO_DIG
1771
1772 // Set IMUXS QMUXS
1773 RIU_WriteByte(0x12802L, 0x40); // VIF path, Bypass PGA
1774 RIU_WriteByte(0x12803L, 0x04); // Mux selection
1775
1776 // Set enable ADC clock
1777 RIU_WriteByte(0x12818L, 0x02); // ADC_Q power down
1778 RIU_WriteByte(0x12819L, 0x00);
1779
1780 RIU_WriteByte(0x12840L, 0x00); // Ref Enable
1781 RIU_WriteByte(0x12841L, 0x00);
1782
1783 // Set ADC gain is 1
1784 RIU_WriteByte(0x12816L, 0x05);
1785 RIU_WriteByte(0x12817L, 0x05);
1786
1787 // Calibration buffer
1788 RIU_WriteByte(0x1281EL, 0x80);
1789 RIU_WriteByte(0x1281FL, 0x00);
1790
1791 // AGC control
1792 RIU_WriteByte(0x12830L, 0x01); // AGC enable
1793 RIU_WriteByte(0x12831L, 0x00);
1794
1795 if(VIFInitialIn_inst.VifSawArch == NO_SAW_DIF)
1796 VIFInitialIn_inst.VifSawArch = NO_SAW;
1797
1798 HAL_VIF_Delay1ms(1);
1799
1800 // RFAGC and IFAGC control (ADC)
1801 RIU_WriteByteMask(RFAGC_DATA_SEL, 0, 0x0C); // RFAGC
1802 RIU_WriteByteMask(IFAGC_DATA_SEL, 0, 0xC0); // IFAGC
1803 RIU_WriteRegBit(RFAGC_ODMODE, 0, _BIT1);
1804 RIU_WriteRegBit(IFAGC_ODMODE, 0, _BIT5);
1805
1806 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
1807 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0); // RFAGC disable
1808 else
1809 RIU_WriteRegBit(RFAGC_ENABLE, 1, _BIT0); // RFAGC enable
1810 RIU_WriteRegBit(IFAGC_ENABLE, 1, _BIT4); // IFAGC enable
1811
1812 // RFAGC and IFAGC control (RF)
1813 msWriteBit(RFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1814 msWriteBit(RFAGC_DITHER_EN, 1, _BIT7); // dither disable
1815 msWriteBit(RFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1816 msWriteBit(OREN_RFAGC, 0, _BIT5); // RFAGC 0: BB control; 1: I2C control
1817
1818 msWriteBit(IFAGC_SEL_SECONDER, 1, _BIT6); // 0: 1st order; 1: 2nd order
1819 msWriteBit(IFAGC_DITHER_EN, 1, _BIT7); // dither disable
1820 msWriteBit(IFAGC_POLARITY, 1, _BIT4); // RFAGC polarity 0: negative logic
1821 msWriteBit(OREN_IFAGC, 0, _BIT6); // RFAGC 0: BB control; 1: I2C control
1822
1823 msWriteBit(OREN_PGA1_V, 0, _BIT3); // Video PGA1 0: BB control; 1: I2C control
1824 msWriteBit(OREN_PGA2_V, 0, _BIT2); // Video PGA2 0: BB control; 1: I2C control
1825 msWriteBit(OREN_PGA1_S, 0, _BIT1); // Audio PGA1 0: BB control; 1: I2C control
1826 msWriteBit(OREN_PGA2_S, 0, _BIT0); // Audio PGA2 0: BB control; 1: I2C control
1827
1828 // ADC_SYNC CLK_R
1829 RIU_WriteByte(0x11F0AL, 0x00);
1830 RIU_WriteByte(0x11F0BL, 0x00);
1831
1832 // ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1833 // enable dvbc adc clock
1834 RIU_WriteByte(0x3314L, 0x04);
1835 RIU_WriteByte(0x3315L, 0x00);
1836
1837 // DMD_ANA_ADC_SYNC CLK_W
1838 RIU_WriteByte(0x128D0L, 0x00);
1839
1840 // EQ BYPASS
1841 msWriteBit(BYPASS_EQFIR, 1, _BIT0);
1842 }
1843
1844 // For API
msVifSetIfFreq(IfFrequencyType ucIfFreq)1845 void msVifSetIfFreq(IfFrequencyType ucIfFreq)
1846 {
1847 HALVIFDBG(printf("\r\nmsVifSetIfFreq() ucIfFreq=%d",ucIfFreq));
1848
1849 if (!_hal_VIF.bBaseAddrInitialized) return ;
1850
1851 //g_FreqType = ucIfFreq; // 0x1121_D2
1852 msWriteByte(VIF_RF_RESERVED_1, ucIfFreq);
1853
1854 // VifShiftClk : 0x1121_D3
1855 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
1856
1857 // cvbs output
1858 msWriteBit(VIFDAC_ENABLE, 1, _BIT3); // enable vifdac
1859
1860 // for China descrambler box
1861 if (VIFInitialIn_inst.ChinaDescramblerBox == 0)
1862 {
1863 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1864 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1865 }
1866 else
1867 {
1868 msWriteByteMask(VIFDAC_OUT_SEL, 0x04, 0x07); // 0: cvbs output; 4: debug bus
1869 msWriteBit(DEBUG2_EN, 1, _BIT7); // select debug2 data
1870 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1871
1872 if(VIFInitialIn_inst.ChinaDescramblerBox == 1)
1873 {
1874 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1875 msWriteByte(DEBUG_PORT, 0x84); // selsect CVBS output after Notch_A2 filter
1876 }
1877 else if(VIFInitialIn_inst.ChinaDescramblerBox == 2)
1878 {
1879 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1880 msWriteByte(DEBUG_PORT, 0x98); // select CVBS output after IMAGE_IIR
1881 }
1882 else if (VIFInitialIn_inst.ChinaDescramblerBox == 3)
1883 {
1884 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1885 msWriteByte(DEBUG_PORT, 0x8A); // select CVBS output after IMAGE_REJ1
1886 }
1887 else if (VIFInitialIn_inst.ChinaDescramblerBox == 4)
1888 {
1889 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1890 msWriteByte(DEBUG_PORT, 0x88); // select CVBS output after ACI_REJ
1891 }
1892 else if (VIFInitialIn_inst.ChinaDescramblerBox == 5)
1893 {
1894 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1895 msWriteByte(DEBUG_PORT, 0x86); // select CVBS output after MIXER_OUT_I
1896 }
1897 else if (VIFInitialIn_inst.ChinaDescramblerBox == 6)
1898 {
1899 msWriteBit(N_A1_IN_SEL, 0, _BIT4); // 0:from dvga, 1:from image_rej_iir
1900 msWriteByte(DEBUG_PORT, 0x8B); // select CVBS output after IMAGE_REJ2
1901 }
1902 else
1903 {
1904 msWriteByteMask(VIFDAC_OUT_SEL, 0x00, 0x07); // 0: cvbs output; 4: debug bus
1905 msWriteBit(DEBUG2_EN, 0, _BIT7); // select debug2 data
1906 msWriteByteMask(DEBUG_MODULE, 0x00, 0x0F); // select filter debug bus
1907 msWriteBit(N_A1_IN_SEL, 1, _BIT4); // 0:from dvga, 1:from image_rej_iir
1908 }
1909 }
1910
1911 if (VIFInitialIn_inst.VifTunerType == 1)
1912 {
1913 // silicon tuner
1914 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1915 msWriteByte(IF_RATE+1, 0x00);
1916 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1917 }
1918 else if (VIFInitialIn_inst.VifTunerType == 2)
1919 {
1920 // FM tuner
1921 if(VIFInitialIn_inst.VifSawArch == SILICON_TUNER)
1922 {
1923 // silicon tuner
1924 msWriteByte(IF_RATE, 0x00); // IF rate for 0 MHz
1925 msWriteByte(IF_RATE+1, 0x00);
1926 msWriteByteMask(IF_RATE+2, 0x00, 0x3F);
1927 }
1928 }
1929 else
1930 {
1931 switch(ucIfFreq)
1932 {
1933 case IF_FREQ_3395:
1934 msWriteByte(IF_RATE, 0x44); // IF rate for -48.9 MHz // HEX [ (IF/144) * 2^22]
1935 msWriteByte(IF_RATE+1, 0x44);
1936 msWriteByteMask(IF_RATE+2, 0x2A, 0x3F);
1937 break;
1938 case IF_FREQ_3800:
1939 if (VifShiftClk/*g_VifShiftClk*/ == 1)
1940 {
1941 msWriteByte(0x12866L, 0x00);//loop divider
1942 msWriteByte(0x12867L, 0x23);
1943
1944 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
1945 msWriteByte(IF_RATE+1, 0x83);
1946 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1947 }
1948 else if(VifShiftClk/*g_VifShiftClk*/ == 2)
1949 {
1950 msWriteByte(0x12866L, 0x00);//loop divider
1951 msWriteByte(0x12867L, 0x25);
1952
1953 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
1954 msWriteByte(IF_RATE+1, 0xF2);
1955 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
1956 }
1957 else
1958 {
1959 msWriteByte(0x12866L, 0x00);//loop divider
1960 msWriteByte(0x12867L, 0x24);
1961
1962 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
1963 msWriteByte(IF_RATE+1, 0x38);
1964 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1965 }
1966 break;
1967 case IF_FREQ_3890:
1968 msWriteByte(IF_RATE, 0x49); // IF rate for 23.9 MHz
1969 msWriteByte(IF_RATE+1, 0x9F);
1970 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1971 break;
1972 case IF_FREQ_3950:
1973 msWriteByte(IF_RATE, 0x8E); // IF rate for 24.5 MHz
1974 msWriteByte(IF_RATE+1, 0xE3);
1975 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
1976 break;
1977 case IF_FREQ_4575:
1978 msWriteByte(IF_RATE, 0xAA); // IF rate for 30.75 MHz
1979 msWriteByte(IF_RATE+1, 0xAA);
1980 msWriteByteMask(IF_RATE+2, 0x0D, 0x3F);
1981 break;
1982 case IF_FREQ_5875:
1983 msWriteByte(IF_RATE, 0xC7); // IF rate for 43.75 MHz
1984 msWriteByte(IF_RATE+1, 0x71);
1985 msWriteByteMask(IF_RATE+2, 0x13, 0x3F);
1986 break;
1987 default:
1988 break;
1989 }
1990 }
1991 }
1992
msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem,FrequencyBand frequencyRange)1993 void msVifGroupDelayFilter(VIFSoundSystem ucSoundSystem, FrequencyBand frequencyRange)
1994 {
1995 BYTE VifPeakingFilter=0, VifYcDelayFilter=0, VifGroupDelayFilter=0;
1996
1997 if (!_hal_VIF.bBaseAddrInitialized) return ;
1998
1999 switch (ucSoundSystem)
2000 {
2001 case VIF_SOUND_B:
2002 case VIF_SOUND_B_NICAM:
2003 if (frequencyRange==FREQ_VHF_L)
2004 {
2005 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_L;
2006 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_L;
2007 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_L;
2008 }
2009 else if (frequencyRange==FREQ_VHF_H)
2010 {
2011 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_VHF_H;
2012 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_VHF_H;
2013 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_VHF_H;
2014 }
2015 else if (frequencyRange==FREQ_UHF)
2016 {
2017 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterB_UHF;
2018 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterB_UHF;
2019 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterB_UHF;
2020 }
2021 else
2022 printf("\r\n ERROR msVifGroupDelayFilter B frequencyRange=%d", frequencyRange);
2023 break;
2024
2025 case VIF_SOUND_GH:
2026 case VIF_SOUND_GH_NICAM:
2027 if (frequencyRange==FREQ_VHF_L)
2028 {
2029 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_L;
2030 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_L;
2031 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_L;
2032 }
2033 else if (frequencyRange==FREQ_VHF_H)
2034 {
2035 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_VHF_H;
2036 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_VHF_H;
2037 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_VHF_H;
2038 }
2039 else if (frequencyRange==FREQ_UHF)
2040 {
2041 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterGH_UHF;
2042 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterGH_UHF;
2043 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterGH_UHF;
2044 }
2045 else
2046 printf("\r\n ERROR msVifGroupDelayFilter GH frequencyRange=%d", frequencyRange);
2047 break;
2048
2049 case VIF_SOUND_I:
2050 if (frequencyRange==FREQ_VHF_L)
2051 {
2052 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_L;
2053 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_L;
2054 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_L;
2055 }
2056 else if (frequencyRange==FREQ_VHF_H)
2057 {
2058 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_VHF_H;
2059 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_VHF_H;
2060 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_VHF_H;
2061 }
2062 else if (frequencyRange==FREQ_UHF)
2063 {
2064 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterI_UHF;
2065 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterI_UHF;
2066 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterI_UHF;
2067 }
2068 else
2069 printf("\r\n ERROR msVifGroupDelayFilter I frequencyRange=%d", frequencyRange);
2070 break;
2071
2072 case VIF_SOUND_DK1:
2073 case VIF_SOUND_DK2:
2074 case VIF_SOUND_DK3:
2075 case VIF_SOUND_DK_NICAM:
2076 if (frequencyRange==FREQ_VHF_L)
2077 {
2078 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_L;
2079 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_L;
2080 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_L;
2081 }
2082 else if (frequencyRange==FREQ_VHF_H)
2083 {
2084 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_VHF_H;
2085 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_VHF_H;
2086 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_VHF_H;
2087 }
2088 else if (frequencyRange==FREQ_UHF)
2089 {
2090 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterDK_UHF;
2091 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterDK_UHF;
2092 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterDK_UHF;
2093 }
2094 else
2095 printf("\r\n ERROR msVifGroupDelayFilter DK frequencyRange=%d", frequencyRange);
2096 break;
2097
2098 case VIF_SOUND_L:
2099 if (frequencyRange==FREQ_VHF_L)
2100 {
2101 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_L;
2102 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_L;
2103 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_L;
2104 }
2105 else if (frequencyRange==FREQ_VHF_H)
2106 {
2107 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_VHF_H;
2108 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_VHF_H;
2109 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_VHF_H;
2110 }
2111 else if (frequencyRange==FREQ_UHF)
2112 {
2113 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterL_UHF;
2114 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterL_UHF;
2115 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterL_UHF;
2116 }
2117 else
2118 printf("\r\n ERROR msVifGroupDelayFilter L frequencyRange=%d", frequencyRange);
2119 break;
2120
2121 case VIF_SOUND_LL:
2122 if (frequencyRange==FREQ_VHF_L)
2123 {
2124 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_L;
2125 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_L;
2126 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_L;
2127 }
2128 else if (frequencyRange==FREQ_VHF_H)
2129 {
2130 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_VHF_H;
2131 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_VHF_H;
2132 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_VHF_H;
2133 }
2134 else if (frequencyRange==FREQ_UHF)
2135 {
2136 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterLL_UHF;
2137 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterLL_UHF;
2138 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterLL_UHF;
2139 }
2140 else
2141 printf("\r\n ERROR msVifGroupDelayFilter LL frequencyRange=%d", frequencyRange);
2142 break;
2143
2144 case VIF_SOUND_MN:
2145 if (frequencyRange==FREQ_VHF_L)
2146 {
2147 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_L;
2148 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_L;
2149 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_L;
2150 }
2151 else if (frequencyRange==FREQ_VHF_H)
2152 {
2153 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_VHF_H;
2154 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_VHF_H;
2155 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_VHF_H;
2156 }
2157 else if (frequencyRange==FREQ_UHF)
2158 {
2159 VifPeakingFilter = VIFInitialIn_inst.VifPeakingFilterMN_UHF;
2160 VifYcDelayFilter = VIFInitialIn_inst.VifYcDelayFilterMN_UHF;
2161 VifGroupDelayFilter =VIFInitialIn_inst.VifGroupDelayFilterMN_UHF;
2162 }
2163 else
2164 printf("\r\n ERROR msVifGroupDelayFilter MN frequencyRange=%d", frequencyRange);
2165 break;
2166
2167 default:
2168 printf("\r\n Error msVifGroupDelayFilter ucSoundSystem=%d",ucSoundSystem);
2169 break;
2170 }
2171
2172 HALVIFDBG(printf("\r\nmsVifGroupDelayFilter() VifPeakingFilter=%d",VifPeakingFilter));
2173 HALVIFDBG(printf(" VifYcDelayFilter=%d VifGroupDelayFilter=%d",VifYcDelayFilter, VifGroupDelayFilter));
2174
2175 if (VifPeakingFilter == 0x00)
2176 {
2177 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_NULL);
2178 }
2179 else if (VifPeakingFilter == 0x01)
2180 {
2181 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_1dB);
2182 }
2183 else if (VifPeakingFilter == 0x02)
2184 {
2185 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_2dB);
2186 }
2187 else if (VifPeakingFilter == 0x03)
2188 {
2189 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB);
2190 }
2191 else if (VifPeakingFilter == 0x04)
2192 {
2193 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB);
2194 }
2195 else if (VifPeakingFilter == 0x05)
2196 {
2197 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_3dB_VSB);
2198 }
2199 else if (VifPeakingFilter == 0x06)
2200 {
2201 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_4dB_VSB);
2202 }
2203 else if (VifPeakingFilter == 0x07)
2204 {
2205 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_PEAKING_5dB_VSB);
2206 }
2207 else if (VifPeakingFilter == 0x80)
2208 {
2209 msWriteByte(SOS21_C0_L, VIFInitialIn_inst.VifSos21FilterC0); // SOS21 (user define)
2210 msWriteByteMask(SOS21_C0_H, VIFInitialIn_inst.VifSos21FilterC0>>8, 0x07);
2211 msWriteByte(SOS21_C1_L, VIFInitialIn_inst.VifSos21FilterC1);
2212 msWriteByteMask(SOS21_C1_H, VIFInitialIn_inst.VifSos21FilterC1>>8, 0x07);
2213 msWriteByte(SOS21_C2_L, VIFInitialIn_inst.VifSos21FilterC2);
2214 msWriteByteMask(SOS21_C2_H, VIFInitialIn_inst.VifSos21FilterC2>>8, 0x07);
2215 msWriteByte(SOS21_C3_L, VIFInitialIn_inst.VifSos21FilterC3);
2216 msWriteByteMask(SOS21_C3_H, VIFInitialIn_inst.VifSos21FilterC3>>8, 0x07);
2217 msWriteByte(SOS21_C4_L, VIFInitialIn_inst.VifSos21FilterC4);
2218 msWriteByteMask(SOS21_C4_H, VIFInitialIn_inst.VifSos21FilterC4>>8, 0x07);
2219 }
2220
2221 if (VifYcDelayFilter == 0x00)
2222 {
2223 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_NULL);
2224 }
2225 else if (VifYcDelayFilter == 0x01)
2226 {
2227 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_YCDelay_VSB);
2228 }
2229 else if (VifYcDelayFilter == 0x80)
2230 {
2231 msWriteByte(SOS22_C0_L, VIFInitialIn_inst.VifSos22FilterC0); // SOS22 (user define)
2232 msWriteByteMask(SOS22_C0_H, VIFInitialIn_inst.VifSos22FilterC0>>8, 0x07);
2233 msWriteByte(SOS22_C1_L, VIFInitialIn_inst.VifSos22FilterC1);
2234 msWriteByteMask(SOS22_C1_H, VIFInitialIn_inst.VifSos22FilterC1>>8, 0x07);
2235 msWriteByte(SOS22_C2_L, VIFInitialIn_inst.VifSos22FilterC2);
2236 msWriteByteMask(SOS22_C2_H, VIFInitialIn_inst.VifSos22FilterC2>>8, 0x07);
2237 msWriteByte(SOS22_C3_L, VIFInitialIn_inst.VifSos22FilterC3);
2238 msWriteByteMask(SOS22_C3_H, VIFInitialIn_inst.VifSos22FilterC3>>8, 0x07);
2239 msWriteByte(SOS22_C4_L, VIFInitialIn_inst.VifSos22FilterC4);
2240 msWriteByteMask(SOS22_C4_H, VIFInitialIn_inst.VifSos22FilterC4>>8, 0x07);
2241 }
2242
2243 if (VifGroupDelayFilter == 0x00)
2244 {
2245 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_NULL);
2246 }
2247 else if (VifGroupDelayFilter == 0x01)
2248 {
2249 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_LG);
2250 }
2251 else if (VifGroupDelayFilter == 0x02)
2252 {
2253 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_VSB_Philips);
2254 }
2255 else if (VifGroupDelayFilter == 0x03)
2256 {
2257 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_R);
2258 }
2259 else if (VifGroupDelayFilter == 0x04)
2260 {
2261 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_Low_L);
2262 }
2263 else if (VifGroupDelayFilter == 0x05)
2264 {
2265 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_R);
2266 }
2267 else if (VifGroupDelayFilter == 0x06)
2268 {
2269 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_GroupDelay_High_L);
2270 }
2271 else if (VifGroupDelayFilter == 0x80)
2272 {
2273 msWriteByte(SOS31_C0_L, VIFInitialIn_inst.VifSos31FilterC0); // SOS31 (user define)
2274 msWriteByteMask(SOS31_C0_H, VIFInitialIn_inst.VifSos31FilterC0>>8, 0x07);
2275 msWriteByte(SOS31_C1_L, VIFInitialIn_inst.VifSos31FilterC1);
2276 msWriteByteMask(SOS31_C1_H, VIFInitialIn_inst.VifSos31FilterC1>>8, 0x07);
2277 msWriteByte(SOS31_C2_L, VIFInitialIn_inst.VifSos31FilterC2);
2278 msWriteByteMask(SOS31_C2_H, VIFInitialIn_inst.VifSos31FilterC2>>8, 0x07);
2279 msWriteByte(SOS31_C3_L, VIFInitialIn_inst.VifSos31FilterC3);
2280 msWriteByteMask(SOS31_C3_H, VIFInitialIn_inst.VifSos31FilterC3>>8, 0x07);
2281 msWriteByte(SOS31_C4_L, VIFInitialIn_inst.VifSos31FilterC4);
2282 msWriteByteMask(SOS31_C4_H, VIFInitialIn_inst.VifSos31FilterC4>>8, 0x07);
2283 msWriteByte(SOS32_C0_L, VIFInitialIn_inst.VifSos32FilterC0); // SOS32 (user define)
2284 msWriteByteMask(SOS32_C0_H, VIFInitialIn_inst.VifSos32FilterC0>>8, 0x07);
2285 msWriteByte(SOS32_C1_L, VIFInitialIn_inst.VifSos32FilterC1);
2286 msWriteByteMask(SOS32_C1_H, VIFInitialIn_inst.VifSos32FilterC1>>8, 0x07);
2287 msWriteByte(SOS32_C2_L, VIFInitialIn_inst.VifSos32FilterC2);
2288 msWriteByteMask(SOS32_C2_H, VIFInitialIn_inst.VifSos32FilterC2>>8, 0x07);
2289 msWriteByte(SOS32_C3_L, VIFInitialIn_inst.VifSos32FilterC3);
2290 msWriteByteMask(SOS32_C3_H, VIFInitialIn_inst.VifSos32FilterC3>>8, 0x07);
2291 msWriteByte(SOS32_C4_L, VIFInitialIn_inst.VifSos32FilterC4);
2292 msWriteByteMask(SOS32_C4_H, VIFInitialIn_inst.VifSos32FilterC4>>8, 0x07);
2293 /*
2294 msWriteByte(SOS33_C0_L, sVIFSOS33.Vif_SOS_33_C0); // SOS33 (user define)
2295 msWriteByteMask(SOS33_C0_H, sVIFSOS33.Vif_SOS_33_C0>>8, 0x07);
2296 msWriteByte(SOS33_C1_L, sVIFSOS33.Vif_SOS_33_C1);
2297 msWriteByteMask(SOS33_C1_H, sVIFSOS33.Vif_SOS_33_C1>>8, 0x07);
2298 msWriteByte(SOS33_C2_L, sVIFSOS33.Vif_SOS_33_C2);
2299 msWriteByteMask(SOS33_C2_H, sVIFSOS33.Vif_SOS_33_C2>>8, 0x07);
2300 msWriteByte(SOS33_C3_L, sVIFSOS33.Vif_SOS_33_C3);
2301 msWriteByteMask(SOS33_C3_H, sVIFSOS33.Vif_SOS_33_C3>>8, 0x07);
2302 msWriteByte(SOS33_C4_L, sVIFSOS33.Vif_SOS_33_C4);
2303 msWriteByteMask(SOS33_C4_H, sVIFSOS33.Vif_SOS_33_C4>>8, 0x07);
2304 */
2305 }
2306 msWriteBit(BYPASS_SOS33, 1, _BIT6);
2307 }
2308
2309 // For API
msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)2310 void msVifSetSoundSystem(VIFSoundSystem ucSoundSystem)
2311 {
2312 HALVIFDBG(printf("\r\nmsVifSetSoundSystem() ucSoundSystem=%d",ucSoundSystem));
2313
2314 if (!_hal_VIF.bBaseAddrInitialized) return ;
2315
2316 DWORD VifCrRateTemp;
2317
2318 // VifShiftClk : 0x1121_D3
2319 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
2320
2321 g_ucVifSoundSystemType = ucSoundSystem;
2322
2323 if((ucSoundSystem == VIF_SOUND_L)||(ucSoundSystem == VIF_SOUND_LL))
2324 msVifInitial();
2325
2326 switch(ucSoundSystem)
2327 {
2328 case VIF_SOUND_B:
2329 if (VIFInitialIn_inst.VifTunerType == 1)
2330 {
2331 // silicon tuner
2332 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2333 {
2334 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2335 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2336 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2337 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2338 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2339 }
2340 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2341 {
2342 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2343 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2344 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2345 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2346 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2347 }
2348 else
2349 {
2350 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2351 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2352 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2353 }
2354 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2355
2356 }
2357
2358 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_A2);
2359 msVifGroupDelayFilter(VIF_SOUND_B, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2360 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2361 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2362 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2363 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2364 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2365 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2366 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2367 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2368
2369 //for Non-NTSC Setting
2370 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2371 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2372
2373 break;
2374
2375 case VIF_SOUND_B_NICAM:
2376 if (VIFInitialIn_inst.VifTunerType == 1)
2377 {
2378 // silicon tuner
2379 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2380 {
2381 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2382 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2383 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2384 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2385 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2386 }
2387 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2388 {
2389 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_B;
2390 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2391 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2392 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2393 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2394 }
2395 else
2396 {
2397 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_B & 0x000000FF)); // cr_rate for 6.4 MHz
2398 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>8) & 0x000000FF));
2399 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_B>>16) & 0x000000FF), 0x0F);
2400 }
2401 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_B, _BIT0); // cr_rate not invert
2402 }
2403
2404 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_NICAM);
2405 msVifGroupDelayFilter(VIF_SOUND_B_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2406 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2407 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_B_LOWER_ACI); //Notch N-1 Audio Carrier
2408 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2409 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2410 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2411 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2412 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2413 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2414 //for Non-NTSC Setting
2415 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2416 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2417
2418 break;
2419
2420 case VIF_SOUND_GH:
2421 if (VIFInitialIn_inst.VifTunerType == 1)
2422 {
2423 // silicon tuner
2424 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2425 {
2426 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2427 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2428 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2429 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2430 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2431 }
2432 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2433 {
2434 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2435 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2436 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2437 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2438 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2439 }
2440 else
2441 {
2442 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2443 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2444 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2445 }
2446 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2447 }
2448
2449 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_A2);
2450 msVifGroupDelayFilter(VIF_SOUND_GH, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2451 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_A2_NOTCH);
2452 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2453 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2454 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2455 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2456 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2457 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2458 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2459 //for Non-NTSC Setting
2460 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2461 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2462
2463 break;
2464
2465 case VIF_SOUND_GH_NICAM:
2466 if (VIFInitialIn_inst.VifTunerType == 1)
2467 {
2468 // silicon tuner
2469 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2470 {
2471 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2472 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2473 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2474 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2475 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2476 }
2477 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2478 {
2479 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_GH;
2480 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2481 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2482 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2483 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2484 }
2485 else
2486 {
2487 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_GH & 0x000000FF)); // cr_rate for 6.4 MHz
2488 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>8) & 0x000000FF));
2489 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_GH>>16) & 0x000000FF), 0x0F);
2490 }
2491 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_GH, _BIT0); // cr_rate not invert
2492 }
2493
2494 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_NICAM);
2495 msVifGroupDelayFilter(VIF_SOUND_GH_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2496 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_BG_NICAM_NOTCH);
2497 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_GH_LOWER_ACI); //Notch N-1 Audio Carrier
2498 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2499 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2500 msWriteBit(BYPASS_A_LPF_BG, 0, _BIT1); // A_LPF_BG not bypass
2501 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2502 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2503 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2504 //for Non-NTSC Setting
2505 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2506 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2507
2508 break;
2509
2510 case VIF_SOUND_I:
2511 if (VIFInitialIn_inst.VifTunerType == 1)
2512 {
2513 // silicon tuner
2514 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2515 {
2516 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2517 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2518 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2519 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2520 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2521 }
2522 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2523 {
2524 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_I;
2525 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2526 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2527 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2528 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2529 }
2530 else
2531 {
2532 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_I & 0x000000FF)); // cr_rate for 6.4 MHz
2533 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>8) & 0x000000FF));
2534 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_I>>16) & 0x000000FF), 0x0F);
2535 }
2536 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_I, _BIT0); // cr_rate not invert
2537 }
2538
2539 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_NICAM);
2540 msVifGroupDelayFilter(VIF_SOUND_I, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2541 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_I_NOTCH);
2542 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_I_LOWER_ACI); //Notch N-1 Audio Carrier
2543 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2544 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2545 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2546 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2547 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2548 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2549 //for Non-NTSC Setting
2550 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2551 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2552
2553 break;
2554
2555 case VIF_SOUND_DK1:
2556 if (VIFInitialIn_inst.VifTunerType == 1)
2557 {
2558 // silicon tuner
2559 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2560 {
2561 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2562 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2563 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2564 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2565 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2566 }
2567 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2568 {
2569 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2570 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2571 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2572 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2573 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2574 }
2575 else
2576 {
2577 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2578 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2579 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2580 }
2581 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2582 }
2583
2584 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK1_A2);
2585 msVifGroupDelayFilter(VIF_SOUND_DK1, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2586 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK1_NOTCH);
2587 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2588 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2589 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2590 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2591 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2592 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2593 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2594 //for Non-NTSC Setting
2595 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2596 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2597
2598 break;
2599
2600 case VIF_SOUND_DK2:
2601 if (VIFInitialIn_inst.VifTunerType == 1)
2602 {
2603 // silicon tuner
2604 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2605 {
2606 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2607 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2608 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2609 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2610 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2611 }
2612 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2613 {
2614 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2615 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2616 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2617 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2618 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2619 }
2620 else
2621 {
2622 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2623 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2624 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2625 }
2626 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2627 }
2628
2629 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_A2);
2630 msVifGroupDelayFilter(VIF_SOUND_DK2, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2631 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK2_NOTCH);
2632 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2633 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2634 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2635 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2636 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2637 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2638 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2639 //for Non-NTSC Setting
2640 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2641 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2642
2643 break;
2644
2645 case VIF_SOUND_DK_NICAM:
2646 if (VIFInitialIn_inst.VifTunerType == 1)
2647 {
2648 // silicon tuner
2649 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2650 {
2651 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2652 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2653 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2654 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2655 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2656 }
2657 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2658 {
2659 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2660 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2661 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2662 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2663 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2664 }
2665 else
2666 {
2667 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2668 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2669 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2670 }
2671 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2672 }
2673
2674 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK2_NICAM);
2675 msVifGroupDelayFilter(VIF_SOUND_DK_NICAM, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2676 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK_NICAM_NOTCH);
2677 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2678 msWriteBit(BYPASS_ACI_REJ_NTSC, 1, _BIT6); // bypass ACI_REJ_NTSC_filter
2679 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2680 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2681 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2682 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2683 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2684 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2685 //for Non-NTSC Setting
2686 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2687 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2688
2689 break;
2690
2691 case VIF_SOUND_DK3:
2692 if (VIFInitialIn_inst.VifTunerType == 1)
2693 {
2694 // silicon tuner
2695 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2696 {
2697 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2698 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2699 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2700 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2701 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2702 }
2703 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2704 {
2705 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_DK;
2706 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2707 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2708 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2709 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2710 }
2711 else
2712 {
2713 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_DK & 0x000000FF)); // cr_rate for 6.4 MHz
2714 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>8) & 0x000000FF));
2715 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_DK>>16) & 0x000000FF), 0x0F);
2716 }
2717 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_DK, _BIT0); // cr_rate not invert
2718 }
2719
2720 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_DK3_A2);
2721 msVifGroupDelayFilter(VIF_SOUND_DK3, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2722 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_DK3_NOTCH);
2723 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2724 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2725 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2726 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2727 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2728 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2729 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2730 //for Non-NTSC Setting
2731 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2732 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2733
2734 break;
2735
2736 case VIF_SOUND_L:
2737 if (VIFInitialIn_inst.VifTunerType == 1)
2738 {
2739 // silicon tuner
2740 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2741 {
2742 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2743 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2744 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2745 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2746 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2747 }
2748 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2749 {
2750 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_L;
2751 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2752 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2753 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2754 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2755 }
2756 else
2757 {
2758 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_L & 0x000000FF)); // cr_rate for 6.4 MHz
2759 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>8) & 0x000000FF));
2760 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_L>>16) & 0x000000FF), 0x0F);
2761 }
2762 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_L, _BIT0); // cr_rate not invert
2763 }
2764
2765 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2766 msVifGroupDelayFilter(VIF_SOUND_L, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2767 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2768 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI); //Notch N-1 Audio Carrier
2769 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2770 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2771 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2772 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2773 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2774 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2775 //for Non-NTSC Setting
2776 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2777 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2778
2779 break;
2780
2781 case VIF_SOUND_LL:
2782 if (VIFInitialIn_inst.VifTunerType == 1)
2783 {
2784 // silicon tuner
2785 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2786 {
2787 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2788 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2789 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2790 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2791 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2792 }
2793 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2794 {
2795 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_LL;
2796 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2797 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2798 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2799 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2800 }
2801 else
2802 {
2803 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_LL & 0x000000FF)); // cr_rate for 6.4 MHz
2804 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>8) & 0x000000FF));
2805 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_LL>>16) & 0x000000FF), 0x0F);
2806 }
2807 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_LL, _BIT0); // cr_rate not invert
2808 }
2809
2810 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_SECAM_L_NICAM);
2811 msVifGroupDelayFilter(VIF_SOUND_LL, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2812 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_L_NICAM_NOTCH);
2813 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_PAL_DK_LOWER_ACI);//Notch N-1 Audio Carrier
2814 msWriteBit(A_LPF_BG_SEL, 0, _BIT6); // A_LPF_BG_SEL = 0 (PAL)
2815 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2816 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2817 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2818 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2819 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2820 //for Non-NTSC Setting
2821 msWriteBit(V_ACI_BPF_SEL, 1 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2822 msWriteBit(A_ACI_BPF_SEL, 1 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2823
2824 break;
2825
2826 case VIF_SOUND_MN:
2827 if (VIFInitialIn_inst.VifTunerType == 1)
2828 {
2829 // silicon tuner
2830 if((VifShiftClk/*g_VifShiftClk*/ == 1)&&(VIF_IS_ADC_48MHz == 0))
2831 {
2832 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2833 VifCrRateTemp = (VifCrRateTemp *2107)>>11; // 43.2/42 = 1.02857 ~= 1.02881
2834 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2835 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2836 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2837 }
2838 else if((VifShiftClk/*g_VifShiftClk*/ == 2)&&(VIF_IS_ADC_48MHz == 0))
2839 {
2840 VifCrRateTemp = VIFInitialIn_inst.VifCrRate_MN;
2841 VifCrRateTemp = (VifCrRateTemp *1993)>>11; // 43.2/44.4 = 0.97297 ~= 0.97314
2842 msWriteByte(CR_RATE, (BYTE) (VifCrRateTemp & 0x000000FF)); // cr_rate for 6.4 MHz
2843 msWriteByte(CR_RATE+1, (BYTE) ((VifCrRateTemp>>8) & 0x000000FF));
2844 msWriteByteMask(CR_RATE+2, (BYTE) ((VifCrRateTemp>>16) & 0x000000FF), 0x0F);
2845 }
2846 else
2847 {
2848 msWriteByte(CR_RATE, (BYTE) (VIFInitialIn_inst.VifCrRate_MN & 0x000000FF)); // cr_rate for 6.4 MHz
2849 msWriteByte(CR_RATE+1, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>8) & 0x000000FF));
2850 msWriteByteMask(CR_RATE+2, (BYTE) ((VIFInitialIn_inst.VifCrRate_MN>>16) & 0x000000FF), 0x0F);
2851 }
2852 msWriteBit(CR_RATE_INV, VIFInitialIn_inst.VifCrInvert_MN, _BIT0); // cr_rate not invert
2853 }
2854
2855 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_A2);
2856 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_GDE_MN_NOTCH);
2857 msVifGroupDelayFilter(VIF_SOUND_MN, (FrequencyBand)VIFInitialIn_inst.VifFreqBand);
2858 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_NTSC_MN_LOWER_ACI); //Notch N-1 Audio Carrier
2859 msWriteBit(A_LPF_BG_SEL, 1, _BIT6); // A_LPF_BG_SEL = 1 (NTSC)
2860 msWriteBit(BYPASS_CO_A_REJ_NTSC, 1, _BIT5); // CO_A_REJ_NTSC bypass
2861 msWriteBit(BYPASS_A_LPF_BG, 1, _BIT1); // A_LPF_BG bypass
2862 msWriteBit(BYPASS_N_A3, 0, _BIT5); // A3 notch not bypass
2863 msWriteBit(BYPASS_N_A4, 0, _BIT6); // A4 notch not bypass
2864 msWriteBit(BYPASS_N_A5, 0, _BIT3); //Notch_S filter not bypass
2865 //for NTSC Setting
2866 msWriteBit(V_ACI_BPF_SEL, 0 , _BIT2); // Video_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2867 msWriteBit(A_ACI_BPF_SEL, 0 , _BIT3); // Audio_ACI_BPF_Selective 0:ACI_BPF_6M , 1:ACI_BPF_7M
2868
2869 break;
2870
2871 default:
2872 break;
2873 }
2874 msVifLoadEQCoeff(ucSoundSystem);
2875 }
2876
2877 // For API
msVifTopAdjust(void)2878 void msVifTopAdjust(void)
2879 {
2880 HALVIFDBG(printf("\r\nmsVifTopAdjust() "));
2881
2882 if (!_hal_VIF.bBaseAddrInitialized) return ;
2883
2884 if (VIFInitialIn_inst.VifTunerType == 0)
2885 {
2886 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifTop, 0x1F); // pga2 min
2887 msWriteByteMask(AGC_PGA2_OV, VIFInitialIn_inst.VifTop, 0x1F);
2888 msWriteBit(AGC_PGA2_OREN, 1, _BIT1);
2889 msWriteBit(AGC_PGA2_OREN, 0, _BIT1);
2890 }
2891 }
2892
msVifDynamicTopAdjust(void)2893 void msVifDynamicTopAdjust(void)
2894 {
2895 HALVIFDBG(printf("\r\nmsVifDynamicTopAdjust() "));
2896
2897 if (!_hal_VIF.bBaseAddrInitialized) return ;
2898
2899 BYTE mean256=0, agc_pga2=0, ref=0, diff=0;
2900 WORD vga=0;
2901
2902 if (VIFInitialIn_inst.VifTunerType == 0)
2903 {
2904 vga = msRead2Bytes(AGC_VGA);
2905 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
2906 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
2907 ref = msReadByte(AGC_REF); // AGC ref
2908
2909 if (g_bCheckModulationType == 0)
2910 {
2911 diff = 0x15; // negative modulation
2912 }
2913 else
2914 {
2915 diff = 0x0A; // positive modulation
2916 }
2917
2918 if ((vga == VIFInitialIn_inst.VifVgaMinimum) && (mean256 >= (ref+diff)) && (agc_pga2 == VIFInitialIn_inst.VifTop))
2919 {
2920 msWriteByteMask(AGC_PGA2_MIN, VIFInitialIn_inst.VifDynamicTopMin, 0x1F); // pga2 min
2921 }
2922 else if (((agc_pga2) < VIFInitialIn_inst.VifTop) && ((vga >= 0xF000) || (vga <= VIFInitialIn_inst.VifVgaMaximum)))
2923 {
2924 msVifTopAdjust();
2925 }
2926 }
2927 }
2928
msVifLoad(void)2929 void msVifLoad(void)
2930 {
2931 if (!_hal_VIF.bBaseAddrInitialized) return ;
2932
2933 RIU_WriteRegBit(RF_LOAD , 1 , _BIT0);
2934 RIU_WriteRegBit(DBB1_LOAD , 1 , _BIT0);
2935 RIU_WriteRegBit(DBB2_LOAD , 1 , _BIT0);
2936 RIU_WriteRegBit(DBB2_LOAD , 0, _BIT0);
2937 }
2938
2939 // For API
msVifInitial(void)2940 void msVifInitial(void)
2941 {
2942 HALVIFDBG(printf("\r\nmsVifInitial()"));
2943
2944 if (!_hal_VIF.bBaseAddrInitialized) return ;
2945
2946 // VifShiftClk : 0x1121_D3
2947 BYTE VifShiftClk = msReadByte(VIF_RF_RESERVED_1+1);
2948
2949 msWriteByteMask(VIF_SOFT_RSTZ, 0x00, 0x7F); // VIF software reset
2950 msWriteBit(CLAMPGAIN_RSTZ, 0, _BIT0); // clampgain software reset
2951 msWriteBit(VSYNC_RSTZ, 0, _BIT0); // vsync software reset
2952
2953 g_ucVifStatusStep = VIF_START;
2954
2955 //Serious_ACI_Det parameter
2956 AGC_Change_Index = 0;
2957 RIU_WriteByte(0x1286EL, 0x04); // ADC Setting Overflow value
2958
2959 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
2960 {
2961 g_bCheckModulationType = 1; // positive modulation
2962 g_bCheckIFFreq = (g_ucVifSoundSystemType == VIF_SOUND_L) ? 0 : 1; // 0: 38.9 MHz; 1: 33.9 MHz
2963 }
2964 else
2965 {
2966 g_bCheckModulationType = 0; // negative modulation
2967 g_bCheckIFFreq = 0; // 38.9 MHz
2968 }
2969
2970 if (g_bCheckModulationType == 1)
2971 {
2972 msWriteByteMask(MODULATION_TYPE, 0x0F, 0x0F); // positive modulation
2973 }
2974 else
2975 {
2976 msWriteByteMask(MODULATION_TYPE, 0x00, 0x0F); // negative modulation
2977 }
2978
2979 // AGC
2980 if (g_bCheckModulationType == 1)
2981 {
2982 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2983 msWriteByteMask(AGC_PEAK_CNT_H, 0x0B, 0x0F);
2984 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefPositive); // AGC ref
2985 }
2986 else
2987 {
2988 msWriteByte(AGC_PEAK_CNT_L, 0x00); // AGC peak cnt
2989 msWriteByteMask(AGC_PEAK_CNT_H, 0x0C, 0x0F);
2990 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
2991 }
2992 msWriteByteMask(AGC_MEAN_SEL, _BIT2, _BIT2|_BIT3); // mean16
2993 msWriteByte(AGC_LINE_CNT_L, 0x01); // AGC line cnt = 1
2994 msWriteByte(AGC_LINE_CNT_H, 0x00);
2995
2996 if (bEnableUsrNonSteadyAgcK)
2997 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
2998 else
2999 {
3000 if (VIFInitialIn_inst.VifTunerType == 1)
3001 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
3002 else
3003 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
3004 }
3005
3006 msWriteByteMask(AGC_PGA2_OREN, 0x00, 0x03);
3007 msWriteByte(AGC_VGA_MAX_L, VIFInitialIn_inst.VifVgaMaximum); // vga max
3008 msWriteByte(AGC_VGA_MAX_H, VIFInitialIn_inst.VifVgaMaximum>>8);
3009 msWriteByte(AGC_VGA_MIN_L, VIFInitialIn_inst.VifVgaMinimum); // vga min
3010 msWriteByte(AGC_VGA_MIN_H, VIFInitialIn_inst.VifVgaMinimum>>8);
3011 msWriteByteMask(AGC_PGA1_MAX, 0x00, 0x0F); // pga1 max
3012 if (VIFInitialIn_inst.VifTunerType == 1)
3013 msWriteByteMask(AGC_PGA2_MAX, 0x00, 0x1F); // pga2 max
3014 else
3015 msWriteByteMask(AGC_PGA2_MAX, 0x1F, 0x1F); // pga2 max
3016
3017 msWriteByte(VAGC_VGA2_OV_L, 0x00); // VGA2(IFAGC) output minimun
3018 msWriteByte(VAGC_VGA2_OV_H, 0x80);
3019 msWriteBit(VAGC_VGA2_OREN, 1, _BIT2);
3020
3021 if ((VIFInitialIn_inst.VifSawArch == SILICON_TUNER) || (VIFInitialIn_inst.VifSawArch == NO_SAW) ||(VIFInitialIn_inst.VifSawArch == SAVE_PIN_VIF))
3022 msWriteBit(VAGC_VGA_OUT_SEL, 1, _BIT0); // VGA1 -> IFAGC
3023
3024 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
3025 {
3026 msWriteBit(LEVEL_SENSE_BYPASS, 0, _BIT0); // Level_Sense not bypass
3027 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
3028 msWriteBit(BYPASS_V_ACI_BPF4AGC, 0, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
3029 }
3030 else
3031 {
3032 msWriteBit(LEVEL_SENSE_BYPASS, 1, _BIT0); // Level_Sense bypass
3033 msWriteBit(LEVEL_SENSE_OUT_SEL, 0, _BIT4); // DVGA input: 0: from LEVEL_SENSE out(can be bypassed); 1: ACI_BPF out(cannot be bypassed)
3034 msWriteBit(BYPASS_V_ACI_BPF4AGC, 1, _BIT0); // bypass ACI_BPF before AGC input: 0:not bypass; 1: bypass
3035 }
3036
3037 msWriteBit(AGC_IN_SEL, 1, _BIT1); // AGC input 0: from SOS_out ; 1:from ACI_BPF out(can be bypassed)
3038
3039 // AGC gain distribution
3040 msWriteBit(AGC_DBB_VVGA_SEL, 0, _BIT3); // Vga gain force x1
3041 msWriteBit(AGC_DBB_AVGA_SEL, 0, _BIT4); // Avga gain force x1
3042
3043 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.VifVgaMaximum); // vga threshold
3044 msWriteByte(AGC_VGA_THR+1, (VIFInitialIn_inst.VifVgaMaximum - 0x1000)>>8);
3045 msWriteByte(AGC_VGA_BASE, (VIFInitialIn_inst.VifAgcVgaBase - 0x14)); // vga base
3046 msWriteByte(AGC_VGA_OFFS, VIFInitialIn_inst.VifAgcVgaOffs); // vga offset
3047
3048 msWriteBit(AGC_ENABLE, 1, _BIT0); // AGC enable
3049
3050 // CR
3051 msWriteByte(CR_DL_A, 0x16); // CR audio delay line
3052 msWriteByte(CR_PD_ERR_MAX_L, 0xFF); // CR pd error max
3053 msWriteByteMask(CR_PD_ERR_MAX_H, 0x3F, 0x3F);
3054 msWriteByte(CR_NOTCH_A1_L, 0x41); // CR notch filter coefficient
3055 msWriteByte(CR_NOTCH_A1_H, 0x0C);
3056 msWriteByte(CR_NOTCH_A2_L, 0xE9); // CR notch filter coefficient
3057 msWriteByte(CR_NOTCH_A2_H, 0x0B);
3058 msWriteByte(CR_NOTCH_B1_L, 0x58); // CR notch filter coefficient
3059 msWriteByte(CR_NOTCH_B1_H, 0x00);
3060 msWriteBit(CR_ANCO_SEL, 1, _BIT0); // audio nco select
3061 if (VIFInitialIn_inst.VifTunerType == 2)
3062 {
3063 msWriteByteMask(CR_KF1_HW, 0x00, 0x0F); // kf1 hardware mode
3064 msWriteByteMask(CR_KP1_HW, 0x00, 0x0F); // kp1 hardware mode
3065 msWriteByteMask(CR_KI1_HW, 0x00, 0xF0);// ki1 hardware mode
3066 msWriteByteMask(CR_KP2_HW, 0x00, 0x0F); // kp2 hardware mode
3067 msWriteByteMask(CR_KI2_HW, 0x00, 0xF0);// ki2 hardware mode
3068 msWriteBit(CR_K_SEL, 0, _BIT6); // hw mode
3069 }
3070 else
3071 {
3072 msWriteByteMask(CR_KF1_HW, VIFInitialIn_inst.VifCrKf1, 0x0F); // kf1 hardware mode
3073 msWriteByteMask(CR_KP1_HW, VIFInitialIn_inst.VifCrKp1, 0x0F); // kp1 hardware mode
3074 msWriteByteMask(CR_KI1_HW, VIFInitialIn_inst.VifCrKi1<<4, 0xF0);// ki1 hardware mode
3075 msWriteByteMask(CR_KP2_HW, VIFInitialIn_inst.VifCrKp2, 0x0F); // kp2 hardware mode
3076 msWriteByteMask(CR_KI2_HW, VIFInitialIn_inst.VifCrKi2<<4, 0xF0);// ki2 hardware mode
3077 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
3078 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1); // for > 150% overmodulation
3079 }
3080 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
3081 msWriteByteMask(CR_KP_SW, 0x00, 0x0F); // kp software mode
3082 msWriteByteMask(CR_KI_SW, 0x00, 0xF0); // ki software mode
3083 msWriteBit(CR_JTRDET_IN_SEL, 1, _BIT4); // carrier jitter detector input select CR_LF1
3084 msWriteBit(VNCO_INV_OREN, 0, _BIT1);
3085
3086 //locking range setting
3087 msWriteBit(CR_FD_IN_SEL, 0 , _BIT0); //0:IIR LPF2; 1:FIR
3088 msWriteBit(CR_IIR_SEL, 1 , _BIT1); //0:IIR LPF1; 1:IIR LPF2
3089
3090 if(VIFInitialIn_inst.VifCrPdModeSel == 0) // 0: imaginary part; 1: cordic
3091 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF1); // IIR LPF1 coefficients
3092 else
3093 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
3094
3095 msWriteBit(CR_LPF_SEL, VIFInitialIn_inst.VifCrLpfSel, _BIT4); // CR LPF 0: FIR LPF; 1: IIR LPF
3096 msWriteBit(CR_PD_MODE, VIFInitialIn_inst.VifCrPdModeSel, _BIT1); // 0: imaginary part; 1: cordic
3097 msWriteBit(LOCK_LEAKY_SEL, VIFInitialIn_inst.VifCrLockLeakySel, _BIT0);
3098 msWriteBit(CR_PD_X2, VIFInitialIn_inst.VifCrPdX2, _BIT2); // CR X2 0: lock 0 degree; 1: lock 0 or 180 degree
3099 msWriteByte(CR_LOCK_TH_L, VIFInitialIn_inst.VifCrLockThr); // CR lock threshold
3100 msWriteByteMask(CR_LOCK_TH_H, VIFInitialIn_inst.VifCrLockThr>>8, 0x03);
3101 msWriteByte(CR_UNLOCK_NUM, 0x00); // CR unlock num
3102 msWriteByte(CR_UNLOCK_NUM+1, 0x40);
3103 msWriteByteMask(CR_UNLOCK_NUM+2, 0x00, 0x0F);
3104 msWriteByte(CR_LOCK_NUM, VIFInitialIn_inst.VifCrLockNum); // CR lock num
3105 msWriteByte(CR_LOCK_NUM+1, VIFInitialIn_inst.VifCrLockNum>>8);
3106 msWriteByteMask(CR_LOCK_NUM+2, VIFInitialIn_inst.VifCrLockNum>>16, 0x0F);
3107 msWriteByte(CR_CODIC_TH, VIFInitialIn_inst.VifCrThr); // CR cordic threshold
3108 msWriteByteMask(CR_CODIC_TH+1, VIFInitialIn_inst.VifCrThr>>8, 0x3F);
3109
3110 if (VIFInitialIn_inst.VifTunerType == 0)
3111 {
3112 if (VifShiftClk/*g_VifShiftClk*/ == 1)
3113 {
3114 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
3115 msWriteByte(CR_RATE+1, 0xDB);
3116 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3117 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3118 }
3119 else if(VifShiftClk/*g_VifShiftClk*/ == 2)
3120 {
3121 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
3122 msWriteByte(CR_RATE+1, 0x9F);
3123 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
3124 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3125 }
3126 else
3127 {
3128 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
3129 msWriteByte(CR_RATE+1, 0x38);
3130 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
3131 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
3132 }
3133 }
3134
3135 // tuner step size
3136 //VIFInitialIn_inst.VifTunerStepSize = FREQ_STEP_62_5KHz;
3137 if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_62_5KHz) // 62.5KHz
3138 {
3139 if (g_bCheckIFFreq == 0)
3140 {
3141 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xB3); // foe scaling factor
3142 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x02, 0x0F);
3143 }
3144 else
3145 { // SECAM L'
3146 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x4D); // foe scaling factor
3147 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0D, 0x0F);
3148 }
3149 }
3150 else if (VIFInitialIn_inst.VifTunerStepSize == FREQ_STEP_50KHz) // 50KHz
3151 {
3152 if (g_bCheckIFFreq == 0)
3153 {
3154 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0x60); // foe scaling factor
3155 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x03, 0x0F);
3156 }
3157 else
3158 { // SECAM L'
3159 msWriteByte(CR_FOE_SCAL_FACTOR_L, 0xA0); // foe scaling factor
3160 msWriteByteMask(CR_FOE_SCAL_FACTOR_H, 0x0C, 0x0F);
3161 }
3162 }
3163
3164 // Filter
3165 msWriteBit(DEBUG_V_A, 1, _BIT5); // single ADC
3166 if (VIFInitialIn_inst.ChinaDescramblerBox !=0)
3167 {
3168 msWriteByteMask(IMAGE_REJ_IIR_SEL, _BIT3, _BIT2|_BIT3); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
3169 }
3170 msWriteByteMask(IMAGE_REJ1_SEL, _BIT0, _BIT0|_BIT1); // 0: aci_rej_out; 1: nyq_slp_out1; 2: nyq_slp_out2; 3: mixer_out_i
3171 msWriteBit(BYPASS_CO_A_REJ, 0, _BIT4); // CO_A_REJ not bypass
3172
3173 msWriteBit(IMAGE_REJ_OUT_SEL, 0, _BIT7); // 0: IMAGE_REJ1; 1: IMAGE_REJ_IIR
3174 msWriteBit(A_BP_OUT_X2, 1, _BIT7); // A_BP output x2
3175 msWriteBit(A_DAGC_SEL, 1, _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
3176 msWriteBit(BYPASS_A_NOTCH, 1, _BIT6); // A_NOTCH bypass
3177 msWriteBit(BYPASS_A_SOS, 1, _BIT7); // A_SOS bypass
3178 msWriteBit(BYPASS_SOS21, 0, _BIT2); // SOS21 not bypass
3179 msWriteBit(BYPASS_SOS22, 0, _BIT3); // SOS22 not bypass
3180 msWriteBit(BYPASS_SOS31, 0, _BIT4); // SOS31 not bypass
3181 msWriteBit(BYPASS_SOS32, 0, _BIT5); // SOS32 not bypass
3182
3183 // silicon tuner
3184 if (VIFInitialIn_inst.VifTunerType == 1)
3185 {
3186 msWriteBit(BYPASS_V_ACI_BPF4LS, 1, _BIT5); // VACI_BPF bypass
3187 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
3188 msWriteBit(BYPASS_VSPUR_REJ, 1, _BIT2); // VSPUR_REJ bypass
3189 msWriteBit(BYPASS_ASPUR_REJ, 1, _BIT3); // ASPUR_REJ bypass
3190
3191 if ((msReadByte(CR_RATE_INV) & 0x01) != 0)
3192 msWriteBit(BYPASS_SOS11, 1, _BIT0); // SOS11 bypass
3193 }
3194 else
3195 {
3196 msWriteBit(BYPASS_A_ACI_BPF, 0, _BIT1); // AACI_BPF not bypass
3197 }
3198
3199 // DAGC1
3200 if (_bit1_(VIFInitialIn_inst.VifDelayReduce))
3201 {
3202 msWriteBit(DAGC1_DL_BYPASS, 1, _BIT3); // DAGC1 delay line bypass
3203 }
3204 else
3205 {
3206 msWriteBit(DAGC1_DL_BYPASS, 0, _BIT3); // DAGC1 delay line not bypass
3207 }
3208 msWriteBit(DAGC1_BYPASS, 0, _BIT1); // DAGC1 not bypass
3209
3210 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
3211 msWriteBit(DAGC1_OREN, 0, _BIT6); // DAGC1 gain_overwrite = 0
3212
3213 msWriteBit(DAGC1_GAIN0_FB_EN, 0, _BIT2); // DAGC1 gain_update = 1
3214
3215 if (g_bCheckModulationType == 1)
3216 {
3217 msWriteByteMask(DAGC1_REF, 0x0B, 0x3F); // DAGC1 ref
3218 msWriteByteMask(DAGC1_RATIO, 0x03, 0x07); // DAGC1 ratio
3219 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
3220 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0B, 0x0F);
3221 msWriteByte(DAGC1_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc1GainOv);
3222 msWriteByteMask(DAGC1_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc1GainOv>>8, 0x3F);
3223 }
3224 else
3225 {
3226 msWriteByteMask(DAGC1_REF, VIFInitialIn_inst.VifDagc1Ref, 0x3F); // DAGC1 ref
3227 msWriteByteMask(DAGC1_RATIO, 0x00, 0x07); // DAGC1 ratio
3228 msWriteByte(DAGC1_PEAK_CNT_L, 0x00); // DAGC1 peak cnt
3229 msWriteByteMask(DAGC1_PEAK_CNT_H, 0x0C, 0x0F);
3230 }
3231 msWriteBit(DAGC1_ENABLE, 1, _BIT0); // DAGC1 enable
3232
3233 // DAGC2
3234 if (_bit2_(VIFInitialIn_inst.VifDelayReduce))
3235 {
3236 msWriteBit(DAGC2_DL_BYPASS, 1, _BIT3); // DAGC2 delay line bypass
3237 }
3238 else
3239 {
3240 msWriteBit(DAGC2_DL_BYPASS, 0, _BIT3); // DAGC2 delay line not bypass
3241 }
3242 msWriteBit(DAGC2_BYPASS, 0, _BIT1); // DAGC2 not bypass
3243
3244 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
3245 msWriteBit(DAGC2_OREN, 0, _BIT6); // DAGC2 gain_overwrite = 0
3246
3247 msWriteBit(DAGC2_GAIN0_FB_EN, 0, _BIT2); // DAGC2 gain_update = 1
3248
3249 if (g_bCheckModulationType == 1)
3250 {
3251 msWriteByteMask(DAGC2_REF, 0x0B, 0x3F); // DAGC2 ref
3252 msWriteByteMask(DAGC2_RATIO, 0x03, 0x07); // DAGC2 ratio
3253 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
3254 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0B, 0x0F);
3255 msWriteByte(DAGC2_GAIN_OVERWRITE_L, VIFInitialIn_inst.VifDagc2GainOv);
3256 msWriteByteMask(DAGC2_GAIN_OVERWRITE_H, VIFInitialIn_inst.VifDagc2GainOv>>8, 0x3F);
3257 }
3258 else
3259 {
3260 msWriteByteMask(DAGC2_REF, VIFInitialIn_inst.VifDagc2Ref, 0x3F); // DAGC2 ref
3261 msWriteByteMask(DAGC2_RATIO, 0x00, 0x07); // DAGC2 ratio
3262 msWriteByte(DAGC2_PEAK_CNT_L, 0x00); // DAGC2 peak cnt
3263 msWriteByteMask(DAGC2_PEAK_CNT_H, 0x0C, 0x0F);
3264 }
3265 msWriteBit(DAGC2_ENABLE, 1, _BIT0); // DAGC2 enable
3266
3267 // clampgain
3268 if (g_bCheckModulationType == 1)
3269 {
3270 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvPositive); // clampgain clamp overwrite value
3271 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvPositive>>8, 0x07);
3272 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvPositive); // clampgain gain overwrite value
3273 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvPositive>>8, 0x07);
3274 }
3275 else
3276 {
3277 msWriteByte(CLAMPGAIN_CLAMP_OVERWRITE, VIFInitialIn_inst.VifClampgainClampOvNegative); // clampgain clamp overwrite value
3278 msWriteByteMask(CLAMPGAIN_CLAMP_OVERWRITE+1, VIFInitialIn_inst.VifClampgainClampOvNegative>>8, 0x07);
3279 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, VIFInitialIn_inst.VifClampgainGainOvNegative); // clampgain gain overwrite value
3280 msWriteByteMask(CLAMPGAIN_GAIN_OVERWRITE+1, VIFInitialIn_inst.VifClampgainGainOvNegative>>8, 0x07);
3281 }
3282 msWriteBit(CLAMPGAIN_BYPASS, 0, _BIT1); // clampgain not bypass
3283 msWriteBit(CLAMPGAIN_SEL, VIFInitialIn_inst.VifClampgainClampSel, _BIT3); // 0: clamp select sync bottom; 1: clamp select porch
3284 msWriteByte(CLAMPGAIN_SYNCBOTT_REF, VIFInitialIn_inst.VifClampgainSyncbottRef); // porch or syncbottom ref
3285 msWriteByte(CLAMPGAIN_SYNCHEIGHT_REF, VIFInitialIn_inst.VifClampgainSyncheightRef); // syncheight ref
3286 msWriteByteMask(CLAMPGAIN_KC, VIFInitialIn_inst.VifClampgainKc, 0x07); // kc
3287 msWriteByteMask(CLAMPGAIN_KG, VIFInitialIn_inst.VifClampgainKg<<4, 0x70); // kg
3288 msWriteByte(CLAMPGAIN_PORCH_CNT, VIFInitialIn_inst.VifClampgainPorchCnt); // clampgain porch cnt for NTSC
3289 msWriteByteMask(CLAMPGAIN_PORCH_CNT+1, VIFInitialIn_inst.VifClampgainPorchCnt>>8, 0x01);
3290 msWriteByte(CLAMPGAIN_CLAMP_MIN, VIFInitialIn_inst.VifClampgainClampMin); // clampgain clamp min
3291 msWriteByte(CLAMPGAIN_CLAMP_MAX, VIFInitialIn_inst.VifClampgainClampMax); // clampgain clamp max
3292 msWriteByte(CLAMPGAIN_GAIN_MIN, VIFInitialIn_inst.VifClampgainGainMin); // clampgain gain min
3293 msWriteByte(CLAMPGAIN_GAIN_MAX, VIFInitialIn_inst.VifClampgainGainMax); // clampgain gain max
3294 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainClampOren, _BIT0); // clampgain clamp overwrite enable
3295 msWriteBit(CLAMPGAIN_CLAMP_OREN, VIFInitialIn_inst.VifClampgainGainOren, _BIT1); // clampgain gain overwrite enable
3296 msWriteBit(CLAMPGAIN_EN, 1, _BIT2); // clampgain enable
3297
3298 // vsync
3299 msWriteBit(VSYNC_ENABLE, 1, _BIT1); // vsync enable
3300
3301 // ADAGC
3302 if (g_bCheckModulationType == 1)
3303 {
3304 msWriteBit(ADAGC_BYPASS, 1, _BIT1); // ADAGC bypass
3305 msWriteByteMask(ADAGC_K, 0x00, 0x07); // ADAGC k
3306 msWriteBit(ADAGC_ENABLE, 0, _BIT0); // ADAGC disable
3307 }
3308 else
3309 {
3310 msWriteBit(ADAGC_BYPASS, 0, _BIT1); // ADAGC not bypass
3311 msWriteByteMask(ADAGC_K, 0x04, 0x07); // ADAGC k
3312 msWriteBit(ADAGC_ENABLE, 1, _BIT0); // ADAGC enable
3313 }
3314
3315 if(VIFInitialIn_inst.VifSeriousACIDetect == 1) //ACI_Functions_Selective
3316 {
3317 VIFInitialIn_inst.VifACIDetect = 0;
3318 }
3319
3320 // zero detector
3321 msWriteBit(ZERO_IN_SEL, 1 , _BIT1); // 0: from dagc_in; 1: from dagc_out
3322 msWriteByteMask(ZERO_TH, 0x20, 0x7F);
3323 msWriteByte(ZERO_CNT_NUM, 0x0A);
3324 msWriteByteMask(ZERO_CNT_NUM+1, 0x00, 0x0F);
3325 msWriteByte(ZERO_ZERO_NUM, 0x20);
3326 msWriteByte(ZERO_ZERO_NUM+1, 0x00);
3327 msWriteBit(ZERO_ENABLE, 0 , _BIT0); // zero detector disable
3328
3329 // Level Sense setting
3330 msWriteByte(LEVEL_SENSE_LOCK_CNT, 0x00);
3331 msWriteByte(LEVEL_SENSE_LOCK_CNT+1, 0x01);
3332
3333 msWriteByte(LEVEL_SENSE_DIFF_AVG_TH, 0x28);
3334 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_TH+1, 0x00, 0x0F);
3335
3336 msWriteBit(LEVEL_SENSE_EN, 1, _BIT0);
3337 msWriteBit(LEVLE_SENSE_MOD_TYPE, 0, _BIT4); // 0: negedge; 1: posedge
3338 msWriteBit(LEVEL_SENSE_MODE, 0, _BIT0); // 0: porch; 1: sync height
3339 msWriteBit(LEVEL_SENSE_VGA_OREN, 0, _BIT4);
3340
3341 msWriteByteMask(LEVEL_SENSE_MEAN_SEL, 0x01, 0x03); // 0: 1 line; 1: 16 lines; 2, 3: 256 lines
3342 msWriteBit(LEVEL_SENSE_DVGA_OREN_SEL, 1 , _BIT4); // 0: SW; 1: HW
3343
3344 msWriteByte(LEVEL_SENSE_REF, 0x59);
3345 msWriteByte(LEVEL_SENSE_REF+1, 0x00);
3346
3347 msWriteByte(LEVEL_SENSE_LINE_CNT, 0x04);
3348 msWriteByte(LEVEL_SENSE_LINE_CNT+1, 0x00);
3349
3350 msWriteByte(LEVEL_SENSE_PORCH_CNT, 0xE0);
3351 msWriteByteMask(LEVEL_SENSE_PORCH_CNT+1, 0x00, 0x01);
3352
3353 msWriteByte(LEVEL_SENSE_PEAK_CNT , 0x00);
3354 msWriteByteMask(LEVEL_SENSE_PEAK_CNT +1, 0x0C, 0x0F);
3355
3356 msWriteByteMask(LEVEL_SENSE_K, 0x04, 0x07); // 0~7: 0, 2^-2 ~ 2^-8
3357 msWriteByteMask(LEVEL_SENSE_K+1, 0x00, 0x00);
3358
3359 msWriteByte(LEVEL_SENSE_VGA_OV, 0x80);
3360 msWriteByte(LEVEL_SENSE_VGA_OV+1, 0x00);
3361
3362 msWriteByte(LEVEL_SENSE_DIFF_AVG_INI, 0xFF); // level_sense diff_avg initial value
3363 msWriteByteMask(LEVEL_SENSE_DIFF_AVG_INI+1, 0x0F, 0x0F);
3364
3365 //AM Hum detection setting
3366 msWriteByteMask(AGC_HUM_CNT_MAX , _BIT5 , _BIT4|_BIT5|_BIT6); // 0->128 ,1->256, 2->512 samples
3367 msWriteByte(AGC_HUM_ERR_THR , 0x20); // format <8,8> => 0.125 = 0x20
3368 msWriteByte(AGC_HUM_DET_LIM , 0x20); // format <8,-2> => 128 samples
3369
3370 //CR_Ki/Kp speed up setting
3371 msWriteBit(CR_KPKI_SPEEDUP_EN , 0 , _BIT0); //0:disable , 1:enable
3372 msWriteBit(CR_INV2_EN , 0 , _BIT4); //0:disable , 1:enable
3373 msWriteByteMask(CR_KP_SPEED, _BIT2 , _BIT0|_BIT1|_BIT2|_BIT3);
3374 msWriteByteMask(CR_KI_SPEED, _BIT6 , _BIT4|_BIT5|_BIT6|_BIT7);
3375
3376 if(VIF_IS_ADC_48MHz == 0)
3377 {
3378 // VIF ADC clock setting
3379 msWriteBit(VIF_ADC_48M, 0, _BIT4); // 0:144MHz , 1:48MHz
3380
3381 // VIF DECI_filter coefficient selection
3382 msWriteBit(VIF_DECI_COEF_SEL, 0, _BIT4); // 0:old, 1:new
3383
3384 msWriteBit(HALVIFDBG2_BIT, 0, _BIT4); // 0:144MHz, 1:48MHz
3385 }
3386 else
3387 {
3388 // VIF ADC clock setting
3389 msWriteBit(VIF_ADC_48M, 1, _BIT4); // 0:144MHz , 1:48MHz
3390
3391 // VIF DECI_filter coefficient selection
3392 msWriteBit(VIF_DECI_COEF_SEL, 1, _BIT4); // 0:old, 1:new
3393
3394 msWriteBit(HALVIFDBG2_BIT, 1, _BIT4); // 0:144MHz, 1:48MHz
3395 }
3396
3397 // VIF ADC LSB mask
3398 msWriteByteMask(VIF_ADC_LSB_MASK, 0x00, _BIT0|_BIT1); // Un-mask ADC_LSB bits
3399
3400 // locking range +/- 500KHz -> +/- 1MHz setting
3401 //msWriteByteMask(CR_KF1_HW, 0x02, 0x0F); // kf1 hardware mode
3402 //msWriteByteMask(CR_KP1_HW, 0x43, 0x0F); // kp1 hardware mode
3403 //msWriteByteMask(CR_KI1_HW, 0x43, 0xF0); // ki1 hardware mode
3404 //msWriteByteMask(CR_FD_DELAY_SEL, _BIT5, _BIT4|_BIT5);
3405 //msWriteByteMask(CR_FD_MU, _BIT5, _BIT4|_BIT5);
3406
3407 //msWriteBit(BYPASS_SOS33, 1, _BIT6);
3408
3409 // real HW_KPKI_THR1_L
3410 msWriteByte(KPKI_ADJ_TH1_L, 0x50);
3411 msWriteByte(KPKI_ADJ_TH1_L+1, 0x00);
3412
3413 // real HW_KPKI_THR1_H
3414 msWriteByte(KPKI_ADJ_TH1_H, 0x50);
3415 msWriteByte(KPKI_ADJ_TH1_H+1, 0x00);
3416
3417 // real HW_KPKI_THR2_L
3418 msWriteByte(KPKI_ADJ_TH2_L, 0x00);
3419 msWriteByte(KPKI_ADJ_TH2_L+1, 0x01);
3420
3421 // real HW_KPKI_THR2_H
3422 msWriteByte(KPKI_ADJ_TH2_H, 0x00);
3423 msWriteByte(KPKI_ADJ_TH2_H+1, 0x01);
3424
3425 // real HW_KPKI_THR3_L
3426 msWriteByte(KPKI_ADJ_TH3_L, 0xFF);
3427 msWriteByte(KPKI_ADJ_TH3_L+1, 0xFF);
3428
3429 // real HW_KPKI_THR3_H
3430 msWriteByte(KPKI_ADJ_TH3_H, 0xFF);
3431 msWriteByte(KPKI_ADJ_TH3_H+1, 0xFF);
3432
3433 // real HW_KPKI setting
3434 msWriteByteMask(CR_KP_ADJ1, 0x05, 0x0F);
3435 msWriteByteMask(CR_KI_ADJ1, 0x80, 0xF0);
3436 msWriteByteMask(CR_KP_ADJ2, 0x04, 0x0F);
3437 msWriteByteMask(CR_KI_ADJ2, 0x70, 0xF0);
3438 msWriteByteMask(CR_KP_ADJ3, 0x03, 0x0F);
3439 msWriteByteMask(CR_KI_ADJ3, 0x60, 0xF0);
3440
3441 // real HW_KPKI_disable
3442 msWriteBit(KPKI_ADJ_EN, 0, _BIT0);
3443 g_VifHWKpKiFlag = 1; // 0:SW_Kp/Ki ; 1:Real HW_Kp/Ki
3444 msWriteBit(HALVIFDBG2_BIT, g_VifHWKpKiFlag, _BIT0);
3445
3446 // for China stream setting
3447 msWriteByte(CR_JTR_MAX_CNT, 0x00);
3448 msWriteByte(CR_JTR_MAX_CNT+1, 0x70);
3449 msWriteByteMask(JTR_DELTA_AVE_NUM, 0x20, 0x30);
3450
3451 msWriteBit(BYPASS_N_A1, 1, _BIT2);
3452 msWriteBit(BYPASS_N_A2, 1, _BIT3);
3453 msWriteBit(BYPASS_SOS11, 1, _BIT0);
3454 msWriteBit(BYPASS_SOS12, 1, _BIT1);
3455
3456 //msWriteBit(BYPASS_A_DC, 1, _BIT0); // Bypass A_DC filter
3457 //msWriteBit(BYPASS_A_BPF, 1, _BIT1); // Bypass A_BPF
3458 //msWriteBit(ADAGC_GAIN_OREN, 1, _BIT0); // fixed ADAGC gain
3459 //msWriteByte(ADAGC_GAIN_OV, 0x24);
3460 //msWriteByte(ADAGC_GAIN_OV+1, 0x00);
3461
3462 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7D); // VIF software reset
3463 msWriteBit(CLAMPGAIN_RSTZ, 1, _BIT0); // clampgain software reset
3464 msWriteBit(VSYNC_RSTZ, 1, _BIT0); // vsync software reset
3465
3466 // TOP
3467 msVifTopAdjust();
3468
3469 // version control
3470 msWriteByte(FIRMWARE_VERSION_L, 0x13); // 19(dd)
3471 msWriteByte(FIRMWARE_VERSION_H, 0x90); // 09/16 (mm/yy) firmware version control
3472
3473 HAL_VIF_Delay1ms(1);
3474 msWriteByteMask(VIF_SOFT_RSTZ, 0x7F, 0x7F);
3475 }
3476
3477 // For API
msVifExit(void)3478 void msVifExit(void)
3479 {
3480 if (!_hal_VIF.bBaseAddrInitialized) return ;
3481
3482 // RFAGC/IFAGC disable
3483 RIU_WriteRegBit(RFAGC_ENABLE, 0, _BIT0);
3484 RIU_WriteRegBit(IFAGC_ENABLE, 0, _BIT4);
3485
3486 // AGC Disable
3487 RIU_WriteByte(0x12830L, 0x00);
3488 RIU_WriteByte(0x12831L, 0x00);
3489
3490 RIU_WriteByte(0x11F0AL, 0x11);
3491 RIU_WriteByte(0x11F0BL, 0x11);
3492
3493 RIU_WriteByte(0x11F1CL, 0x11);
3494 RIU_WriteByte(0x11F1DL, 0x11);
3495
3496 RIU_WriteByte(0x11FE3L, 0x11);
3497
3498 RIU_WriteByte(0x11F78L, 0x11);
3499
3500 RIU_WriteByte(0x11F25L, 0x01);
3501
3502 RIU_WriteByte(0x52991L, 0x11);
3503
3504 // SRAM Power Control
3505 RIU_WriteByte(0x12090L, 0xFC);
3506 RIU_WriteByte(0x12091L, 0xFF);
3507
3508 RIU_WriteByte(0x127E0L, 0x00);
3509 RIU_WriteByte(0x127E1L, 0x00);
3510 RIU_WriteByte(0x127E2L, 0x00);
3511 RIU_WriteByte(0x127E3L, 0x00);
3512 RIU_WriteByte(0x127E4L, 0x00);
3513 RIU_WriteByte(0x127E5L, 0x00);
3514 RIU_WriteByte(0x127E6L, 0x00);
3515 RIU_WriteByte(0x127E7L, 0x00);
3516 RIU_WriteByte(0x127E8L, 0x00);
3517 RIU_WriteByte(0x127E9L, 0x00);
3518
3519 // MPLL Power Down
3520 RIU_WriteByte(0x12860L, 0xFA);
3521 RIU_WriteByte(0x12861L, 0x24);
3522 }
3523
3524 // For API
msVifHandler(BOOL bVifDbbAcq)3525 void msVifHandler(BOOL bVifDbbAcq)
3526 {
3527 BYTE afc_foe;
3528 BYTE mean16;
3529 BYTE agc_pga2;
3530 WORD agc_vga;
3531 BYTE dagc1_var;
3532 BYTE kpki_gear;
3533 static BYTE crjtr_det_cnt = 0;
3534 static WORD kpki_cnt_idx = 0;
3535
3536 if (!_hal_VIF.bBaseAddrInitialized) return ;
3537
3538 MsOS_DelayTask(3);
3539
3540 switch(g_ucVifStatusStep)
3541 {
3542 case VIF_START:
3543 case VIF_AGC_STATUS:
3544 g_VifCrKpKiAdjLoopCnt = 0;
3545 kpki_cnt_idx = 0;
3546 crjtr_det_cnt = 0;
3547 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3548 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3549 agc_vga = msRead2Bytes(AGC_VGA);
3550 if (g_bCheckModulationType == 0)
3551 {
3552 if (((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3553 {
3554 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3555 msWriteByte(AGC_LINE_CNT_H, 0x00);
3556
3557 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1; kp2,ki2,kf2
3558 msWriteBit(CR_K_SEL2, 0, _BIT0);
3559
3560 g_ucVifStatusStep = VIF_AFC_STATUS;
3561 }
3562 }
3563 else
3564 {
3565 if (((mean16 < AGC_MEAN16_UPBOUND_SECAM) && (mean16 > AGC_MEAN16_LOWBOUND_SECAM)) || (agc_pga2 == 0x1F) || (agc_vga == VIFInitialIn_inst.VifVgaMinimum))
3566 {
3567 msWriteByte(AGC_LINE_CNT_L, 0x04); // AGC line cnt = 4
3568 msWriteByte(AGC_LINE_CNT_H, 0x00);
3569
3570 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3571
3572 g_ucVifStatusStep = VIF_AFC_STATUS;
3573 }
3574 }
3575
3576 // for No-SAW use
3577 if((VIFInitialIn_inst.VifSawArch == NO_SAW)&&(g_bCheckModulationType == 0))
3578 {
3579 if(bVifDbbAcq == 0)
3580 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative);
3581 else
3582 msWriteByte(AGC_REF, VIFInitialIn_inst.VifChanelScanAGCREF);
3583 }
3584
3585 break;
3586
3587 case VIF_AFC_STATUS:
3588 if (_bit0_(msReadByte(CR_LOCK_STATUS)))
3589 {
3590 // DAGC
3591 if (g_bCheckModulationType == 1)
3592 {
3593 msWriteBit(DAGC1_OREN, 1, _BIT6); // DAGC1 gain_overwrite = 1
3594 msWriteBit(DAGC2_OREN, 1, _BIT6); // DAGC2 gain_overwrite = 1
3595 }
3596 g_ucVifStatusStep = VIF_AFC_STATUS2;
3597 }
3598 else
3599 {
3600 msWriteBit(CR_K_SEL, 0, _BIT6); // kp1,ki1,kf1,kp2,ki2,kf2
3601 HAL_VIF_Delay1us(1);
3602 msWriteBit(CR_NCO_FF_RSTZ, 0, _BIT2); // reset NCO_FF
3603 msWriteBit(CR_LF_FF_RSTZ, 0, _BIT5); // reset AFC integral part
3604 HAL_VIF_Delay1us(5);
3605 msWriteBit(CR_NCO_FF_RSTZ, 1, _BIT2);
3606 HAL_VIF_Delay1us(1);
3607 msWriteBit(CR_LF_FF_RSTZ, 1, _BIT5);
3608 }
3609 break;
3610
3611 case VIF_AFC_STATUS2:
3612 afc_foe = msReadByte(CR_FOE); // AFC_FOE
3613 if ((afc_foe <= 0x04) || (afc_foe >= 0xFC)) // |AFC_FOE|<=4
3614 {
3615 // AGC
3616 msWriteByte(AGC_VGA_THR, VIFInitialIn_inst.GainDistributionThr); // vga threshold
3617 msWriteByte(AGC_VGA_THR+1, VIFInitialIn_inst.GainDistributionThr>>8);
3618 msWriteByte(AGC_VGA_BASE, VIFInitialIn_inst.VifAgcVgaBase); // vga base
3619 if (bVifDbbAcq == 0) // 0: not channel scan; 1: channel scan
3620 {
3621 // AGC
3622 if (bEnableUsrSteadyAgcK)
3623 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3624 else
3625 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2);// k
3626
3627 msWriteByte(AGC_LINE_CNT_L, 0x10); // AGC line cnt = 16
3628 msWriteByte(AGC_LINE_CNT_H, 0x00);
3629
3630 // CR
3631 msWriteRegsTbl((MS_VIF_REG_TYPE *)VIF_CR_IIR_LPF2); // IIR LPF2 coefficients
3632
3633 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3634 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3635 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3636 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3637
3638 msWriteByteMask(CR_KF_SW, 0x00, 0x0F); // kf software mode
3639 msWriteBit(CR_K_SEL, 1, _BIT6); // kp,ki,kf
3640
3641 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3642 {
3643 //if(g_VifHWKpKiFlag == 1)
3644 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3645 {
3646 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3647 kpki_gear = msReadByte(CR_KPKI_GEAR) & 0x30;
3648 }
3649 }
3650
3651 msWriteByte(CR_PD_ERR_MAX_L, VIFInitialIn_inst.VifCrPdErrMax); // CR pd error max
3652 msWriteByteMask(CR_PD_ERR_MAX_H, VIFInitialIn_inst.VifCrPdErrMax>>8, 0x3F);
3653 msWriteByte(CR_UNLOCK_NUM, VIFInitialIn_inst.VifCrUnlockNum); // CR unlock num
3654 msWriteByte(CR_UNLOCK_NUM+1, VIFInitialIn_inst.VifCrUnlockNum>>8);
3655 msWriteByteMask(CR_UNLOCK_NUM+2, VIFInitialIn_inst.VifCrUnlockNum>>16, 0x0F);
3656
3657 // over modulation
3658 if ((VIFInitialIn_inst.VifOverModulation == 1) && (g_bCheckModulationType == 0))
3659 {
3660 msWriteBit(VNCO_INV_OREN, 1, _BIT1);
3661 msWriteBit(VNCO_INV_OV, 0, _BIT2);
3662 }
3663
3664 g_ucVifStatusStep = VIF_STEADY_STATUS;
3665 }
3666 }
3667
3668 if (!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3669 msVifInitial();
3670 break;
3671
3672 case VIF_STEADY_STATUS:
3673
3674 // for SAWless, ADC back-off for +20dB ACI
3675 if(VIFInitialIn_inst.VifSawArch == NO_SAW)
3676 {
3677 if(VIFInitialIn_inst.VifSeriousACIDetect)
3678 msVifSeriousACIDetection();
3679 }
3680
3681 // Dynamic TOP adjust for strong signal
3682 if (VIFInitialIn_inst.VifDynamicTopAdjust)
3683 {
3684 msVifDynamicTopAdjust();
3685 }
3686
3687 // AM hum detector
3688 agc_vga = msRead2Bytes(AGC_VGA);
3689 dagc1_var = msReadByte(DAGC1_VAR+1);
3690 if ((VIFInitialIn_inst.VifAmHumDetection == 1) && ((agc_vga > VIFInitialIn_inst.VifVgaMinimum) || (agc_vga < (VIFInitialIn_inst.GainDistributionThr - 0x1000))))
3691 {
3692 if ((dagc1_var >= 0x18) && (g_bCheckModulationType == 0))
3693 {
3694 // 20% AM modulation
3695 msWriteByte(AGC_REF, 0x43); // AGC ref
3696 }
3697 else if ((dagc1_var <= 0x05) && (g_bCheckModulationType == 0))
3698 {
3699 // 10% AM modulation
3700 msWriteByte(AGC_REF, VIFInitialIn_inst.VifAgcRefNegative); // AGC ref
3701 }
3702 }
3703
3704 // AGC
3705 mean16 = (BYTE)(msRead2Bytes(AGC_MEAN16)>>1); // AGC mean16
3706 if (g_bCheckModulationType == 0)
3707 {
3708 if ((mean16 < AGC_MEAN16_UPBOUND) && (mean16 > AGC_MEAN16_LOWBOUND))
3709 {
3710 if (bEnableUsrSteadyAgcK)
3711 msWriteByteMask(AGC_K, u8UsrSteadyAgcK, _BIT0|_BIT1|_BIT2);// k
3712 else
3713 msWriteByteMask(AGC_K, 0x04, _BIT0|_BIT1|_BIT2); // k
3714 }
3715 else
3716 {
3717 if (bEnableUsrNonSteadyAgcK)
3718 msWriteByteMask(AGC_K, u8UsrNonSteadyAgcK, _BIT0|_BIT1|_BIT2); // k
3719 else
3720 {
3721 if (VIFInitialIn_inst.VifTunerType == 1)
3722 msWriteByteMask(AGC_K, 0x03, _BIT0|_BIT1|_BIT2); // k
3723 else
3724 msWriteByteMask(AGC_K, 0x02, _BIT0|_BIT1|_BIT2); // k
3725 }
3726 }
3727 }
3728
3729 // CR monitor
3730 agc_pga2 = msReadByte(AGC_PGA2C) & 0x1F;
3731 if ((agc_pga2 >= 0x0F) && (VIFInitialIn_inst.VifCrPdModeSel == 1))
3732 {
3733 msWriteByteMask(CR_KP_SW, (VIFInitialIn_inst.VifCrKp)+0x01, 0x0F); // kp software mode
3734 msWriteByteMask(CR_KI_SW, (VIFInitialIn_inst.VifCrKi<<4)+0x10, 0xF0); // ki software mode
3735 }
3736 else
3737 {
3738 if (VIFInitialIn_inst.VifCrKpKiAdjust)
3739 {
3740 //if(g_VifHWKpKiFlag == 1)
3741 if((msReadByte(HALVIFDBG2_BIT) & 0x01) != 0)
3742 {
3743 g_VifCrKp = VIFInitialIn_inst.VifCrKp;
3744 g_VifCrKi = VIFInitialIn_inst.VifCrKi;
3745 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3746 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3747
3748 msWriteBit(KPKI_ADJ_EN, 1, _BIT0); // real HW_KPKI_enable
3749 kpki_gear = msReadByte(CR_KPKI_GEAR) & 0x30;
3750
3751 if(kpki_gear == 0)
3752 kpki_cnt_idx = 0;
3753 else
3754 {
3755 if(kpki_cnt_idx == 7000)
3756 {
3757 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1); // for > 150% overmodulation
3758 kpki_cnt_idx = 0;
3759 }
3760 kpki_cnt_idx++;
3761 }
3762 }
3763 else
3764 {
3765 msWriteBit(KPKI_ADJ_EN, 0, _BIT0); // real HW_KPKI_disable
3766
3767 if(crjtr_det_cnt < 6)
3768 {
3769 msVifCrKpKiAutoAdjust(VIFInitialIn_inst.VifCrKpKiAdjustThr1, VIFInitialIn_inst.VifCrKpKiAdjustThr2);
3770
3771 if(g_VifCrKpKiAdjLoopCnt == 0)
3772 {
3773 crjtr_det_cnt++;
3774 msWriteByteMask(CR_KP_SW, g_VifCrKp, 0x0F); // Ki Kp software mode
3775 msWriteByteMask(CR_KI_SW, g_VifCrKi << 4, 0xF0);
3776
3777 if(g_VifCrKp != VIFInitialIn_inst.VifCrKp) // If carrier drift
3778 msWriteBit(CR_PD_IMAG_INV, 0, _BIT1);
3779 else
3780 msWriteBit(CR_PD_IMAG_INV, 1, _BIT1);
3781 }
3782 }
3783 }
3784 }
3785 else
3786 {
3787 msWriteByteMask(CR_KP_SW, VIFInitialIn_inst.VifCrKp, 0x0F); // kp software mode
3788 msWriteByteMask(CR_KI_SW, VIFInitialIn_inst.VifCrKi<<4, 0xF0); // ki software mode
3789 }
3790 }
3791
3792 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3793 {
3794 HAL_VIF_Delay1ms(50); // for Fluke 54200 50dBuV <-> 51dBuV switch
3795 if(!(_bit0_(msReadByte(CR_LOCK_STATUS))))
3796 {
3797 // for debug
3798 if (msReadByte(HALVIFDBG_BIT) & 0x08)
3799 {
3800 printf("VIF msVifInitial!!!");
3801 }
3802 msVifInitial();
3803 }
3804 }
3805
3806 // for debug
3807 if (msReadByte(HALVIFDBG_BIT) & 0x40)
3808 {
3809 if (VIFInitialIn_inst.VifCrKpKiAdjust==1 )
3810 {
3811 VIFInitialIn_inst.VifCrKpKiAdjust=0;
3812 }
3813 printf("\r\n Disable VIF KpKi auto adjust");
3814 }
3815
3816 // for debug
3817 if ((msReadByte(HALVIFDBG_BIT) & 0x80) || (VIFInitialIn_inst.VifReserve & _BIT3))
3818 {
3819 U8 ir_rate;
3820
3821 // IR Rate
3822 ir_rate = msReadByte(IF_RATE);
3823 if (ir_rate==0x49)
3824 printf("\r\n IF_FREQ_3395 IF_FREQ_3890");
3825 else if (ir_rate==0xE3)
3826 printf("\r\n IF_FREQ_3800");
3827 else if (ir_rate==0x8E)
3828 printf("\r\n IF_FREQ_3950");
3829 else if (ir_rate==0xAA)
3830 printf("\r\n IF_FREQ_4575");
3831 else if (ir_rate==0xC7)
3832 printf("\r\n IF_FREQ_5875");
3833 else
3834 printf("\r\n unknown");
3835
3836 printf(" IR_RATE=0x%x ", ir_rate);
3837
3838 // sound system
3839 if (g_ucVifSoundSystemType==0)
3840 printf("\r\n VIF_SOUND_B");
3841 else if (g_ucVifSoundSystemType==1)
3842 printf("\r\n VIF_SOUND_B_NICAM");
3843 else if (g_ucVifSoundSystemType==2)
3844 printf("\r\n VIF_SOUND_GH");
3845 else if (g_ucVifSoundSystemType==3)
3846 printf("\r\n VIF_SOUND_GH_NICAM");
3847 else if (g_ucVifSoundSystemType==4)
3848 printf("\r\n VIF_SOUND_I");
3849 else if (g_ucVifSoundSystemType==5)
3850 printf("\r\n VIF_SOUND_DK1");
3851 else if (g_ucVifSoundSystemType==6)
3852 printf("\r\n VIF_SOUND_DK2");
3853 else if (g_ucVifSoundSystemType==7)
3854 printf("\r\n VIF_SOUND_DK3");
3855 else if (g_ucVifSoundSystemType==8)
3856 printf("\r\n VIF_SOUND_DK_NICAM");
3857 else if (g_ucVifSoundSystemType==9)
3858 printf("\r\n VIF_SOUND_L");
3859 else if (g_ucVifSoundSystemType==10)
3860 printf("\r\n VIF_SOUND_LL");
3861 else if (g_ucVifSoundSystemType==11)
3862 printf("\r\n VIF_SOUND_MN");
3863 else
3864 printf("\r\n unknown");
3865
3866 printf(" sound system=%d", (BYTE)g_ucVifSoundSystemType);
3867
3868 // freq band select
3869 printf("\r\n band=%d", (BYTE)VIFInitialIn_inst.VifFreqBand);
3870 }
3871 break;
3872
3873 default:
3874 g_ucVifStatusStep++;
3875 break;
3876 }
3877
3878 if ((g_ucVifSoundSystemType == VIF_SOUND_L) || (g_ucVifSoundSystemType == VIF_SOUND_LL))
3879 {
3880 if (g_bCheckModulationType == 0)
3881 msVifInitial();
3882 if ((g_ucVifSoundSystemType == VIF_SOUND_L) && (g_bCheckIFFreq == 1))
3883 msVifInitial();
3884 if ((g_ucVifSoundSystemType == VIF_SOUND_LL) && (g_bCheckIFFreq == 0))
3885 msVifInitial();
3886 }
3887 else
3888 {
3889 if (g_bCheckModulationType == 1)
3890 msVifInitial();
3891 }
3892 }
3893
msVifSeriousACIDetection(void)3894 void msVifSeriousACIDetection(void)
3895 {
3896 BYTE AGC_Ref, AGC_Mean256, temp;
3897 BYTE PGA = 0, ADC_Index = 0, ADC_Underflow_Index = 0, ADC_Overflow_Index = 0;
3898 WORD VGA = 0;
3899
3900 temp = msReadByte(AGC_REF);
3901 AGC_Ref =(temp << 1);
3902 AGC_Mean256 = msReadByte(AGC_MEAN256);
3903
3904 if(SeriousACI_Index == 1)
3905 {
3906 VGA = msRead2Bytes(AGC_VGA);
3907 PGA = msReadByte(AGC_PGA2C);
3908 ADC_Index = RIU_ReadByte(0x12870L);
3909 ADC_Underflow_Index = ADC_Index & 0x02;
3910 ADC_Overflow_Index = ADC_Index & 0x04;
3911
3912 if((ADC_Underflow_Index == 0x02 ||ADC_Overflow_Index == 0x04)&&(VGA == 0x7000)&&(PGA == 0x1F)&&(AGC_Change_Index == 0)
3913 &&(AGC_Ref - AGC_Mean256 > 5))
3914 {
3915 msWriteByte(AGC_REF, VIFInitialIn_inst.VifADCOverflowAGCREF);
3916 msWriteBit(BYPASS_SOS21, 1 , _BIT2);
3917 msWriteBit(BYPASS_SOS22, 1 , _BIT3);
3918 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE, 0x00);
3919 msWriteByte(CLAMPGAIN_GAIN_OVERWRITE+1, 0x04);
3920 AGC_Change_Index = 1;
3921 }
3922 SeriousACI_Index = 0;
3923 }
3924 SeriousACI_Index = SeriousACI_Index + 1;
3925 }
3926
msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1,BYTE VifCrKpKiAdjustThr2)3927 void msVifCrKpKiAutoAdjust(BYTE VifCrKpKiAdjustThr1, BYTE VifCrKpKiAdjustThr2)
3928 {
3929 MS_S16 CrJtrMax, CrJtrMin;
3930 static DWORD CrJtrDelta;
3931
3932 HALVIFDBG(printf("\r\msVifCrKpKiAutoAdjust()"));
3933
3934 msWriteBit(CR_STATUS_LATCH_EN, 1, _BIT4); // latch CR loop-filter
3935
3936 msWriteByteMask(CR_JTR_SEL, 0, _BIT3|_BIT2|_BIT1|_BIT0); // 0: max
3937 CrJtrMax = msRead2Bytes(CR_JTR_OUT);
3938
3939 msWriteByteMask(CR_JTR_SEL, _BIT0, _BIT3|_BIT2|_BIT1|_BIT0); // 1: min
3940 CrJtrMin = msRead2Bytes(CR_JTR_OUT);
3941
3942 msWriteBit(CR_STATUS_LATCH_EN, 0, _BIT4); // un-latch CR loop-filter status
3943
3944 if(g_VifCrKpKiAdjLoopCnt == 0) // reset delta value
3945 CrJtrDelta = 0;
3946
3947 CrJtrDelta += (DWORD)(CrJtrMax - CrJtrMin);
3948
3949 if (++g_VifCrKpKiAdjLoopCnt == 32) // 32 samples
3950 {
3951 CrJtrDelta = CrJtrDelta >> 5; // divided by 32
3952 CrJtrDelta = CrJtrDelta >> 7;
3953 if (g_VifCrKp >= VIFInitialIn_inst.VifCrKp)
3954 {
3955 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3956 {
3957 g_VifCrKp -= 0x02;
3958 g_VifCrKi -= 0x02;
3959 }
3960 else if ((CrJtrDelta < VifCrKpKiAdjustThr2) && (CrJtrDelta >= VifCrKpKiAdjustThr1))
3961 {
3962 g_VifCrKp -= 0x01;
3963 g_VifCrKi -= 0x01;
3964 }
3965 }
3966 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 1)
3967 {
3968 if (CrJtrDelta >= VifCrKpKiAdjustThr2)
3969 {
3970 g_VifCrKp -= 0x01;
3971 g_VifCrKi -= 0x01;
3972 }
3973 else if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3974 {
3975 g_VifCrKp += 0x01 ;
3976 g_VifCrKi += 0x01;
3977 }
3978 }
3979 else if (g_VifCrKp == VIFInitialIn_inst.VifCrKp - 2)
3980 {
3981 if (CrJtrDelta < VifCrKpKiAdjustThr1 - 1)
3982 {
3983 g_VifCrKp += 0x02;
3984 g_VifCrKi += 0x02;
3985 }
3986 else if (CrJtrDelta < VifCrKpKiAdjustThr2 - 3)
3987 {
3988 g_VifCrKp += 0x01;
3989 g_VifCrKi += 0x01;
3990 }
3991 }
3992
3993 g_VifCrKpKiAdjLoopCnt = 0;
3994 if (msReadByte(HALVIFDBG_BIT) & 0x20)
3995 {
3996 printf("\r\ng_ucVifStatusStep = %d", g_ucVifStatusStep);
3997 printf("\nKi/Kp = %x%x", g_VifCrKi, g_VifCrKp);
3998 printf("\nCrJtrMax = %x", CrJtrMax >> 7);
3999 printf("\nCrJtrMin = %x", CrJtrMin >> 7);
4000 printf("\r\nCrJtrDelta = %x", (WORD)((CrJtrDelta & 0xFFFF0000) >> 16));
4001 printf("%x\r\n",(WORD)(CrJtrDelta & 0x0000FFFF));
4002 }
4003 }
4004 }
4005
msVifReadCRFOE(void)4006 U8 msVifReadCRFOE(void)
4007 {
4008 HALVIFDBG(printf("\r\nmsVifReadCRFOE()"));
4009
4010 if (!_hal_VIF.bBaseAddrInitialized) return 0;
4011
4012 return msReadByte(CR_FOE);
4013 }
4014
msVifReadLockStatus(void)4015 U8 msVifReadLockStatus(void)
4016 {
4017 HALVIFDBG(printf("\r\nmsVifReadLockStatus()"));
4018
4019 if (!_hal_VIF.bBaseAddrInitialized) return 0;
4020
4021 return msReadByte(CR_LOCK_STATUS);
4022 }
4023
msVifLoadEQCoeff(BYTE VifSoundStandard)4024 void msVifLoadEQCoeff(BYTE VifSoundStandard)
4025 {
4026 U8 u8index;
4027
4028 HALVIFDBG(printf("\r\n msVifLoadEQCoeff()"));
4029
4030 // set coef
4031 RIU_WriteByte(0x120A0L, 0x01); // VIF use DVB SRAM and FIR
4032 RIU_WriteByteMask(0x120A2L, 0x01, 0x0F); // reg_vif_fir_coef_ctrl
4033 RIU_WriteByteMask(0x120A2L, 0x03, 0x0F); // reg_vif_fir_coef_ctrl
4034 msWriteBit(BYPASS_EQFIR, 1, _BIT0); // EQ BYPASS
4035
4036 if(VIF_IS_EQ_IIR == 0)
4037 {
4038 // EQ FIR
4039 RIU_WriteRegBit(0x120A0L, 0, _BIT4); // 0:FIR, 1:IIR
4040
4041 if(VifSoundStandard == VIF_SOUND_MN)
4042 {
4043 for(u8index = 0; u8index < 56; ++u8index)
4044 {
4045 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]+0x8000);
4046 RIU_Write2Byte(0x120A4, VIF_NTSC_EQ_CO_A_REJ[u8index]);
4047 }
4048 }
4049 else
4050 {
4051 for(u8index = 0; u8index < 56; ++u8index)
4052 {
4053 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]+0x8000);
4054 RIU_Write2Byte(0x120A4, VIF_PAL_EQ_CO_A_REJ[u8index]);
4055 }
4056 }
4057 }
4058 else
4059 {
4060 // EQ IIR
4061 RIU_WriteRegBit(0x120A0L, 1, _BIT4); // 0:FIR, 1:IIR
4062
4063 switch(VifSoundStandard)
4064 {
4065 case VIF_SOUND_B:
4066 case VIF_SOUND_GH:
4067 for(u8index = 0; u8index < 18; ++u8index)
4068 {
4069 RIU_Write2Byte(0x120A4, VIF_BG_EQ_IIR_BANDSTOP[u8index]+0x8000);
4070 RIU_Write2Byte(0x120A4, VIF_BG_EQ_IIR_BANDSTOP[u8index]);
4071 }
4072 break;
4073
4074 case VIF_SOUND_B_NICAM:
4075 case VIF_SOUND_GH_NICAM:
4076 for(u8index = 0; u8index < 18; ++u8index)
4077 {
4078 RIU_Write2Byte(0x120A4, VIF_BG_NICAM_EQ_IIR_NOTCH[u8index]+0x8000);
4079 RIU_Write2Byte(0x120A4, VIF_BG_NICAM_EQ_IIR_NOTCH[u8index]);
4080 }
4081 break;
4082
4083 case VIF_SOUND_I:
4084 for(u8index = 0; u8index < 18; ++u8index)
4085 {
4086 RIU_Write2Byte(0x120A4, VIF_I_EQ_IIR_NOTCH[u8index]+0x8000);
4087 RIU_Write2Byte(0x120A4, VIF_I_EQ_IIR_NOTCH[u8index]);
4088 }
4089 break;
4090
4091 case VIF_SOUND_DK1:
4092 for(u8index = 0; u8index < 18; ++u8index)
4093 {
4094 RIU_Write2Byte(0x120A4, VIF_DK1_EQ_IIR_NOTCH[u8index]+0x8000);
4095 RIU_Write2Byte(0x120A4, VIF_DK1_EQ_IIR_NOTCH[u8index]);
4096 }
4097 break;
4098
4099 case VIF_SOUND_DK2:
4100 for(u8index = 0; u8index < 18; ++u8index)
4101 {
4102 RIU_Write2Byte(0x120A4, VIF_DK2_EQ_IIR_NOTCH[u8index]+0x8000);
4103 RIU_Write2Byte(0x120A4, VIF_DK2_EQ_IIR_NOTCH[u8index]);
4104 }
4105 break;
4106
4107 case VIF_SOUND_DK3:
4108 for(u8index = 0; u8index < 18; ++u8index)
4109 {
4110 RIU_Write2Byte(0x120A4, VIF_DK3_EQ_IIR_NOTCH[u8index]+0x8000);
4111 RIU_Write2Byte(0x120A4, VIF_DK3_EQ_IIR_NOTCH[u8index]);
4112 }
4113 break;
4114
4115 case VIF_SOUND_DK_NICAM:
4116 for(u8index = 0; u8index < 18; ++u8index)
4117 {
4118 RIU_Write2Byte(0x120A4, VIF_DK_NICAM_EQ_IIR_NOTCH[u8index]+0x8000);
4119 RIU_Write2Byte(0x120A4, VIF_DK_NICAM_EQ_IIR_NOTCH[u8index]);
4120 }
4121 break;
4122
4123 case VIF_SOUND_MN:
4124 for(u8index = 0; u8index < 18; ++u8index)
4125 {
4126 RIU_Write2Byte(0x120A4, VIF_NTSC_MN_EQ_IIR_NOTCH[u8index]+0x8000);
4127 RIU_Write2Byte(0x120A4, VIF_NTSC_MN_EQ_IIR_NOTCH[u8index]);
4128 }
4129 break;
4130
4131 case VIF_SOUND_L:
4132 case VIF_SOUND_LL:
4133 //audio carrier 1 and 2 are at the same position as DK NICAM
4134 for(u8index = 0; u8index < 18; ++u8index)
4135 {
4136 RIU_Write2Byte(0x120A4, VIF_DK_NICAM_EQ_IIR_NOTCH[u8index]+0x8000);
4137 RIU_Write2Byte(0x120A4, VIF_DK_NICAM_EQ_IIR_NOTCH[u8index]);
4138 }
4139 break;
4140
4141 case VIF_SOUND_NUMS:
4142 default:
4143 break;
4144 }
4145 }
4146 msWriteBit(BYPASS_EQFIR , 0 , _BIT0); // EQ not BYPASS
4147 }
4148
msVifShiftClk(BYTE VifShiftClk)4149 void msVifShiftClk(BYTE VifShiftClk)
4150 {
4151 if(VIF_IS_ADC_48MHz == 0)
4152 {
4153 if (VifShiftClk == 1)
4154 {
4155 //g_VifShiftClk = 1; // 0x1121_D3
4156 msWriteByte(VIF_RF_RESERVED_1+1, 0x01);
4157
4158 msWriteByte(0x12866L, 0x00);//loop divider
4159 msWriteByte(0x12867L, 0x23);
4160 if (VIFInitialIn_inst.VifTunerType == 0)
4161 {
4162 // move to clk 42 Mhz
4163 msWriteByte(CR_RATE, 0x6D); // cr_rate for 15 MHz
4164 msWriteByte(CR_RATE+1, 0xDB);
4165 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
4166 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
4167
4168 // move to clk 140 Mhz
4169 msWriteByte(IF_RATE, 0xA8); // IF rate for 23 MHz
4170 msWriteByte(IF_RATE+1, 0x83);
4171 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
4172 }
4173 }
4174 else if(VifShiftClk == 2)
4175 {
4176 //g_VifShiftClk = 2; // 0x1121_D3
4177 msWriteByte(VIF_RF_RESERVED_1+1, 0x02);
4178
4179 msWriteByte(0x12866L, 0x00);//loop divider
4180 msWriteByte(0x12867L, 0x25);
4181 if (VIFInitialIn_inst.VifTunerType == 0)
4182 {
4183 // move to clk 44.4 Mhz
4184 msWriteByte(CR_RATE, 0x22); // cr_rate for 15 MHz
4185 msWriteByte(CR_RATE+1, 0x9F);
4186 msWriteByteMask(CR_RATE+2, 0x15, 0x1F);
4187 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
4188
4189 // move to clk 148 Mhz
4190 msWriteByte(IF_RATE, 0x29); // IF rate for 23 MHz
4191 msWriteByte(IF_RATE+1, 0xF2);
4192 msWriteByteMask(IF_RATE+2, 0x09, 0x3F);
4193 }
4194 }
4195 else
4196 {
4197 //g_VifShiftClk = 0; // 0x1121_D3
4198 msWriteByte(VIF_RF_RESERVED_1+1, 0x00);
4199
4200 msWriteByte(0x12866L, 0x00);//loop divider
4201 msWriteByte(0x12867L, 0x24);
4202 if (VIFInitialIn_inst.VifTunerType == 0)
4203 {
4204 // move to clk 43.2 Mhz
4205 msWriteByte(CR_RATE, 0xE3); // cr_rate for 15 MHz
4206 msWriteByte(CR_RATE+1, 0x38);
4207 msWriteByteMask(CR_RATE+2, 0x16, 0x1F);
4208 msWriteBit(CR_RATE_INV, 0, _BIT0); // cr_rate not invert
4209
4210 // move to clk 142 Mhz
4211 msWriteByte(IF_RATE, 0xE3); // IF rate for 23 MHz
4212 msWriteByte(IF_RATE+1, 0x38);
4213 msWriteByteMask(IF_RATE+2, 0x0A, 0x3F);
4214 }
4215 }
4216 }
4217 }
4218
HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)4219 void HAL_VIF_BypassDBBAudioFilter(BOOL bEnable)
4220 {
4221 HALVIFDBG(printf("HAL_VIF_BypassDBBAudioFilter() bEnableq=%d\n",bEnable));
4222 msWriteBit(A_DAGC_SEL, (!bEnable), _BIT7); // 0: input from a_sos; 1: input from a_lpf_up
4223 }
4224
HAL_VIF_GetInputLevelIndicator(void)4225 BOOL HAL_VIF_GetInputLevelIndicator(void)
4226 {
4227 BYTE ref, mean256, diff;
4228
4229 HALVIFDBG(printf("\r\nHAL_VIF_GetInputLevelIndicator()"));
4230
4231 ref = msReadByte(AGC_REF); // AGC ref
4232 mean256 = (BYTE)(msRead2Bytes(AGC_MEAN256)>>1); // AGC mean256
4233
4234 if (g_bCheckModulationType == 0)
4235 diff = 0x15; // negative modulation
4236 else
4237 diff = 0x0A; // positive modulation
4238
4239 if (mean256 >= (ref-diff))
4240 return 1;
4241 else
4242 return 0;
4243 }
4244
HAL_VIF_GetCrPDInverse(void)4245 U8 HAL_VIF_GetCrPDInverse(void)
4246 {
4247 HALVIFDBG(printf("HAL_VIF_GetCrPDInverse() %d \n", 0));
4248 if ((HAL_VIF_ReadByte(CR_PD_IMAG_INV) & _BIT1)!=0)
4249 return 1;
4250 else
4251 return 0;
4252 }
4253
HAL_VIF_SetCrPDInverse(BOOL bEnable)4254 void HAL_VIF_SetCrPDInverse(BOOL bEnable)
4255 {
4256 HALVIFDBG(printf("HAL_VIF_SetCrPDInverse() bEnableq=%d\n",bEnable));
4257 msWriteBit(CR_PD_IMAG_INV, (bEnable), _BIT1); // 0: disable; 1: enable
4258 }
4259
4260 #endif //_HALVIF_C_
4261
4262