Lines Matching refs:RIU_WriteRegBit
142 #define RIU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ macro
6280 RIU_WriteRegBit(VD_MCU_RST, bEnable, BIT(0)); //halt VD MCU first in HAL_AVD_VDMCU_SetFreeze()
6498 RIU_WriteRegBit(VD_MCU_SRAM_EN, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6504 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6537 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, DISABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6543 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6584 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6585 RIU_WriteRegBit(BK_AFEC_14, DISABLE, BIT(7)); in HAL_AVD_RegInit()
6598 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6804 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6806 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6845 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
6855 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6856 RIU_WriteRegBit (L_BK_CLKGEN0(0x21), DISABLE, BIT(0)); // CLK_VDMCU, 0:Enable 1:Disable in HAL_AVD_AFEC_SetClock()
6857 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6861 RIU_WriteRegBit (L_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD2X in HAL_AVD_AFEC_SetClock()
6862 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
6879 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), DISABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6881 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6882 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6902 RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4)); in HAL_AVD_AFEC_SetClockSource()
6962 RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5)); in HAL_AVD_AFEC_SetPatchFlag()
7021 RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6] in HAL_AVD_AFEC_SetInput()
7035 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7040 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7055 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7060 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7077 RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7082 RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C in HAL_AVD_AFEC_SetInput()
7096 RIU_WriteRegBit (BK_COMB_10, DISABLE, BIT(7)); // <- SET COMB in HAL_AVD_AFEC_SetInput()
7101 RIU_WriteRegBit( BK_AFEC_1F, DISABLE, BIT(7)); // disable clamp C in HAL_AVD_AFEC_SetInput()
7115 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD in HAL_AVD_AFEC_SetInput()
7135 RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7139 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7144 RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7145 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7146 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move … in HAL_AVD_AFEC_SetInput()
7147 RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware in HAL_AVD_AFEC_SetInput()
7154 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7155 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7156 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7157 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7166 RIU_WriteRegBit(BK_AFEC_8F,DISABLE,BIT(5)); in HAL_AVD_AFEC_SetInput()
7170 RIU_WriteRegBit(BK_AFEC_CF,DISABLE,BIT(7)); in HAL_AVD_AFEC_SetInput()
7171 RIU_WriteRegBit(H_BK_CHIPTOP(0x13), DISABLE, BIT(8)); //20090611EL in HAL_AVD_AFEC_SetInput()
7172 …RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move… in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteRegBit(BK_AFEC_40,DISABLE,BIT(7)); // disable VIF in hardware in HAL_AVD_AFEC_SetInput()
7260 RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7))); in HAL_AVD_AFEC_SetHTotal()
7278 RIU_WriteRegBit(BK_AFEC_A0, DISABLE, BIT(7)); in HAL_AVD_AFEC_SetHTotal()
7282 RIU_WriteRegBit(BK_COMB_50, DISABLE, BIT(0)); in HAL_AVD_AFEC_SetHTotal()
7317 RIU_WriteRegBit(BK_AFEC_55, bEnable, BIT(0)); in HAL_AVD_AFEC_Set656DCOffset()
7351 RIU_WriteRegBit( BK_AFEC_CE, bEnable, BIT(0)); in HAL_AVD_AFEC_EnableForceMode()
7402 RIU_WriteRegBit(BK_AFEC_67, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableCVBSLPF()
7403 RIU_WriteRegBit(BK_AFEC_CF, bEnable, BIT(2)); in HAL_AVD_AFEC_EnableCVBSLPF()
7444 RIU_WriteRegBit(BK_AFEC_D4, bEnable, BIT(4)); in HAL_AVD_AFEC_EnableVBIDPLSpeedup()
7463 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7465 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetMode()
7484 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7486 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetCoarseGain()
7505 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7507 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_AFEC_AGCSetFineGain()
7654 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); // BK_COMB_4C[7] COMB memory prote… in HAL_AVD_COMB_SetMemoryProtect()
7674 RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7675 RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7679 RIU_WriteRegBit(BK_COMB_EE, DISABLE, BIT(7)); in HAL_AVD_COMB_Set3dCombMid()
7680 RIU_WriteRegBit(BK_COMB_2D, DISABLE, BIT(4)); in HAL_AVD_COMB_Set3dCombMid()
7701 … RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7713 … RIU_WriteRegBit( BK_COMB_2D, DISABLE, BIT(4)); // T3 Transition Vertical line in channel change. in HAL_AVD_COMB_Set3dComb()
7940 RIU_WriteRegBit(BK_COMB_18, DISABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
7947 RIU_WriteRegBit(BK_COMB_C0, DISABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
7953 RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0)); in HAL_AVD_COMB_SetNonStandardHtotal()
7960 RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5)); in HAL_AVD_COMB_SetNonStandardHtotal()
8020 RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7)); in HAL_AVD_COMB_SetMemoryRequest()
8027 RIU_WriteRegBit(BK_COMB_4C, DISABLE, BIT(7)); in HAL_AVD_COMB_SetMemoryRequest()
8053 RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8057 RIU_WriteRegBit(BK_VBI_8D, DISABLE, BIT(6)); in HAL_AVD_VBI_SetTTSigDetSel()
8126 RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8128 RIU_WriteRegBit(BK_AFEC_55, DISABLE, BIT(2)); in HAL_AVD_SetPQFineTune()
8153 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()
8171 RIU_WriteRegBit(BK_AFEC_4E, bEnable, BIT(7)); in HAL_AVD_AFEC_BackPorchWindowPosition()