Searched refs:REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK (Results 1 – 13 of 13) sorted by relevance
257 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080335 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()336 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
391 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()392 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
352 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()353 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
399 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()400 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
400 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()401 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
409 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()410 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0 in HAL_TSO_Init()
203 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080 macro
204 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080 macro