Home
last modified time | relevance | path

Searched refs:REG_CLKGEN0_STC_CW_SEL (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c182 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
2117 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2131 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c183 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
2138 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2152 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c183 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
2119 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2133 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h69 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
H A DhalTSP.c2284 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2341 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2410 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c205 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
3082 u32value = REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
3100 u32value = REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2727 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2748 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2787 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
H A DregTSP.h75 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c199 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3388 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
3406 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c213 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3414 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
3432 u32value = ((u32EngId == 0) ? REG_CLKGEN0_STC_CW_SEL : REG_CLKGEN0_STC1_CW_SEL); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c215 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3396 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3410 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h76 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
H A DhalTSP.c3631 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3652 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3691 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h76 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3658 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3627 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3641 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3723 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3737 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL macro
3684 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3698 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro
H A DhalTSP.c3948 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3981 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
4030 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3800 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3821 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3860 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
H A DregTSP.h72 #define REG_CLKGEN0_STC_CW_SEL 0x0002 macro