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Searched refs:REG_CLKGEN0_DC0_SYTNTH (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2727 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2728 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2738 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
2739 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_STC_Init()
2740 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
2741 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
2742 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_STC_Init()
2743 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
2748 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2749 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
[all …]
H A DregTSP.h74 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DhalTSP.c2284 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2285 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
2313 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
2314 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_STC_Init()
2315 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
2316 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
2317 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_STC_Init()
2318 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
2341 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
2342 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
[all …]
H A DregTSP.h68 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c3631 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3632 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3642 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3643 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_STC_Init()
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3645 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3646 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_STC_Init()
3647 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3652 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3653 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
[all …]
H A DregTSP.h75 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3800 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3801 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3811 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3812 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_STC_Init()
3813 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3814 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3815 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_STC_Init()
3816 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3821 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3822 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
[all …]
H A DregTSP.h71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c3948 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3949 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
3965 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3966 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_STC_Init()
3967 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_STC_Init()
3968 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3969 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_STC_Init()
3970 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN); in HAL_TSP_STC_Init()
3981 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_STC_Init()
3982 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_STC_Init()
[all …]
H A DregTSP.h71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3652 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3653 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3654 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3658 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3661 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3664 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3665 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3666 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3627 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3635 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3636 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3637 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3641 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3647 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3648 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3649 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3723 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3731 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3732 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3733 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3737 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3740 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3743 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3744 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3745 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3684 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3692 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3693 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3694 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3698 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3701 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL; in HAL_TSP_SetSTCSynth()
3704 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3705 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
3706 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_EN; in HAL_TSP_SetSTCSynth()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c181 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
2117 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2125 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2126 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_Stc_ctrl()
2127 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2131 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c182 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
2138 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2146 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2147 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_Stc_ctrl()
2148 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2152 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c182 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
2119 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
2127 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2128 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_Stc_ctrl()
2129 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN); in HAL_TSP_Stc_ctrl()
2133 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c204 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
3083 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3094 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3095 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
3096 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3101 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c198 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3389 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3400 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3401 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
3402 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3407 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c212 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL macro
3415 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3426 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3427 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
3428 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~u32value; in HAL_TSP_Stc_ctrl()
3433 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= u32value; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c214 #define REG_CLKGEN0_DC0_SYTNTH 0x05UL macro
3396 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
3404 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3405 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3406 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_EN; in HAL_TSP_SetSTCSynth()
3410 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h75 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h71 #define REG_CLKGEN0_DC0_SYTNTH 0x05 macro