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Searched refs:REG_CLKGEN0_DC0_STC_CW_L (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c203 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3393 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_L : (REG_CLKGEN0_DC0_STC_CW_L+2)); in HAL_TSP_Stc_ctrl()
3425 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_L : (REG_CLKGEN0_DC0_STC_CW_L+2)); in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3419 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_L : (REG_CLKGEN0_DC0_STC_CW_L+2)); in HAL_TSP_Stc_ctrl()
3451 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_L : (REG_CLKGEN0_DC0_STC_CW_L+2)); in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h74 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
H A DhalTSP.c2295 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000; in HAL_TSP_STC_Init()
2363 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L); in HAL_TSP_GetSTCSynth()
2413 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c207 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
3087 u32value = REG_CLKGEN0_DC0_STC_CW_L; in HAL_TSP_Stc_ctrl()
3119 u32value = REG_CLKGEN0_DC0_STC_CW_L; in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2732 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000; in HAL_TSP_STC_Init()
2770 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L); in HAL_TSP_GetSTCSynth()
2790 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
H A DregTSP.h79 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c217 #define REG_CLKGEN0_DC0_STC_CW_L 0x06UL macro
3377 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3400 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c185 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
2121 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c186 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
2142 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c186 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
2123 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF); in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h80 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
H A DhalTSP.c3636 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000; in HAL_TSP_STC_Init()
3674 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L); in HAL_TSP_GetSTCSynth()
3694 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h80 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c222 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3625 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3648 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c222 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3608 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3631 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c222 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3704 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3727 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c222 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL macro
3665 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3688 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (MS_U16)(u32Sync & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro
H A DhalTSP.c3955 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000; in HAL_TSP_STC_Init()
4003 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L); in HAL_TSP_GetSTCSynth()
4033 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3805 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000; in HAL_TSP_STC_Init()
3843 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L); in HAL_TSP_GetSTCSynth()
3863 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF; in HAL_TSP_SetSTCSynth()
H A DregTSP.h77 #define REG_CLKGEN0_DC0_STC_CW_L 0x06 macro