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Searched refs:REG_CLKGEN0_DC0_STC_CW_H (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DhalTSP.c204 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3395 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_H : (REG_CLKGEN0_DC0_STC_CW_H+2)); in HAL_TSP_Stc_ctrl()
3427 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_H : (REG_CLKGEN0_DC0_STC_CW_H+2)); in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3421 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_H : (REG_CLKGEN0_DC0_STC_CW_H+2)); in HAL_TSP_Stc_ctrl()
3453 u32value = ((u32EngId == 0) ? REG_CLKGEN0_DC0_STC_CW_H : (REG_CLKGEN0_DC0_STC_CW_H+2)); in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h75 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
H A DhalTSP.c2296 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800; in HAL_TSP_STC_Init()
2364 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
2414 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DhalTSP.c208 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
3089 u32value = REG_CLKGEN0_DC0_STC_CW_H; in HAL_TSP_Stc_ctrl()
3121 u32value = REG_CLKGEN0_DC0_STC_CW_H; in HAL_TSP_GetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2733 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800; in HAL_TSP_STC_Init()
2771 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
2791 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
H A DregTSP.h80 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DhalTSP.c218 #define REG_CLKGEN0_DC0_STC_CW_H 0x07UL macro
3377 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3401 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c186 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
2122 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c187 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
2143 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c187 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
2124 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF; in HAL_TSP_Stc_ctrl()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DregTSP.h81 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
H A DhalTSP.c3637 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800; in HAL_TSP_STC_Init()
3675 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
3695 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h81 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3625 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3649 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3608 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3632 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3704 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3728 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DhalTSP.c223 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL macro
3665 … return (TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) | TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H)); in HAL_TSP_GetSTCSynth()
3689 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (MS_U16)((u32Sync >> 16UL) & 0xFFFF); in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DregTSP.h78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro
H A DhalTSP.c3956 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800; in HAL_TSP_STC_Init()
4004 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
4034 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c3806 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800; in HAL_TSP_STC_Init()
3844 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ; in HAL_TSP_GetSTCSynth()
3864 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16; in HAL_TSP_SetSTCSynth()
H A DregTSP.h78 #define REG_CLKGEN0_DC0_STC_CW_H 0x07 macro