Home
last modified time | relevance | path

Searched refs:REG_CLKGEN0_53_L (Results 1 – 17 of 17) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.h204 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
230 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
243 #define REG_CKG_ODCLK_MFT REG_CLKGEN0_53_L
255 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.h189 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
210 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
219 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.h189 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
210 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
219 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h211 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
246 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
259 #define REG_CKG_ODCLK_MFT REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h213 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
248 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
261 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h202 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
223 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
232 #define REG_CKG_BT656 REG_CLKGEN0_53_L
H A DhalPNL.c3156 W2BYTE(REG_CLKGEN0_53_L,0x00CC); //[13:8] clk_bt656 -> clk_lpll_buf in MHal_PNL_SetOSDCOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h213 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
248 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
261 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.h199 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
220 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
229 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.h199 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
220 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
229 #define REG_CKG_BT656 REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.h197 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
220 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
230 #define REG_CKG_BT656 REG_CLKGEN0_53_L
H A DhalPNL.c3554 W2BYTE(REG_CLKGEN0_53_L,0x00CC); //[13:8] clk_bt656 -> clk_lpll_buf in MHal_PNL_SetOSDCOutputType()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.h211 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
246 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
259 #define REG_CKG_ODCLK_MFT REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.h198 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.h198 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.h198 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.h198 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) macro
215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L