1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halPNL.h 98 /// @brief Panel Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_PNL_H_ 103 #define _HAL_PNL_H_ 104 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 #ifdef _HAL_PNL_C_ 110 #define HAL_PNL_INTERFACE 111 #else 112 #define HAL_PNL_INTERFACE extern 113 #endif 114 115 // Current platform is DAC out or not 116 #define IS_DAC_OUT TRUE 117 118 // version0: Not support TV chip as HDMITx 119 // version1: Maserati + Raptor 120 // version2: Maxim + inside HDMITx 121 #define HW_DESIGN_HDMITX_VER (0) 122 123 // XC register serpead define 124 #define XC_REGISTER_SPREAD 1 125 #define SUPPORT_FRC 0 126 #define PNL_SUPPORT_2P_MODE 0 127 128 //------------------------------------------------------------------------------------------------- 129 // Driver Capability 130 //------------------------------------------------------------------------------------------------- 131 #define GAMMA_10BIT BIT(0) ///< gamma value range up to 10 BIt 132 #define GAMMA_12BIT BIT(1) ///< gamma value range up to 12 BIT 133 134 #define GAMMA_8BIT_MAPPING BIT(0) ///< mapping GAMMA value to 256 sampline entries 135 #define GAMMA_10BIT_MAPPING BIT(1) ///< mapping GAMMA value to 1024 sampling entries 136 137 typedef struct 138 { 139 MS_U8 eSupportGammaType; ///< refer to HAL_PNL_GAMMA_TYPE 140 MS_U8 eSupportGammaMapMode; ///< refero to HAL_PNL_GAMMA_MAPPEING_MODE 141 } PNL_HalInfo; 142 143 #define SUPPORT_OVERDRIVE 1 144 #define GAMMA_TYPE (GAMMA_10BIT | GAMMA_12BIT) 145 #define GAMMA_MAPPING (GAMMA_8BIT_MAPPING) 146 #define SUPPORT_SYNC_FOR_DUAL_MODE TRUE //New feature after T7 147 #define ENABLE_MODE_PATCH 0 148 #define PNL_SUPPORT_DEVICE_NUM 2 149 150 // MIU Word (Bytes) 151 #define BYTE_PER_WORD (8) 152 153 #define SUPPORT_TCON FALSE 154 //------------------------------------------------------------------------------------------------- 155 // Macro and Define 156 //------------------------------------------------------------------------------------------------- 157 158 159 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 160 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 161 162 // NONPM 163 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF 164 #if XC_REGISTER_SPREAD 165 #define REG_SCALER_BASE 0x130000UL 166 #else 167 #define REG_SCALER_BASE 0x102F00UL 168 #endif 169 #define REG_HDGEN_BASE 0x103000 170 #define REG_LPLL_BASE 0x103100 171 #define REG_MOD_BASE 0x103200 172 #define REG_UTMI1_BASE 0x103A00 173 174 #define XC_DAC_BASE 0x101A00 175 #define HDMITX_MISC_REG_BASE 0x172A00 176 177 178 179 #define L_BK_DAC(x) BK_REG_L(XC_DAC_BASE, x) 180 #define H_BK_DAC(x) BK_REG_H(XC_DAC_BASE, x) 181 #define L_BK_HDMITX(x) BK_REG_L(HDMITX_MISC_REG_BASE, x) 182 #define H_BK_HDMITX(x) BK_REG_H(HDMITX_MISC_REG_BASE, x) 183 184 185 /* TCON */ 186 #define L_BK_TCON(x) BK_REG_L(REG_HDGEN_BASE, x) 187 #define H_BK_TCON(x) BK_REG_H(REG_HDGEN_BASE, x) 188 189 /* LPLL */ 190 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 191 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 192 193 /* UTMI1 */ 194 #define L_BK_UTMI1(x) BK_REG_L(REG_UTMI1_BASE, x) 195 #define H_BK_UTMI1(x) BK_REG_H(REG_UTMI1_BASE, x) 196 197 #define REG_CLKGEN0_52_L (REG_CHIPTOP_BASE + 0xA4) 198 #define REG_CLKGEN0_53_L (REG_CHIPTOP_BASE + 0xA6) 199 #define REG_CLKGEN0_57_L (REG_CHIPTOP_BASE + 0xAE) 200 #define REG_CLKGEN0_58_L (REG_CHIPTOP_BASE + 0xB0) 201 #define REG_CLKGEN0_5E_L (REG_CHIPTOP_BASE + 0xBC) 202 203 204 205 #define XC_PAFRC_DITH_NOISEDITH_EN (0x01) 206 #define XC_PAFRC_DITH_TAILCUT_DISABLE (0x00) 207 208 #define LVDS_DUAL_OUTPUT 0 209 #define LVDS_DUAL_OUTPUT_SPECIAL 1// only for use with T8 board 210 #define LVDS_SINGLE_OUTPUT_A 2 211 #define LVDS_SINGLE_OUTPUT_B 3 212 #define LVDS_OUTPUT_User 4 213 214 // SCALER CLK select 215 #define REG_CKG_ODCLK REG_CLKGEN0_53_L 216 #define CKG_ODCLK_GATED BIT(0) 217 #define CKG_ODCLK_INVERT BIT(1) 218 #define CKG_ODCLK_MASK BMASK(3:2) 219 #define CKG_ODCLK_CLK_OUT_PIX (0 << 2) 220 #define CKG_ODCLK_CLK_LPLL CKG_ODCLK_CLK_OUT_PIX //Mapping 221 222 #define REG_CKG_SC1_ODCLK REG_CLKGEN0_5E_L 223 #define CKG_SC1_ODCLK_GATED BIT(8) 224 #define CKG_SC1_ODCLK_INVERT BIT(9) 225 #define CKG_SC1_ODCLK_MASK BMASK(11:10) 226 #define CKG_SC1_ODCLK_13M (0 << 10) 227 #define CKG_SC1_ODCLK_EDCLK (1 << 10) 228 229 #define PANEL_LPLL_INPUT_DIV_1st 0x00 230 #define PANEL_LPLL_INPUT_DIV_2nd 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 231 #define PANEL_LPLL_LOOP_DIV_1st 0x03 // 0:/1, 1:/2, 2:/4, 3:/8 232 #define PANEL_LPLL_LOOP_DIV_2nd 0x01 // 233 #define PANEL_LPLL_OUTPUT_DIV_1st 0x00 // 0:/1, 1:/2, 2:/4, 3:/8 234 #define PANEL_LPLL_OUTPUT_DIV_2nd 0x00 235 #define LPLL_LOOPGAIN 0x08 236 237 #define LVDS_MPLL_CLOCK_MHZ 216 // For crystal 24Mhz, mm = 9 238 #define LVDS_SPAN_FACTOR 131072 239 240 #define REG_DAC_SD_CTRL (0x00) 241 #define REG_DAC_SD_CLK (0x01) 242 #define REG_DAC_SD_SEL (0x02) 243 #define REG_DAC_HD_CTRL (0x03) 244 #define REG_DAC_HD_CLK (0x04) 245 #define REG_DAC_HD_SEL (0x05) 246 #define REG_DAC_LEVEL_CTRL (0x08) 247 #define REG_VE_CONFIG_01 0x01 248 249 #define VOP_DE_HSTART_MASK (0x3FFF) //BK_10_04 250 #define VOP_DE_HEND_MASK (0x3FFF) //BK_10_05 251 #define VOP_DE_VSTART_MASK (0x1FFF) //BK_10_06 252 #define VOP_DE_VEND_MASK (0x1FFF) //BK_10_07 253 254 #define VOP_VTT_MASK (0x1FFF) //BK_10_0D 255 #define VOP_HTT_MASK (0x3FFF) //BK_10_0C 256 257 #define VOP_VSYNC_END_MASK (0x1FFF) //BK_10_03 258 #define VOP_DISPLAY_HSTART_MASK (0x3FFF) //BK_10_08 259 #define VOP_DISPLAY_HEND_MASK (0x3FFF) //BK_10_09 260 #define VOP_DISPLAY_VSTART_MASK (0x1FFF) //BK_10_0A 261 #define VOP_DISPLAY_VEND_MASK (0x1FFF) //BK_10_0B 262 263 //------------------------------------------------------------------------------------------------- 264 // Type and Structure 265 //------------------------------------------------------------------------------------------------- 266 typedef enum 267 { 268 E_HALPNL_DEVICE0_XC_BANK_OFFSET = 0, 269 E_HALPNL_DEVICE1_XC_BANK_OFFSET = 0x80 270 }PNL_HAL_DEVICE_XC_BANK_OFFSET; 271 272 typedef enum 273 { 274 E_DRVPNL_ALLIN_MODE = 1, 275 E_DRVPNL_2X_MODE = 2, 276 E_DRVPNL_SEPARATE_MODE = 3, 277 E_DRVPNL_TYPE_NUM 278 }DRVPNL_OUT_SWING_TYPE; 279 280 typedef enum 281 { 282 HAL_TI_10BIT_MODE = 0, 283 HAL_TI_8BIT_MODE = 2, 284 HAL_TI_6BIT_MODE = 3, 285 } PNL_HAL_TIMODES; 286 287 //------------------------------------------------------------------------------------------------- 288 // Function and Variable 289 //------------------------------------------------------------------------------------------------- 290 HAL_PNL_INTERFACE MS_VIRT g_ptr_PnlRiuBaseAddr; 291 HAL_PNL_INTERFACE MS_VIRT g_ptr_PMRiuBaseAddr; 292 293 MS_U8 MHal_MOD_PowerOn(void *pInstance, MS_BOOL bEn, MS_U8 u8LPLL_Type,MS_U8 DualModeType, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 294 void MHal_PNL_TCON_Init(void *pInstance); 295 296 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 297 298 void MHal_Shift_LVDS_Pair(void *pInstance, MS_U8 Type); 299 void MHal_Output_LVDS_Pair_Setting(void *pInstance, MS_U8 Type, MS_U16 u16OutputCFG0_7, MS_U16 u16OutputCFG8_15, MS_U16 u16OutputCFG16_21); 300 void MHal_PQ_Clock_Gen_For_Gamma(void *pInstance); 301 302 void MHal_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping); 303 MS_BOOL Hal_VOP_Is_GammaMappingMode_enable(void *pInstance); 304 MS_BOOL Hal_VOP_Is_GammaSupportSignalWrite(void *pInstance, DRVPNL_GAMMA_MAPPEING_MODE u8Mapping); 305 void hal_PNL_WriteGamma12Bit(void *pInstance, MS_U8 u8Channel, MS_BOOL bBurstWrite, MS_U16 u16Addr, MS_U16 u16GammaValue); 306 void hal_PNL_SetMaxGammaValue( void *pInstance, MS_U8 u8Channel, MS_U16 u16MaxGammaValue); 307 void Hal_PNL_Set12BitGammaPerChannel( void *pInstance, MS_U8 u8Channel, MS_U8 * u8Tab, DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode ); 308 #define Hal_PNL_Get12BitGammaPerChannel(args...) 309 void MHal_PNL_Init_LPLL(void *pInstance, PNL_TYPE eLPLL_Type,PNL_MODE eLPLL_Mode,MS_U64 ldHz); 310 //void _MDrv_PNL_Set_12BIT_Gamma( MS_U8 u8Channel, MS_U8 * u8Tab ); 311 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 312 #define MHal_PNL_FRC_lpll_src_sel(args...) 313 314 MS_U8 MHal_PNL_Get_Loop_DIV( void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz); 315 MS_BOOL Hal_PNL_SkipTimingChange_GetCaps(void *pInstance); 316 void MHal_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode); 317 void MHal_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo); 318 void MHal_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_MSB_limit, MS_PHY u32OD_LSB_Addr, MS_PHY u32OD_LSB_limit, MS_U8 u8MIUSel); 319 void MHal_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable); 320 void MHal_PNL_OverDriver_TBL(void *pInstance, MS_U8 u8ODTbl[1056]); 321 322 void MHal_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam); 323 PNL_OUTPUT_MODE MHal_PNL_Get_Output_MODE(void *pInstance); 324 void MHal_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type); 325 MS_BOOL MHal_PNL_MOD_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level); 326 MS_BOOL MHal_PNL_MOD_Control_Out_PE_Current (void *pInstance, MS_U16 u16Current_Level); 327 #define MHal_PNL_MOD_PECurrent_Setting(args...) 328 MS_BOOL MHal_PNL_MOD_Control_Out_TTL_Resistor_OP (void *pInstance, MS_BOOL u16TTL_OP_Level); 329 330 void MHal_PNL_Init_MOD(void *pInstance, PNL_InitData *pstPanelInitData); 331 void MHal_PNL_Init_XC_Clk(void *pInstance, PNL_InitData *pstPanelInitData); 332 void MHal_PNL_DumpMODReg(void *pInstance, MS_U32 u32Addr, MS_U16 u16Value, MS_BOOL bHiByte, MS_U16 u16Mask); 333 void MHal_MOD_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData); 334 void MHal_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type); 335 PNL_Result MHal_PNL_MOD_Calibration(void *pInstance); 336 PNL_Result MHal_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn); 337 void MHal_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue); 338 339 void MHal_PNL_Switch_LPLL_SubBank(void *pInstance, MS_U16 u16Bank); 340 void Mhal_PNL_Flock_LPLLSet(void *pInstance, MS_U64 ldHz); 341 342 void MHal_PNL_Switch_TCON_SubBank(void *pInstance, MS_U16 u16Bank); 343 MS_U16 MHal_PNL_Read_TCON_SubBank(void *pInstance); 344 MS_BOOL MHal_PNL_IsYUVOutput(void *pInstance); 345 346 MS_BOOL MHal_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable); 347 void MHal_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable); 348 349 /// Set pair swap for user mode 350 #define MHal_FRC_MOD_PairSwap_UserMode(args...) 351 352 #define MHal_PNL_Is_Support120Hz(args...) SUPPORT_FRC 353 354 #define MHal_PNL_CalExtLPLLSETbyDClk(args...) 355 356 #define MHal_PNL_VBY1_Handshake(args...) TRUE 357 #define MHal_PNL_VBY1_OC_Handshake(args...) TRUE 358 359 360 #define MHal_PNL_SetOutputInterlaceTiming(args...) 0 361 MS_BOOL MHal_PNL_GetOutputInterlaceTiming(void *pInstance); 362 #define MHal_PNL_SetOSDCOutputType(args...) 363 364 #define MHal_PNL_Set_T3D_Setting(args...) 365 366 void MHal_PNL_Set_Device_Bank_Offset(void *pInstance); 367 void MHal_PNL_Init(void *pInstance); 368 #define MHal_PNL_ChannelFIFOPointerADjust(args...) 369 #define MHal_Pnl_Get_SupportMaxDclk(args...) 0 370 371 MS_U16 MHal_PNL_GetPanelVStart(void); 372 #define MHal_PNL_Check_VBY1_Handshake_Status(args...) FALSE 373 #define MHal_PNL_VBY1_Hardware_TrainingMode_En(args...) 374 #define MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(args...) FALSE 375 #define MHal_PNL_TCON_Patch(args...) 376 377 #ifdef __cplusplus 378 } 379 #endif 380 381 #endif // _HAL_PNL_H_ 382 383