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Searched refs:MAU1_LV2_1_MIU_SEL (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h368 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2424 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2434 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2444 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2469 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2479 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2489 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2440 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2450 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2460 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2439 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2449 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2459 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2560 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2570 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2580 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2578 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2588 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2598 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2506 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2516 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2526 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2745 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2755 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2765 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2726 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2736 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2746 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h383 #define MAU1_LV2_1_MIU_SEL(vpu) (MAU1_LV2_1_BASE(vpu)+(0x0001<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2720 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2730 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2740 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2716 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2726 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2736 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) macro
H A DhalVPU_EX.c2728 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2738 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()
2748 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900); in HAL_VPU_EX_CPUSetting()

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