Home
last modified time | relevance | path

Searched refs:CKG_ODCLK_INVERT (Results 1 – 25 of 64) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c1764 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1768 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1779 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1786 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c1764 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1768 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1779 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1786 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2698 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2719 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2729 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h248 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2698 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2709 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2719 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
2729 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1424 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1428 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h212 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1424 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
1428 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h212 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.h217 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.h217 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.h217 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.h217 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3470 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3500 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3531 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3621 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h250 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3497 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3527 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3558 … W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // [1] invert clock in MHal_PNL_Init_XC_Clk()
3648 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_INVERT); // clock not invert in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h250 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h225 #define CKG_ODCLK_INVERT BIT(1) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h352 #define CKG_ODCLK_INVERT BIT1 macro

123