1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef __CLKGEN_REG_S4LE_H__ 96 #define __CLKGEN_REG_S4LE_H__ 97 98 #define REG_CKG_USB30 0x1E24 99 #define CKG_USB30_GATED BIT0 100 #define CKG_USB30_INVERT BIT1 101 102 #define REG_CKG_DOT_MINI 0x1E25 103 #define CKG_DOT_MINI_GATED BIT0 104 #define CKG_DOT_MINI_INVERT BIT1 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2) 106 #define CKG_DOT_MINI_CLK_LPLL (0 << 2) 107 #define CKG_DOT_MINI_FIFO_CLK (1 << 2) 108 #define CKG_DOT_MINI_DFT_LIVE (3 << 2) 109 110 #define REG_CKG_MIU 0x1E25 111 #define CKG_MIU_GATED BIT4 112 #define CKG_MIU_INVERT BIT5 113 #define CKG_MIU_MASK (BIT7 | BIT6) 114 #define REG_CKG_MIU_4 0x1E46 115 #define CKG_MIU_4_MASK BIT1 116 #define CKG_MIU_MEMPLL (0 << 6) 117 #define CKG_MIU_170MHZ (1 << 6) 118 #define CKG_MIU_MEMPLL_DIV2 (2 << 6) 119 #define CKG_MIU_216MHZ (3 << 6) 120 #define CKG_MIU_SCPLL (4 << 6) 121 #define CKG_MIU_192MHZ (5 << 6) 122 123 #define REG_CKG_TS0 0x1E26 124 #define CKG_TS0_GATED BIT0 125 #define CKG_TS0_INVERT BIT1 126 #define CKG_TS0_MASK (BIT3 | BIT2) 127 #define CKG_TS0_TS0_CLK (0 << 2) 128 #define CKG_TS0_TS2_CLK (1 << 2) 129 #define CKG_TS0_0 (2 << 2) 130 #define CKG_TS0_XTAL (3 << 2) 131 132 #define REG_CKG_TCK 0x1E26 133 #define CKG_TCK_GATED BIT4 134 #define CKG_TCK_INVERT BIT5 135 136 #define REG_CKG_AEON 0x1E26 137 #define CKG_AEON_GATED BIT6 138 #define CKG_AEON_INVERT BIT7 139 140 #define REG_CKG_TSP 0x1E27 141 #define CKG_TSP_GATED BIT0 142 #define CKG_TSP_INVERT BIT1 143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2) 144 #define CKG_TSP_144MHZ (0 << 2) 145 #define CKG_TSP_123MHZ (1 << 2) 146 #define CKG_TSP_72MHZ (2 << 2) 147 #define CKG_TSP_XTAL (7 << 2) 148 149 #define REG_CKG_STC0 0x1E27 150 #define CKG_STC0_GATED BIT4 151 #define CKG_STC0_INVERT BIT5 152 #define CKG_STC0_MASK (BIT7 | BIT6) 153 #define CKG_STC0_STC0_SYNTH (0 << 6) 154 #define CKG_STC0_1 (1 << 6) 155 #define CKG_STC0_27MHZ (2 << 6) 156 #define CKG_STC0_XTAL (3 << 6) 157 158 #define REG_CKG_MAD_STC 0x1E28 159 #define CKG_MAD_STC_GATED BIT4 160 #define CKG_MAD_STC_INVERT BIT5 161 #define CKG_MAD_STC_MASK (BIT7 | BIT6) 162 #define CKG_MAD_STC_STC0_SYNTH (0 << 6) 163 #define CKG_MAD_STC_1 (1 << 6) 164 #define CKG_MAD_STC_27MHZ (2 << 6) 165 #define CKG_MAD_STC_XTAL (3 << 6) 166 167 #define REG_MVD_BOOT 0x1E29 168 #define CKG_MVD_BOOT_GATED BIT0 169 #define CKG_MVD_BOOT_INVERT BIT1 170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2) 171 #define CKG_MVD_BOOT_144MHZ (0 << 2) 172 #define CKG_MVD_BOOT_123MHZ (1 << 2) 173 #define CKG_MVD_BOOT_CLK_MIU (2 << 2) 174 #define CKG_MVD_BOOT_XTAL (3 << 2) 175 176 #define REG_CKG_MVD 0x1E29 177 #define CKG_MVD_GATED BIT4 178 #define CKG_MVD_INVERT BIT5 179 #define CKG_MVD_MASK (BIT7 | BIT6) 180 #define CKG_MVD_144MHZ (0 << 6) 181 #define CKG_MVD_123MHZ (1 << 6) 182 #define CKG_MVD_CLK_MIU (2 << 6) 183 #define CKG_MVD_XTAL (3 << 6) 184 185 #define REG_CKG_MVD_IAP_RMEM 0x1E2A 186 #define CKG_MVD_IAP_RMEM_GATED BIT0 187 #define CKG_MVD_IAP_RMEM_INVERT BIT1 188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2) 189 #define CKG_MVD_IAP_RMEM_CLK_MVD_P (0 << 2) 190 #define CKG_MVD_IAP_RMEM_CLK_MIU_P (1 << 2) 191 #define CKG_MVD_IAP_RMEM_XTAL (3 << 2) 192 193 #define REG_CKG_DC0 0x1E2A 194 #define CKG_DC0_GATED BIT4 195 #define CKG_DC0_INVERT BIT5 196 #define CKG_DC0_MASK (BIT7 | BIT6) 197 #define REG_CKG_DC0_3 0x1E46 198 #define CKG_DC0_3_MASK BIT0 199 #define CKG_DC0_SYNCHRONOUS (0 << 6) 200 #define CKG_DC0_FREERUN (1 << 6) 201 #define CKG_DC0_27MHZ (2 << 6) 202 #define CKG_DC0_54MHZ (3 << 6) 203 #define CKG_DC0_72MHZ (4 << 6) 204 #define CKG_DC0_86MHZ (5 << 6) 205 #define CKG_DC0_108MHZ (6 << 6) 206 #define CKG_DC0_144MHZ (7 << 6) 207 208 #define REG_CKG_RVD 0x1E2B 209 #define CKG_RVD_GATED BIT0 210 #define CKG_RVD_INVERT BIT1 211 #define CKG_RVD_MASK (BIT3 | BIT2) 212 #define CKG_RVD_108MHZ (0 << 2) 213 #define CKG_RVD_86MHZ (1 << 2) 214 #define CKG_RVD_72MHZ (2 << 2) 215 #define CKG_RVD_XTAL (3 << 2) 216 217 #define REG_CKG_GE 0x1E2B 218 #define CKG_GE_GATED BIT4 219 #define CKG_GE_INVERT BIT5 220 #define CKG_GE_MASK (BIT7 | BIT6) 221 #define CKG_GE_170MHZ (0 << 6) 222 #define CKG_GE_123MHZ (1 << 6) 223 #define CKG_GE_86MHZ (2 << 6) 224 #define CKG_GE_144MHZ (3 << 6) 225 226 #define REG_CKG_GOPG0 0x1E2C 227 #define CKG_GOPG0_GATED BIT0 228 #define CKG_GOPG0_INVERT BIT1 229 #define CKG_GOPG0_MASK (BIT3 | BIT2) 230 #define CKG_GOPG0_ODCLK (0 << 2) 231 #define CKG_GOPG0_0 (1 << 2) 232 #define CKG_GOPG0_IDCLK2 (2 << 2) 233 #define CKG_GOPG0_XTAL (3 << 2) 234 235 #define REG_CKG_GOPG1 0x1E2C 236 #define CKG_GOPG1_GATED BIT4 237 #define CKG_GOPG1_INVERT BIT5 238 #define CKG_GOPG1_MASK (BIT7 | BIT6) 239 #define CKG_GOPG1_ODCLK (0 << 6) 240 #define CKG_GOPG1_0 (1 << 6) 241 #define CKG_GOPG1_IDCLK2 (2 << 6) 242 #define CKG_GOPG1_XTAL (3 << 6) 243 244 #define REG_CKG_GOPD 0x1E2D 245 #define CKG_GOPD_GATED BIT0 246 #define CKG_GOPD_INVERT BIT1 247 #define CKG_GOPD_MASK (BIT3 | BIT2) 248 #define CKG_GOPD_CLK_ADC (0 << 2) 249 #define CKG_GOPD_CLK_ODCLK (1 << 2) 250 #define CKG_GOPD_CLK_DC0 (2 << 2) 251 #define CKG_GOPD_XTAL (3 << 2) 252 253 #define REG_CKG_VD 0x1E2D 254 #define CKG_VD_GATED BIT4 255 #define CKG_VD_INVERT BIT5 256 #define CKG_VD_MASK (BIT7 | BIT6) 257 #define CKG_VD_CLK_VD (0 << 6) 258 #define CKG_VD_CLK_VD_ (1 << 6) 259 #define CKG_VD_TESTMODE_CLK (2 << 6) 260 #define CKG_VD_XTAL (3 << 6) 261 262 #define REG_CKG_VDMCU 0x1E2E 263 #define CKG_VDMCU_GATED BIT0 264 #define CKG_VDMCU_INVERT BIT1 265 #define CKG_VDMCU_MASK (BIT3 | BIT2) 266 #define CKG_VDMCU_108MHZ (0 << 2) 267 #define CKG_VDMCU_86MHZ (1 << 2) 268 #define CKG_VDMCU_54MHZ (2 << 2) 269 #define CKG_VDMCU_XTAL (3 << 2) 270 271 #define REG_CKG_VD200 0x1E2E 272 #define CKG_VD200_GATED BIT4 273 #define CKG_VD200_INVERT BIT5 274 #define CKG_VD200_MASK (BIT7 | BIT6) 275 #define CKG_VD200_216MHZ (0 << 6) 276 #define CKG_VD200_216MHZ_ (1 << 6) 277 #define CKG_VD200_216MHZ__ (2 << 6) 278 #define CKG_VD200_XTAL (3 << 6) 279 280 #define REG_CKG_FICLK_F2 0x1E30 281 #define CKG_FICLK_F2_GATED BIT4 282 #define CKG_FICLK_F2_INVERT BIT5 283 #define CKG_FICLK_F2_MASK (BIT7 | BIT6) 284 #define CKG_FICLK_F2_CLK_IDCLK2 (0 << 6) 285 #define CKG_FICLK_F2_CLK_FCLK (1 << 6) 286 #define CKG_FICLK_F2_0 (2 << 6) 287 #define CKG_FICLK_F2_XTAL (3 << 6) 288 289 #define REG_CKG_GOPG2 0x1E31 290 #define CKG_GOPG2_GATED BIT0 291 #define CKG_GOPG2_INVERT BIT1 292 #define CKG_GOPG2_MASK (BIT3 | BIT2) 293 #define CKG_GOPG2_CLK_ODCLK (0 << 2) 294 #define CKG_GOPG2_0 (1 << 2) 295 #define CKG_GOPG2_CLK_IDCLK2 (2 << 2) 296 #define CKG_GOPG2_XTAL (3 << 2) 297 298 #define REG_CKG_PCM 0x1E31 299 #define CKG_PCM_GATED BIT4 300 #define CKG_PCM_INVERT BIT5 301 #define CKG_PCM_MASK (BIT7 | BIT6) 302 #define CKG_PCM_27MHZ (0 << 6) 303 #define CKG_PCM_27MHZ_ (1 << 6) 304 #define CKG_PCM_XTAL (2 << 6) 305 #define CKG_PCM_XTAL_ (3 << 6) 306 307 #define REG_CKG_VE 0x1E33 308 #define CKG_VE_GATED BIT0 309 #define CKG_VE_INVERT BIT1 310 #define CKG_VE_MASK (BIT3 | BIT2) 311 #define CKG_VE_27MHZ (0 << 2) 312 #define CKG_VE_27MHZ_ (1 << 2) 313 #define CKG_VE_XTAL (2 << 2) 314 #define CKG_VE_XTAL_ (3 << 2) 315 316 #define REG_CKG_VEDAC 0x1E33 317 #define CKG_VEDAC_GATED BIT4 318 #define CKG_VEDAC_INVERT BIT5 319 #define CKG_VEDAC_MASK (BIT7 | BIT6) 320 #define CKG_VEDAC_27MHZ (0 << 6) 321 #define CKG_VEDAC_54MHZ (1 << 6) 322 #define CKG_VEDAC_108MHZ (2 << 6) 323 #define CKG_VEDAC_DFT_LIVE (3 << 6) 324 325 #define REG_CKG_FODCLK 0x1E34 326 #define CKG_FODCLK_GATED BIT0 327 #define CKG_FODCLK_INVERT BIT1 328 #define CKG_FODCLK_MASK (BIT3 | BIT2) 329 #define CKG_FODCLK_FCLK_P (0 << 2) 330 #define CKG_FODCLK_ODCLK_P (1 << 2) 331 #define CKG_FODCLK_XTAL (3 << 2) 332 333 #define REG_CKG_FCLK 0x1E35 334 #define CKG_FCLK_GATED BIT0 335 #define CKG_FCLK_INVERT BIT1 336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) 337 #define CKG_FCLK_170MHZ (0 << 2) 338 #define CKG_FCLK_CLK_MIU (1 << 2) 339 #define CKG_FCLK_CLK_ODCLK (2 << 2) 340 #define CKG_FCLK_216MHZ (3 << 2) 341 #define CKG_FCLK_CLK_IDCLK2 (4 << 2) 342 #define CKG_FCLK_SCPLL (5 << 2) 343 #define CKG_FCLK_0 (6 << 2) 344 #define CKG_FCLK_XTAL (7 << 2) 345 #define CKG_FCLK_XTAL_ (8 << 2) 346 347 #define REG_CKG_CPUM 0x1E36 348 #define CKG_CPUM_GATED BIT0 349 350 #define REG_CKG_ODCLK 0x1E37 351 #define CKG_ODCLK_GATED BIT0 352 #define CKG_ODCLK_INVERT BIT1 353 #define CKG_ODCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) 354 #define CKG_ODCLK_CLK_ADC (0 << 2) 355 #define CKG_ODCLK_CLK_DVI (1 << 2) 356 #define CKG_ODCLK_CLK_VD (2 << 2) 357 #define CKG_ODCLK_CLK_MPEG0 (3 << 2) 358 #define CKG_ODCLK_1 (4 << 2) 359 #define CKG_ODCLK_CLK_EXT_DI (5 << 2) 360 #define CKG_ODCLK_XTAL (6 << 2) 361 #define CKG_ODCLK_CLK_LPLL (7 << 2) 362 #define CKG_ODCLK_XTAL_ (8 << 2) 363 364 #define REG_CKG_VE_IN 0x1E38 365 #define CKG_VE_IN_GATED BIT0 366 #define CKG_VE_IN_INVERT BIT1 367 #define CKG_VE_IN_MASK (BIT5 | BIT4 | BIT3 | BIT2) 368 #define CKG_VE_IN_CLK_ADC (0 << 2) 369 #define CKG_VE_IN_CLK_DVI (1 << 2) 370 #define CKG_VE_IN_CLK_VD (2 << 2) 371 #define CKG_VE_IN_CLK_MPEG0 (3 << 2) 372 #define CKG_VE_IN_1 (4 << 2) 373 #define CKG_VE_IN_CLK_EXT_DI (5 << 2) 374 #define CKG_VE_IN_0 (6 << 2) 375 #define CKG_VE_IN_0_ (7 << 2) 376 #define CKG_VE_IN_DFT_LIVE (8 << 2) 377 378 #define REG_CKG_NFIE 0x1E39 379 #define CKG_NFIE_GATED BIT0 380 #define CKG_NFIE_INVERT BIT1 381 #define CKG_NFIE_MASK (BIT4 | BIT3 | BIT2) 382 #define CKG_NFIE_62MHZ (0 << 2) 383 #define CKG_NFIE_54MHZ (1 << 2) 384 #define CKG_NFIE_43MHZ (2 << 2) 385 #define CKG_NFIE_36MHZ (3 << 2) 386 #define CKG_NFIE_27MHZ (4 << 2) 387 #define CKG_NFIE_18MHZ (5 << 2) 388 #define CKG_NFIE_13MHZ (6 << 2) 389 #define CKG_NFIE_XTAL (7 << 2) 390 391 #define REG_CKG_TS2 0x1E3A 392 #define CKG_TS2_GATED BIT0 393 #define CKG_TS2_INVERT BIT1 394 #define CKG_TS2_MASK (BIT3 | BIT2) 395 #define CKG_TS2_TS2_CLK (0 << 2) 396 #define CKG_TS2_0 (1 << 2) 397 #define CKG_TS2_0_ (2 << 2) 398 #define CKG_TS2_XTAL (3 << 2) 399 400 #define REG_CKG_TSOUT 0x1E3A 401 #define CKG_TSOUT_GATED BIT4 402 #define CKG_TSOUT_INVERT BIT5 403 #define CKG_TSOUT_MASK (BIT7 | BIT6) 404 #define CKG_TSOUT_27MHZ (0 << 6) 405 #define CKG_TSOUT_36MHZ (1 << 6) 406 #define CKG_TSOUT_43MHZ (2 << 6) 407 #define CKG_TSOUT_XTAL (3 << 6) 408 409 #define REG_CKG_UART 0x1E3C 410 #define CKG_UART_GATED BIT4 // FIXME 411 #define CKG_UART_INVERT BIT5 412 #define CKG_UART_MASK (BIT7 | BIT6) 413 #define REG_CKG_UART_4 0x1E46 414 #define CKG_UART_4_MASK BIT2 415 #define CKG_UART_170MHZ (0 << 6) 416 #define CKG_UART_160MHZ (1 << 6) 417 #define CKG_UART_144MHZ (2 << 6) 418 #define CKG_UART_123MHZ (3 << 6) 419 #define CKG_UART_108MHZ (4 << 6) 420 #define CKG_UART_MEMPLL (5 << 6) 421 #define CKG_UART_MEMPLL_DIV2 (6 << 6) 422 423 #define REG_CKG_DC1 0x1E3D 424 #define CKG_DC1_GATED BIT0 425 #define CKG_DC1_INVERT BIT1 426 #define CKG_DC1_MASK (BIT3 | BIT2) 427 #define CKG_DC1_SYNCHRONOUS (0 << 2) 428 #define CKG_DC1_FREERUN (1 << 2) 429 #define CKG_DC1_27MHZ (2 << 2) 430 #define CKG_DC1_DFT_LIVE (3 << 2) 431 432 #define REG_CKG_IDCLK1 0x1E3E 433 #define CKG_IDCLK1_GATED BIT0 434 #define CKG_IDCLK1_INVERT BIT1 435 #define CKG_IDCLK1_MASK (BIT5 | BIT4 | BIT3 | BIT2) 436 #define CKG_IDCLK1_CLK_ADC (0 << 2) 437 #define CKG_IDCLK1_CLK_DVI (1 << 2) 438 #define CKG_IDCLK1_CLK_VD (2 << 2) 439 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 440 #define CKG_IDCLK1_1 (4 << 2) 441 #define CKG_IDCLK1_CLK_EXT_DI (5 << 2) 442 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 443 #define CKG_IDCLK1_0 (7 << 2) 444 #define CKG_IDCLK1_XTAL (8 << 2) 445 446 #define REG_CKG_IDCLK2 0x1E3F 447 #define CKG_IDCLK2_GATED BIT0 448 #define CKG_IDCLK2_INVERT BIT1 449 #define CKG_IDCLK2_MASK (BIT5 | BIT4 | BIT3 | BIT2) 450 #define CKG_IDCLK2_CLK_ADC (0 << 2) 451 #define CKG_IDCLK2_CLK_DVI (1 << 2) 452 #define CKG_IDCLK2_CLK_VD (2 << 2) 453 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 454 #define CKG_IDCLK2_1 (4 << 2) 455 #define CKG_IDCLK2_CLK_EXT_DI (5 << 2) 456 #define CKG_IDCLK2_CLK_VD_ADC (6 << 2) 457 #define CKG_IDCLK2_0 (7 << 2) 458 #define CKG_IDCLK2_XTAL (8 << 2) 459 460 #define REG_CKG_STRLD 0x1E44 461 #define CKG_STRLD_GATED BIT0 462 #define CKG_STRLD_INVERT BIT1 463 #define CKG_STRLD_MASK (BIT3 | BIT2) 464 #define CKG_STRLD_144MHZ (0 << 2) 465 #define CKG_STRLD_123MHZ (1 << 2) 466 #define CKG_STRLD_108MHZ (2 << 2) 467 #define CKG_STRLD_XTAL (3 << 2) 468 469 #define REG_CKG_MCU 0x1E45 470 #define CKG_MCU_GATED BIT0 471 #define CKG_MCU_INVERT BIT1 472 #define CKG_MCU_MASK (BIT4 | BIT3 | BIT2) 473 #define CKG_MCU_170MHZ (0 << 2) 474 #define CKG_MCU_160MHZ (1 << 2) 475 #define CKG_MCU_144MHZ (2 << 2) 476 #define CKG_MCU_123MHZ (3 << 2) 477 #define CKG_MCU_108MHZ (4 << 2) 478 #define CKG_MCU_CLK_MIU (5 << 2) 479 #define CKG_MCU_CLK_MIU_DIV2 (6 << 2) 480 #define CKG_MCU_0 (7 << 2) 481 482 #define REG_CKG_SVD 0x1E58 483 #define CKG_SVD_GATED BIT0 484 #define CKG_SVD_INVERT BIT1 485 #define CKG_SVD_MASK BITMASK(6:2) 486 #define CKG_SVD_240MHZ (0 << 2) 487 #define CKG_SVD_216MHZ (1 << 2) 488 #define CKG_SVD_CLK_MVD_P (2 << 2) 489 #define CKG_SVD_CLK_RVD_P (3 << 2) 490 #define CKG_SVD_CLK_MIU (8 << 2) 491 #define CKG_SVD_XTAL (18 << 2) 492 493 #define REG_CKG_PSRAM0 0x1E5A 494 #define CKG_PSRAM0_GATED BIT0 495 #define CKG_PSRAM0_INVERT BIT1 496 497 #define REG_CKG_PSRAM1 0x1E5A 498 #define CKG_PSRAM1_GATED BIT2 499 #define CKG_PSRAM1_INVERT BIT3 500 501 #define REG_CKG_JPD 0x1E9A 502 #define CKG_JPD_GATED BIT0 503 #define CKG_JPD_INVERT BIT1 504 #define CKG_JPD_MASK (BIT3 | BIT2) 505 #define CKG_JPD_72MHZ (0 << 2) 506 #define CKG_JPD_108MHZ (1 << 2) 507 #define CKG_JPD_123MHZ (2 << 2) 508 509 #define REG_CKG_VDS REG_CKG_VDMCU 510 #define REG_CKG_VDGOPD REG_CKG_VD 511 #define REG_CKG_AEONTS0 REG_CKG_AEON 512 #define REG_CKG_STC0TSP REG_CKG_TSP 513 #define REG_CKG_VEIN REG_CKG_VE_IN 514 #define REG_CKG_AEON1DC0 REG_CKG_DC0 515 516 #endif /* __CLKGEN_REG_S4LE_H__ */ 517 518