Home
last modified time | relevance | path

Searched refs:CKG_ODCLK_GATED (Results 1 – 25 of 64) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c1765 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1769 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1780 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1787 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c1765 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1769 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1780 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1787 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c2697 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2718 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2728 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h247 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c2697 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2708 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2718 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
2728 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1425 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1429 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h211 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1425 W2BYTEMSK(REG_CKG_ODCLK, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
1429 W2BYTEMSK(REG_CKG_BT656, DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h211 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.h216 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.h216 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.h216 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.h216 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3469 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3499 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3530 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3622 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h249 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3496 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3526 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3557 …W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // [0] disable clock in MHal_PNL_Init_XC_Clk()
3649 W2BYTEMSK(L_CLKGEN0(0x53), DISABLE, CKG_ODCLK_GATED); // enable clock in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h249 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.h224 #define CKG_ODCLK_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h351 #define CKG_ODCLK_GATED BIT0 macro

123