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Searched refs:dev (Results 1 – 25 of 114) sorted by relevance

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/rockchip-linux_mpp/osal/test/
H A Dmpp_platform_test.c14 const char *dev = NULL; in main() local
70 dev = mpp_get_vcodec_dev_name(MPP_CTX_DEC, MPP_VIDEO_CodingAVC); in main()
71 mpp_log("H.264 decoder: %s\n", dev); in main()
73 dev = mpp_get_vcodec_dev_name(MPP_CTX_DEC, MPP_VIDEO_CodingHEVC); in main()
74 mpp_log("H.265 decoder: %s\n", dev); in main()
76 dev = mpp_get_vcodec_dev_name(MPP_CTX_DEC, MPP_VIDEO_CodingMJPEG); in main()
77 mpp_log("MJPEG decoder: %s\n", dev); in main()
79 dev = mpp_get_vcodec_dev_name(MPP_CTX_DEC, MPP_VIDEO_CodingVP9); in main()
80 mpp_log("VP9 decoder: %s\n", dev); in main()
82 dev = mpp_get_vcodec_dev_name(MPP_CTX_DEC, MPP_VIDEO_CodingAVSPLUS); in main()
[all …]
/rockchip-linux_mpp/osal/driver/
H A Dvcodec_service.c125 #define mpp_find_device(dev) _mpp_find_device(dev, MPP_ARRAY_ELEMS(dev)) argument
127 static const char *_mpp_find_device(const char **dev, RK_U32 size) in _mpp_find_device() argument
132 if (!access(dev[i], F_OK)) in _mpp_find_device()
133 return dev[i]; in _mpp_find_device()
140 const char *dev = NULL; in mpp_get_platform_dev_name() local
147 dev = mpp_find_device(mpp_rkvdec_dev); in mpp_get_platform_dev_name()
150 dev = mpp_find_device(mpp_hevc_dev); in mpp_get_platform_dev_name()
153 dev = mpp_find_device(mpp_avsd_dev); in mpp_get_platform_dev_name()
156 dev = mpp_find_device(mpp_rkvenc_dev); in mpp_get_platform_dev_name()
159 dev = mpp_find_device(mpp_h265e_dev); in mpp_get_platform_dev_name()
[all …]
/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu382_com.c75 void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info) in vdpu382_setup_rcb() argument
91 mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset); in vdpu382_setup_rcb()
93 mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset); in vdpu382_setup_rcb()
95 mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset); in vdpu382_setup_rcb()
97 mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset); in vdpu382_setup_rcb()
99 mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset); in vdpu382_setup_rcb()
101 mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset); in vdpu382_setup_rcb()
103 mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset); in vdpu382_setup_rcb()
105 mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset); in vdpu382_setup_rcb()
107 mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset); in vdpu382_setup_rcb()
[all …]
H A Dvdpu34x_com.c75 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info) in vdpu34x_setup_rcb() argument
91 mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset); in vdpu34x_setup_rcb()
93 mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset); in vdpu34x_setup_rcb()
95 mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset); in vdpu34x_setup_rcb()
97 mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset); in vdpu34x_setup_rcb()
99 mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset); in vdpu34x_setup_rcb()
101 mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset); in vdpu34x_setup_rcb()
103 mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset); in vdpu34x_setup_rcb()
105 mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset); in vdpu34x_setup_rcb()
107 mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset); in vdpu34x_setup_rcb()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu1_v2.c49 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_jpege_vepu1_init()
54 ctx->dev = cfg->dev; in hal_jpege_vepu1_init()
89 if (ctx->dev) { in hal_jpege_vepu1_deinit()
90 mpp_dev_deinit(ctx->dev); in hal_jpege_vepu1_deinit()
91 ctx->dev = NULL; in hal_jpege_vepu1_deinit()
132 static MPP_RET hal_jpege_vepu1_set_extra_info(MppDev dev, JpegeSyntax *syntax, in hal_jpege_vepu1_set_extra_info() argument
146 mpp_dev_set_reg_offset(dev, 11, offset); in hal_jpege_vepu1_set_extra_info()
153 mpp_dev_set_reg_offset(dev, 12, offset); in hal_jpege_vepu1_set_extra_info()
158 mpp_dev_set_reg_offset(dev, 13, offset); in hal_jpege_vepu1_set_extra_info()
164 mpp_dev_set_reg_offset(dev, 11, offset); in hal_jpege_vepu1_set_extra_info()
[all …]
H A Dhal_jpege_vepu2_v2.c77 ret = mpp_dev_init(&cfg->dev, type); in hal_jpege_vepu2_init()
82 ctx->dev = cfg->dev; in hal_jpege_vepu2_init()
120 if (ctx->dev) { in hal_jpege_vepu2_deinit()
121 mpp_dev_deinit(ctx->dev); in hal_jpege_vepu2_deinit()
122 ctx->dev = NULL; in hal_jpege_vepu2_deinit()
339 static MPP_RET hal_jpege_vepu2_set_extra_info(MppDev dev, JpegeSyntax *syntax, in hal_jpege_vepu2_set_extra_info() argument
355 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_Y, cfg.offset_byte[0]); in hal_jpege_vepu2_set_extra_info()
358 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_U, cfg.offset_byte[1]); in hal_jpege_vepu2_set_extra_info()
361 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_V, cfg.offset_byte[2]); in hal_jpege_vepu2_set_extra_info()
468 mpp_dev_set_reg_offset(ctx->dev, 77, bytepos); in hal_jpege_vepu2_gen_regs()
[all …]
/rockchip-linux_mpp/mpp/base/inc/
H A Dmpp_buffer_impl.h200 MPP_RET mpp_buffer_attach_dev_f(const char *caller, MppBuffer buffer, MppDev dev);
201 MPP_RET mpp_buffer_detach_dev_f(const char *caller, MppBuffer buffer, MppDev dev);
202 RK_U32 mpp_buffer_get_iova_f(const char *caller, MppBuffer buffer, MppDev dev);
204 #define mpp_buffer_attach_dev(buf, dev) mpp_buffer_attach_dev_f(__FUNCTION__, buf, dev) argument
205 #define mpp_buffer_detach_dev(buf, dev) mpp_buffer_detach_dev_f(__FUNCTION__, buf, dev) argument
206 #define mpp_buffer_get_iova(buf, dev) mpp_buffer_get_iova_f(__FUNCTION__, buf, dev) argument
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c43 MppDev dev; member
91 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_jpege_v540c_init()
97 ctx->dev = cfg->dev; in hal_jpege_v540c_init()
118 if (ctx->dev) { in hal_jpege_v540c_deinit()
119 mpp_dev_deinit(ctx->dev); in hal_jpege_v540c_deinit()
120 ctx->dev = NULL; in hal_jpege_v540c_deinit()
156 cfg.dev = ctx->dev; in hal_jpege_v540c_gen_regs()
256 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); in hal_jpege_v540c_start()
266 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); in hal_jpege_v540c_start()
276 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg); in hal_jpege_v540c_start()
[all …]
H A Dhal_jpege_vepu511.c32 MppDev dev; member
79 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_jpege_vepu511_init()
85 ctx->dev = cfg->dev; in hal_jpege_vepu511_init()
105 if (ctx->dev) { in hal_jpege_vepu511_deinit()
106 mpp_dev_deinit(ctx->dev); in hal_jpege_vepu511_deinit()
107 ctx->dev = NULL; in hal_jpege_vepu511_deinit()
126 static MPP_RET vepu511_jpeg_set_patch_info(MppDev dev, JpegeSyntax *syn, in vepu511_jpeg_set_patch_info() argument
184 mpp_dev_set_reg_offset(dev, 265, u_offset); in vepu511_jpeg_set_patch_info()
188 mpp_dev_set_reg_offset(dev, 266, v_offset); in vepu511_jpeg_set_patch_info()
210 vepu511_jpeg_set_patch_info(cfg->dev, syn, (VepuFmt)fmt->format, task); in vepu511_set_jpeg_reg()
[all …]
H A Dhal_jpege_vpu720.c88 MppDev dev; member
132 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_jpege_vpu720_init()
138 ctx->dev = cfg->dev; in hal_jpege_vpu720_init()
150 mpp_buffer_attach_dev(ctx->qtbl_buffer, ctx->dev); in hal_jpege_vpu720_init()
169 if (ctx->dev) { in hal_jpege_vpu720_deinit()
170 mpp_dev_deinit(ctx->dev); in hal_jpege_vpu720_deinit()
171 ctx->dev = NULL; in hal_jpege_vpu720_deinit()
513 mpp_dev_set_reg_offset(ctx->dev, 20, mpp_packet_get_length(task->packet)); in hal_jpege_vpu720_gen_regs()
514 mpp_dev_set_reg_offset(ctx->dev, 17, mpp_buffer_get_size(task->output)); in hal_jpege_vpu720_gen_regs()
515 mpp_dev_set_reg_offset(ctx->dev, 23, ctx->fmt_cfg.u_offset); in hal_jpege_vpu720_gen_regs()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c43 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1); in hal_m2vd_vdpu1_init()
66 cfg->dev = ctx->dev; in hal_m2vd_vdpu1_init()
88 if (p->dev) { in hal_m2vd_vdpu1_deinit()
89 mpp_dev_deinit(p->dev); in hal_m2vd_vdpu1_deinit()
90 p->dev = NULL; in hal_m2vd_vdpu1_deinit()
218 mpp_dev_set_reg_offset(ctx->dev, 12, dx->bitstream_offset); in hal_m2vd_vdpu1_gen_regs()
228 mpp_dev_set_reg_offset(ctx->dev, 13, MPP_ALIGN(dx->seq.decode_width, 16)); in hal_m2vd_vdpu1_gen_regs()
275 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_m2vd_vdpu1_start()
285 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_m2vd_vdpu1_start()
291 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_m2vd_vdpu1_start()
[all …]
H A Dhal_m2vd_vdpu2.c47 ret = mpp_dev_init(&p->dev, VPU_CLIENT_VDPU2); in hal_m2vd_vdpu2_init()
86 cfg->dev = p->dev; in hal_m2vd_vdpu2_init()
112 if (p->dev) { in hal_m2vd_vdpu2_deinit()
113 mpp_dev_deinit(p->dev); in hal_m2vd_vdpu2_deinit()
114 p->dev = NULL; in hal_m2vd_vdpu2_deinit()
268 mpp_dev_set_reg_offset(ctx->dev, 64, dx->bitstream_offset); in hal_m2vd_vdpu2_gen_regs()
279 mpp_dev_set_reg_offset(ctx->dev, 63, MPP_ALIGN(dx->seq.decode_width, 16)); in hal_m2vd_vdpu2_gen_regs()
347 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_m2vd_vdpu2_start()
357 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_m2vd_vdpu2_start()
363 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_m2vd_vdpu2_start()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu2.c48 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2); in hal_vp8d_vdpu2_init()
86 cfg->dev = ctx->dev; in hal_vp8d_vdpu2_init()
91 if (ctx->dev) { in hal_vp8d_vdpu2_init()
92 mpp_dev_deinit(ctx->dev); in hal_vp8d_vdpu2_init()
93 ctx->dev = NULL; in hal_vp8d_vdpu2_init()
126 if (ctx->dev) { in hal_vp8d_vdpu2_deinit()
127 mpp_dev_deinit(ctx->dev); in hal_vp8d_vdpu2_deinit()
128 ctx->dev = NULL; in hal_vp8d_vdpu2_deinit()
270 mpp_dev_set_reg_offset(ctx->dev, 145, pic_param->stream_start_offset); in hal_vp8d_dct_partition_cfg()
299 mpp_dev_set_reg_offset(ctx->dev, 64, addr); in hal_vp8d_dct_partition_cfg()
[all …]
H A Dhal_vp8d_vdpu1.c48 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1); in hal_vp8d_vdpu1_init()
84 cfg->dev = ctx->dev; in hal_vp8d_vdpu1_init()
89 if (ctx->dev) { in hal_vp8d_vdpu1_init()
90 mpp_dev_deinit(ctx->dev); in hal_vp8d_vdpu1_init()
91 ctx->dev = NULL; in hal_vp8d_vdpu1_init()
124 if (ctx->dev) { in hal_vp8d_vdpu1_deinit()
125 mpp_dev_deinit(ctx->dev); in hal_vp8d_vdpu1_deinit()
126 ctx->dev = NULL; in hal_vp8d_vdpu1_deinit()
273 mpp_dev_set_reg_offset(ctx->dev, 27, pic_param->stream_start_offset); in hal_vp8d_dct_partition_cfg()
302 mpp_dev_set_reg_offset(ctx->dev, 12, addr); in hal_vp8d_dct_partition_cfg()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu2.c86 mpp_dev_set_reg_offset(ctx->dev, 64, consumed_bytes_align); in vpu2_h263d_setup_regs_by_syntax()
138 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2); in hal_vpu2_h263d_init()
172 if (ctx->dev) { in hal_vpu2_h263d_deinit()
173 mpp_dev_deinit(ctx->dev); in hal_vpu2_h263d_deinit()
174 ctx->dev = NULL; in hal_vpu2_h263d_deinit()
255 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vpu2_h263d_start()
265 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vpu2_h263d_start()
271 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_vpu2_h263d_start()
287 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_vpu2_h263d_wait()
H A Dhal_h263d_vdpu1.c86 mpp_dev_set_reg_offset(ctx->dev, 12, consumed_bytes_align); in vpu1_h263d_setup_regs_by_syntax()
137 ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1); in hal_vpu1_h263d_init()
171 if (ctx->dev) { in hal_vpu1_h263d_deinit()
172 mpp_dev_deinit(ctx->dev); in hal_vpu1_h263d_deinit()
173 ctx->dev = NULL; in hal_vpu1_h263d_deinit()
254 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg); in hal_vpu1_h263d_start()
264 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vpu1_h263d_start()
270 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL); in hal_vpu1_h263d_start()
286 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL); in hal_vpu1_h263d_wait()
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_api.c97 ret = mpp_dev_init(&p_hal->dev, client_type); in init_hard_platform()
125 if (p_hal->dev) { in hal_avsd_deinit()
126 ret = mpp_dev_deinit(p_hal->dev); in hal_avsd_deinit()
168 cfg->dev = p_hal->dev; in hal_avsd_init()
200 if (p_hal->dev) { in hal_avsd_gen_regs()
201 ret = mpp_dev_deinit(p_hal->dev); in hal_avsd_gen_regs()
205 p_hal->dev = NULL; in hal_avsd_gen_regs()
/rockchip-linux_mpp/mpp/hal/common/av1/
H A Dhal_av1d_api_v2.c68 ret = mpp_dev_init(&cfg->dev, type); in hal_av1d_init()
83 p_hal->dev = cfg->dev; in hal_av1d_init()
109 if (p_hal->dev) { in hal_av1d_deinit()
110 mpp_dev_deinit(p_hal->dev); in hal_av1d_deinit()
111 p_hal->dev = NULL; in hal_av1d_deinit()
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_api.c40 ret = mpp_dev_init(&cfg->dev, client_type); in hal_vp9d_init()
49 p->dev = cfg->dev; in hal_vp9d_init()
89 if (p->dev) { in hal_vp9d_deinit()
90 mpp_dev_deinit(p->dev); in hal_vp9d_deinit()
91 p->dev = NULL; in hal_vp9d_deinit()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu1_v2.c45 MppDev dev; member
87 if (p->dev) { in hal_h264e_vepu1_deinit_v2()
88 mpp_dev_deinit(p->dev); in hal_h264e_vepu1_deinit_v2()
89 p->dev = NULL; in hal_h264e_vepu1_deinit_v2()
117 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_h264e_vepu1_init_v2()
122 p->dev = cfg->dev; in hal_h264e_vepu1_init_v2()
268 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8); in setup_output_packet()
540 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2, in hal_h264e_vepu1_gen_regs_v2()
544 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2, in hal_h264e_vepu1_gen_regs_v2()
548 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2, in hal_h264e_vepu1_gen_regs_v2()
[all …]
H A Dhal_h264e_vepu2_v2.c45 MppDev dev; member
87 if (p->dev) { in hal_h264e_vepu2_deinit_v2()
88 mpp_dev_deinit(p->dev); in hal_h264e_vepu2_deinit_v2()
89 p->dev = NULL; in hal_h264e_vepu2_deinit_v2()
118 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_h264e_vepu2_init_v2()
123 p->dev = cfg->dev; in hal_h264e_vepu2_init_v2()
269 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8); in setup_output_packet()
607 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2, in hal_h264e_vepu2_gen_regs_v2()
611 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2, in hal_h264e_vepu2_gen_regs_v2()
615 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2, in hal_h264e_vepu2_gen_regs_v2()
[all …]
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_api.c59 if (p_hal->dev) { in hal_avs2d_deinit()
60 ret = mpp_dev_deinit(p_hal->dev); in hal_avs2d_deinit()
101 ret = mpp_dev_init(&cfg->dev, VPU_CLIENT_RKVDEC); in hal_avs2d_init()
111 p_hal->dev = cfg->dev; in hal_avs2d_init()
/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_api.c53 ret = mpp_dev_init(&cfg->dev, client_type); in hal_h265d_init()
62 p->dev = cfg->dev; in hal_h265d_init()
104 if (p->dev) { in hal_h265d_deinit()
105 mpp_dev_deinit(p->dev); in hal_h265d_deinit()
106 p->dev = NULL; in hal_h265d_deinit()
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_v2.c58 mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
71 mpp_dev_set_reg_offset(ctx->dev, 11, hw_cfg->input_lum_offset); in vp8e_vpu_frame_start()
75 mpp_dev_set_reg_offset(ctx->dev, 12, hw_cfg->input_cb_offset); in vp8e_vpu_frame_start()
79 mpp_dev_set_reg_offset(ctx->dev, 13, hw_cfg->input_cr_offset); in vp8e_vpu_frame_start()
198 mpp_dev_set_reg_offset(ctx->dev, 58, hw_cfg->partition_offset[0]); in vp8e_vpu_frame_start()
200 mpp_dev_set_reg_offset(ctx->dev, 59, hw_cfg->partition_offset[1]); in vp8e_vpu_frame_start()
291 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_vp8e_vepu1_init_v2()
296 ctx->dev = cfg->dev; in hal_vp8e_vepu1_init_v2()
334 if (ctx->dev) { in hal_vp8e_vepu1_deinit_v2()
335 mpp_dev_deinit(ctx->dev); in hal_vp8e_vepu1_deinit_v2()
[all …]
H A Dhal_vp8e_vepu2_v2.c61 mpp_dev_set_reg_offset(ctx->dev, 77, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
73 mpp_dev_set_reg_offset(ctx->dev, 48, hw_cfg->input_lum_offset); in vp8e_vpu_frame_start()
77 mpp_dev_set_reg_offset(ctx->dev, 49, hw_cfg->input_cb_offset); in vp8e_vpu_frame_start()
81 mpp_dev_set_reg_offset(ctx->dev, 50, hw_cfg->input_cr_offset); in vp8e_vpu_frame_start()
201 mpp_dev_set_reg_offset(ctx->dev, 44, hw_cfg->partition_offset[0]); in vp8e_vpu_frame_start()
203 mpp_dev_set_reg_offset(ctx->dev, 45, hw_cfg->partition_offset[1]); in vp8e_vpu_frame_start()
293 ret = mpp_dev_init(&cfg->dev, cfg->type); in hal_vp8e_vepu2_init_v2()
298 ctx->dev = cfg->dev; in hal_vp8e_vepu2_init_v2()
338 if (ctx->dev) { in hal_vp8e_vepu2_deinit_v2()
339 mpp_dev_deinit(ctx->dev); in hal_vp8e_vepu2_deinit_v2()
[all …]

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