58     mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset);  in vp8e_vpu_frame_start()
71         mpp_dev_set_reg_offset(ctx->dev, 11, hw_cfg->input_lum_offset);  in vp8e_vpu_frame_start()
75         mpp_dev_set_reg_offset(ctx->dev, 12, hw_cfg->input_cb_offset);  in vp8e_vpu_frame_start()
79         mpp_dev_set_reg_offset(ctx->dev, 13, hw_cfg->input_cr_offset);  in vp8e_vpu_frame_start()
198     mpp_dev_set_reg_offset(ctx->dev, 58, hw_cfg->partition_offset[0]);  in vp8e_vpu_frame_start()
200     mpp_dev_set_reg_offset(ctx->dev, 59, hw_cfg->partition_offset[1]);  in vp8e_vpu_frame_start()
291     ret = mpp_dev_init(&cfg->dev, cfg->type);  in hal_vp8e_vepu1_init_v2()
296     ctx->dev = cfg->dev;  in hal_vp8e_vepu1_init_v2()
334     if (ctx->dev) {  in hal_vp8e_vepu1_deinit_v2()
335         mpp_dev_deinit(ctx->dev);  in hal_vp8e_vepu1_deinit_v2()
336         ctx->dev = NULL;  in hal_vp8e_vepu1_deinit_v2()
394         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_vp8e_vepu1_start_v2()
404         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);  in hal_vp8e_vepu1_start_v2()
410         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);  in hal_vp8e_vepu1_start_v2()
454     if (NULL == ctx->dev) {  in hal_vp8e_vepu1_wait_v2()
459     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);  in hal_vp8e_vepu1_wait_v2()