1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_av1d_api"
18
19 #include <stdio.h>
20 #include <stdlib.h>
21 #include <string.h>
22 #include <dlfcn.h>
23 #include <unistd.h>
24
25 #include "mpp_mem.h"
26 #include "mpp_env.h"
27 #include "mpp_platform.h"
28 #include "mpp_common.h"
29
30 #include "dxva_syntax.h"
31
32 #include "hal_av1d_vdpu_reg.h"
33 #include "hal_av1d_vdpu.h"
34 #include "hal_av1d_vdpu383.h"
35 #include "hal_av1d_common.h"
36
37 RK_U32 hal_av1d_debug = 0;
38
hal_av1d_init(void * hal,MppHalCfg * cfg)39 MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
40 {
41 MPP_RET ret = MPP_OK;
42 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
43 RK_U32 vcodec_type = mpp_get_vcodec_type();
44 MppClientType type = VPU_CLIENT_RKVDEC;
45 RK_U32 hw_id = 0;
46
47 INP_CHECK(ret, NULL == p_hal);
48 memset(p_hal, 0, sizeof(Av1dHalCtx));
49 mpp_env_get_u32("hal_av1d_debug", &hal_av1d_debug, 0);
50
51 // check codec_type first
52 if (!(vcodec_type & (HAVE_RKVDEC | HAVE_AV1DEC))) {
53 mpp_err_f("can not found av1 decoder hardware on platform %x\n", vcodec_type);
54 return ret;
55 }
56
57 hw_id = mpp_get_client_hw_id(type);
58 if (hw_id == HWID_VDPU383) {
59 p_hal->api = &hal_av1d_vdpu383;
60 } else {
61 p_hal->api = &hal_av1d_vdpu;
62 type = VPU_CLIENT_AV1DEC;
63 }
64
65 //!< callback function to parser module
66 p_hal->dec_cb = cfg->dec_cb;
67
68 ret = mpp_dev_init(&cfg->dev, type);
69 if (ret) {
70 mpp_err("mpp_dev_init failed ret: %d\n", ret);
71 goto __FAILED;
72 }
73 cfg->hw_info = mpp_get_dec_hw_info_by_client_type(type);
74 p_hal->hw_info = cfg->hw_info;
75
76 //< get buffer group
77 if (p_hal->buf_group == NULL) {
78 FUN_CHECK(ret = mpp_buffer_group_get_internal
79 (&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
80 }
81
82 cfg->support_fast_mode = 0;
83 p_hal->dev = cfg->dev;
84 p_hal->cfg = cfg->cfg;
85 p_hal->slots = cfg->frame_slots;
86 p_hal->packet_slots = cfg->packet_slots;
87 p_hal->fast_mode = cfg->cfg->base.fast_parse && cfg->support_fast_mode;
88
89 if (p_hal->buf_group == NULL) {
90 FUN_CHECK(ret = mpp_buffer_group_get_internal
91 (&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
92 }
93 //!< run init funtion
94 FUN_CHECK(ret = p_hal->api->init(hal, cfg));
95
96 __RETURN:
97 return MPP_OK;
98 __FAILED:
99 return ret;
100 }
101
hal_av1d_deinit(void * hal)102 MPP_RET hal_av1d_deinit(void *hal)
103 {
104 MPP_RET ret = MPP_ERR_UNKNOW;
105 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
106
107 FUN_CHECK(ret = p_hal->api->deinit(hal));
108
109 if (p_hal->dev) {
110 mpp_dev_deinit(p_hal->dev);
111 p_hal->dev = NULL;
112 }
113
114 if (p_hal->buf_group) {
115 FUN_CHECK(ret = mpp_buffer_group_put(p_hal->buf_group));
116 }
117
118 return MPP_OK;
119 __FAILED:
120 return ret;
121 }
122
hal_av1d_gen_regs(void * hal,HalTaskInfo * task)123 MPP_RET hal_av1d_gen_regs(void *hal, HalTaskInfo *task)
124 {
125 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
126 MPP_RET ret = MPP_NOK;
127
128 if (p_hal && p_hal->api && p_hal->api->reg_gen)
129 ret = p_hal->api->reg_gen(hal, task);
130 return ret;
131 }
132
hal_av1d_start(void * hal,HalTaskInfo * task)133 MPP_RET hal_av1d_start(void *hal, HalTaskInfo *task)
134 {
135 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
136 MPP_RET ret = MPP_NOK;
137
138 if (p_hal && p_hal->api && p_hal->api->start)
139 ret = p_hal->api->start(hal, task);
140 return ret;
141 }
142
hal_av1d_wait(void * hal,HalTaskInfo * task)143 MPP_RET hal_av1d_wait(void *hal, HalTaskInfo *task)
144 {
145 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
146 MPP_RET ret = MPP_NOK;
147
148 if (p_hal && p_hal->api && p_hal->api->wait)
149 ret = p_hal->api->wait(hal, task);
150 return ret;
151 }
152
hal_av1d_reset(void * hal)153 MPP_RET hal_av1d_reset(void *hal)
154 {
155 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
156 MPP_RET ret = MPP_NOK;
157
158 if (p_hal && p_hal->api && p_hal->api->reset)
159 ret = p_hal->api->reset(hal);
160 return ret;
161 }
162
hal_av1d_flush(void * hal)163 MPP_RET hal_av1d_flush(void *hal)
164 {
165 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
166 MPP_RET ret = MPP_NOK;
167
168 if (p_hal && p_hal->api && p_hal->api->flush)
169 ret = p_hal->api->flush(hal);
170 return ret;
171 }
172
hal_av1d_control(void * hal,MpiCmd cmd_type,void * param)173 MPP_RET hal_av1d_control(void *hal, MpiCmd cmd_type, void *param)
174 {
175 Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
176 MPP_RET ret = MPP_NOK;
177
178 if (p_hal && p_hal->api && p_hal->api->control)
179 ret = p_hal->api->control(hal, cmd_type, param);
180 return ret;
181 }
182
183 const MppHalApi hal_api_av1d = {
184 .name = "av1d_vdpu",
185 .type = MPP_CTX_DEC,
186 .coding = MPP_VIDEO_CodingAV1,
187 .ctx_size = sizeof(Av1dHalCtx),
188 .flag = 0,
189 .init = hal_av1d_init,
190 .deinit = hal_av1d_deinit,
191 .reg_gen = hal_av1d_gen_regs,
192 .start = hal_av1d_start,
193 .wait = hal_av1d_wait,
194 .reset = hal_av1d_reset,
195 .flush = hal_av1d_flush,
196 .control = hal_av1d_control,
197 };
198