48     ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1);  in hal_vp8d_vdpu1_init()
84     cfg->dev            = ctx->dev;  in hal_vp8d_vdpu1_init()
89     if (ctx->dev) {  in hal_vp8d_vdpu1_init()
90         mpp_dev_deinit(ctx->dev);  in hal_vp8d_vdpu1_init()
91         ctx->dev = NULL;  in hal_vp8d_vdpu1_init()
124     if (ctx->dev) {  in hal_vp8d_vdpu1_deinit()
125         mpp_dev_deinit(ctx->dev);  in hal_vp8d_vdpu1_deinit()
126         ctx->dev = NULL;  in hal_vp8d_vdpu1_deinit()
273         mpp_dev_set_reg_offset(ctx->dev, 27, pic_param->stream_start_offset);  in hal_vp8d_dct_partition_cfg()
302                 mpp_dev_set_reg_offset(ctx->dev, 12, addr);  in hal_vp8d_dct_partition_cfg()
307                 mpp_dev_set_reg_offset(ctx->dev, 21 + i, addr);  in hal_vp8d_dct_partition_cfg()
312                 mpp_dev_set_reg_offset(ctx->dev, 22 + i, addr);  in hal_vp8d_dct_partition_cfg()
487         mpp_dev_set_reg_offset(ctx->dev, 14, (mb_width * mb_height) << 8);  in hal_vp8d_vdpu1_gen_regs()
504         mpp_dev_set_reg_offset(ctx->dev, 18, pic_param->ref_frame_sign_bias_golden);  in hal_vp8d_vdpu1_gen_regs()
516         mpp_dev_set_reg_offset(ctx->dev, 19, pic_param->ref_frame_sign_bias_altref);  in hal_vp8d_vdpu1_gen_regs()
520         mpp_dev_set_reg_offset(ctx->dev, 10, (pic_param->stVP8Segments.segmentation_enabled  in hal_vp8d_vdpu1_gen_regs()
648         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_vp8d_vdpu1_start()
658         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);  in hal_vp8d_vdpu1_start()
664         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);  in hal_vp8d_vdpu1_start()
684     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);  in hal_vp8d_vdpu1_wait()