48     ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2);  in hal_vp8d_vdpu2_init()
86     cfg->dev            = ctx->dev;  in hal_vp8d_vdpu2_init()
91     if (ctx->dev) {  in hal_vp8d_vdpu2_init()
92         mpp_dev_deinit(ctx->dev);  in hal_vp8d_vdpu2_init()
93         ctx->dev = NULL;  in hal_vp8d_vdpu2_init()
126     if (ctx->dev) {  in hal_vp8d_vdpu2_deinit()
127         mpp_dev_deinit(ctx->dev);  in hal_vp8d_vdpu2_deinit()
128         ctx->dev = NULL;  in hal_vp8d_vdpu2_deinit()
270         mpp_dev_set_reg_offset(ctx->dev, 145, pic_param->stream_start_offset);  in hal_vp8d_dct_partition_cfg()
299                 mpp_dev_set_reg_offset(ctx->dev, 64, addr);  in hal_vp8d_dct_partition_cfg()
303                 mpp_dev_set_reg_offset(ctx->dev, 139 + i, addr);  in hal_vp8d_dct_partition_cfg()
307                 mpp_dev_set_reg_offset(ctx->dev, 140 + i, addr);  in hal_vp8d_dct_partition_cfg()
480         mpp_dev_set_reg_offset(ctx->dev, 131, mb_width * mb_height);  in hal_vp8d_vdpu2_gen_regs()
498         mpp_dev_set_reg_offset(ctx->dev, 136, pic_param->ref_frame_sign_bias_golden);  in hal_vp8d_vdpu2_gen_regs()
511         mpp_dev_set_reg_offset(ctx->dev, 137, pic_param->ref_frame_sign_bias_altref);  in hal_vp8d_vdpu2_gen_regs()
515         mpp_dev_set_reg_offset(ctx->dev, 149, pic_param->stVP8Segments.segmentation_enabled  in hal_vp8d_vdpu2_gen_regs()
659         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_vp8d_vdpu2_start()
669         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);  in hal_vp8d_vdpu2_start()
675         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);  in hal_vp8d_vdpu2_start()
695     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);  in hal_vp8d_vdpu2_wait()