61     mpp_dev_set_reg_offset(ctx->dev, 77, hw_cfg->output_strm_offset);  in vp8e_vpu_frame_start()
73         mpp_dev_set_reg_offset(ctx->dev, 48, hw_cfg->input_lum_offset);  in vp8e_vpu_frame_start()
77         mpp_dev_set_reg_offset(ctx->dev, 49, hw_cfg->input_cb_offset);  in vp8e_vpu_frame_start()
81         mpp_dev_set_reg_offset(ctx->dev, 50, hw_cfg->input_cr_offset);  in vp8e_vpu_frame_start()
201     mpp_dev_set_reg_offset(ctx->dev, 44, hw_cfg->partition_offset[0]);  in vp8e_vpu_frame_start()
203     mpp_dev_set_reg_offset(ctx->dev, 45, hw_cfg->partition_offset[1]);  in vp8e_vpu_frame_start()
293     ret = mpp_dev_init(&cfg->dev, cfg->type);  in hal_vp8e_vepu2_init_v2()
298     ctx->dev = cfg->dev;  in hal_vp8e_vepu2_init_v2()
338     if (ctx->dev) {  in hal_vp8e_vepu2_deinit_v2()
339         mpp_dev_deinit(ctx->dev);  in hal_vp8e_vepu2_deinit_v2()
340         ctx->dev = NULL;  in hal_vp8e_vepu2_deinit_v2()
398         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);  in hal_vp8e_vepu2_start_v2()
408         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);  in hal_vp8e_vepu2_start_v2()
414         ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);  in hal_vp8e_vepu2_start_v2()
457     if (NULL == ctx->dev) {  in hal_vp8e_vepu2_wait_v2()
462     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);  in hal_vp8e_vepu2_wait_v2()