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Searched refs:tcr (Results 1 – 24 of 24) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dtimer.c27 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); in lpc32xx_timer_reset()
28 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_reset()
42 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); in lpc32xx_timer_count()
44 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_count()
/rk3399_rockchip-uboot/arch/arm/include/asm/armv8/
H A Dmmu.h105 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) in set_ttbr_tcr_mair() argument
110 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
114 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
118 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dtimer.c41 writel(0x0, &timer->tcr); in timer_init()
46 writel(2 << 22, &timer->tcr); in timer_init()
108 writel(0x0, &wdttimer->tcr); in davinci_hw_watchdog_enable()
114 writel(2 << 22, &wdttimer->tcr); in davinci_hw_watchdog_enable()
H A Dreset.c25 writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr); in reset_cpu()
/rk3399_rockchip-uboot/arch/m68k/include/asm/
H A Dtimer.h26 u16 tcr; /* 0x08 Capture register */ member
38 u32 tcr; /* 0x08 Capture register */
H A Dfsl_mcdmafec.h31 u32 tcr; /* 0x0C4 */ member
H A Dfec.h131 u32 tcr; /* 0x144 */ member
160 u32 tcr;
/rk3399_rockchip-uboot/drivers/net/
H A Dfsl_mcdmafec.c123 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); in dbg_fec_regs()
160 fecp->tcr = FEC_TCR_FDEN; in set_fec_duplex_speed()
165 fecp->tcr &= ~FEC_TCR_FDEN; in set_fec_duplex_speed()
265 fecp->tcr |= FEC_TCR_GTS; in fec_recv()
270 if (fecp->tcr & FEC_TCR_GTS) { in fec_recv()
273 fecp->tcr &= ~FEC_TCR_GTS; in fec_recv()
471 fecp->tcr |= FEC_TCR_GTS; in fec_halt()
H A Dmcffec.c93 fecp->tcr = FEC_TCR_FDEN; in setFecDuplexSpeed()
98 fecp->tcr &= ~FEC_TCR_FDEN; in setFecDuplexSpeed()
263 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); in dbgFecRegs()
H A Dat91_emac.c402 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); in at91emac_send()
403 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) in at91emac_send()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dcache_v8.c42 u64 tcr; in get_tcr() local
71 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; in get_tcr()
73 tcr = TCR_EL2_RSVD | (ips << 16); in get_tcr()
75 tcr = TCR_EL3_RSVD | (ips << 16); in get_tcr()
79 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; in get_tcr()
80 tcr |= TCR_T0SZ(va_bits); in get_tcr()
87 return tcr; in get_tcr()
/rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/
H A Dat91_pdc.h14 u32 tcr; /* 0x10C Transmit Counter Register */ member
H A Dat91_emac.h17 u32 tcr; member
H A Dat91_matrix.h53 u32 tcr; member
/rk3399_rockchip-uboot/arch/arm/mach-davinci/include/mach/
H A Dtimer_defs.h19 u_int32_t tcr; member
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h15 u32 tcr; /* Timer Control Register */ member
/rk3399_rockchip-uboot/arch/m68k/include/asm/coldfire/
H A Ddspi.h17 u32 tcr; /* 0x08 */ member
H A Dssi.h21 u32 tcr; member
/rk3399_rockchip-uboot/include/
H A Dfsl_dspi.h19 u32 tcr; /* 0x08 */ member
/rk3399_rockchip-uboot/drivers/usb/eth/
H A Dr8152.c56 unsigned short tcr; member
981 u16 tcr; in r8152b_get_version() local
985 tcr = (u16)(ocp_data & VERSION_MASK); in r8152b_get_version()
988 if (tcr == r8152_versions[i].tcr) { in r8152b_get_version()
997 debug("r8152 Unknown tcr version 0x%04x\n", tcr); in r8152b_get_version()
/rk3399_rockchip-uboot/drivers/mmc/
H A Dfsl_esdhc.c77 uint tcr; /* Tuning control register */ member
/rk3399_rockchip-uboot/arch/powerpc/include/asm/
H A Dimmap_86xx.h593 uint tcr; /* 0x41300 - Timer Control Register */ member
H A Dimmap_85xx.h694 u32 tcr; /* Timer Control */ member
/rk3399_rockchip-uboot/
H A DREADME4765 …tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0…
4772 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
4775 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
4778 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
4781 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0