1*3d357619SMasahiro Yamada /* 2*3d357619SMasahiro Yamada * Copyright (C) 2011 DENX Software Engineering GmbH 3*3d357619SMasahiro Yamada * Heiko Schocher <hs@denx.de> 4*3d357619SMasahiro Yamada * 5*3d357619SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*3d357619SMasahiro Yamada */ 7*3d357619SMasahiro Yamada #ifndef _TIMER_DEFS_H_ 8*3d357619SMasahiro Yamada #define _TIMER_DEFS_H_ 9*3d357619SMasahiro Yamada 10*3d357619SMasahiro Yamada struct davinci_timer { 11*3d357619SMasahiro Yamada u_int32_t pid12; 12*3d357619SMasahiro Yamada u_int32_t emumgt; 13*3d357619SMasahiro Yamada u_int32_t na1; 14*3d357619SMasahiro Yamada u_int32_t na2; 15*3d357619SMasahiro Yamada u_int32_t tim12; 16*3d357619SMasahiro Yamada u_int32_t tim34; 17*3d357619SMasahiro Yamada u_int32_t prd12; 18*3d357619SMasahiro Yamada u_int32_t prd34; 19*3d357619SMasahiro Yamada u_int32_t tcr; 20*3d357619SMasahiro Yamada u_int32_t tgcr; 21*3d357619SMasahiro Yamada u_int32_t wdtcr; 22*3d357619SMasahiro Yamada }; 23*3d357619SMasahiro Yamada 24*3d357619SMasahiro Yamada #define DV_TIMER_TCR_ENAMODE_MASK 3 25*3d357619SMasahiro Yamada 26*3d357619SMasahiro Yamada #define DV_TIMER_TCR_ENAMODE12_SHIFT 6 27*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CLKSRC12_SHIFT 8 28*3d357619SMasahiro Yamada #define DV_TIMER_TCR_READRSTMODE12_SHIFT 10 29*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CAPMODE12_SHIFT 11 30*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12 31*3d357619SMasahiro Yamada #define DV_TIMER_TCR_ENAMODE34_SHIFT 22 32*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CLKSRC34_SHIFT 24 33*3d357619SMasahiro Yamada #define DV_TIMER_TCR_READRSTMODE34_SHIFT 26 34*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CAPMODE34_SHIFT 27 35*3d357619SMasahiro Yamada #define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28 36*3d357619SMasahiro Yamada 37*3d357619SMasahiro Yamada #define DV_WDT_ENABLE_SYS_RESET 0x00020000 38*3d357619SMasahiro Yamada #define DV_WDT_TRIGGER_SYS_RESET 0x00020002 39*3d357619SMasahiro Yamada 40*3d357619SMasahiro Yamada #ifdef CONFIG_HW_WATCHDOG 41*3d357619SMasahiro Yamada void davinci_hw_watchdog_enable(void); 42*3d357619SMasahiro Yamada void davinci_hw_watchdog_reset(void); 43*3d357619SMasahiro Yamada #endif 44*3d357619SMasahiro Yamada #endif /* _TIMER_DEFS_H_ */ 45