xref: /rk3399_rockchip-uboot/arch/arm/mach-at91/include/mach/at91_pdc.h (revision b9cb64825b5e6efeb715abd8b48d9b12f98973e9)
1*af930827SMasahiro Yamada /*
2*af930827SMasahiro Yamada  * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
3*af930827SMasahiro Yamada  *
4*af930827SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
5*af930827SMasahiro Yamada  */
6*af930827SMasahiro Yamada 
7*af930827SMasahiro Yamada #ifndef AT91_PDC_H
8*af930827SMasahiro Yamada #define AT91_PDC_H
9*af930827SMasahiro Yamada 
10*af930827SMasahiro Yamada typedef struct at91_pdc {
11*af930827SMasahiro Yamada 	u32	rpr;		/* 0x100 Receive Pointer Register */
12*af930827SMasahiro Yamada 	u32	rcr;		/* 0x104 Receive Counter Register */
13*af930827SMasahiro Yamada 	u32	tpr;		/* 0x108 Transmit Pointer Register */
14*af930827SMasahiro Yamada 	u32	tcr;		/* 0x10C Transmit Counter Register */
15*af930827SMasahiro Yamada 	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
16*af930827SMasahiro Yamada 	u32	pncr;		/* 0x114 Receive Next Counter Register */
17*af930827SMasahiro Yamada 	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
18*af930827SMasahiro Yamada 	u32	tncr;		/* 0x11C Transmit Next Counter Register */
19*af930827SMasahiro Yamada 	u32	ptcr;		/* 0x120 Transfer Control Register */
20*af930827SMasahiro Yamada 	u32	ptsr;		/* 0x124 Transfer Status Register */
21*af930827SMasahiro Yamada } at91_pdc_t;
22*af930827SMasahiro Yamada 
23*af930827SMasahiro Yamada #endif
24