Searched refs:ppll_hz (Results 1 – 8 of 8) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3568.h | 41 ulong ppll_hz; member
48 ulong ppll_hz; member
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| H A D | cru_rk3528.h | 38 ulong ppll_hz; member
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| H A D | cru_rk3588.h | 44 ulong ppll_hz; member
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| H A D | cru_rk3576.h | 44 ulong ppll_hz; member
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3568.c | 259 return DIV_TO_RATE(priv->ppll_hz, div); in rk3568_i2c_get_pmuclk()
268 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
297 parent = priv->ppll_hz; in rk3568_pwm_get_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
347 parent = priv->ppll_hz; in rk3568_pmu_get_pmuclk()
358 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pmu_set_pmuclk()
374 if (!priv->ppll_hz) { in rk3568_pmuclk_get_rate()
375 printf("%s ppll=%lu\n", __func__, priv->ppll_hz); in rk3568_pmuclk_get_rate()
414 if (!priv->ppll_hz) { in rk3568_pmuclk_set_rate()
415 printf("%s ppll=%lu\n", __func__, priv->ppll_hz); in rk3568_pmuclk_set_rate()
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| H A D | clk_rk3588.c | 1487 return DIV_TO_RATE(priv->ppll_hz, div); in rk3588_pciephy_get_rate()
1504 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3588_pciephy_set_rate()
1549 if (!priv->ppll_hz) { in rk3588_clk_get_rate()
1550 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_get_rate()
1704 if (!priv->ppll_hz) { in rk3588_clk_set_rate()
1705 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
1741 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
2084 if (priv->ppll_hz != PPLL_HZ) { in rk3588_clk_init()
2087 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_init()
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| H A D | clk_rk3528.c | 275 return DIV_TO_RATE(priv->ppll_hz, div); in rk3528_ppll_matrix_get_rate()
314 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3528_ppll_matrix_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
1956 if (priv->ppll_hz != PPLL_HZ) { in rk3528_clk_init()
1960 priv->ppll_hz = PPLL_HZ; in rk3528_clk_init()
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| H A D | clk_rk3576.c | 2046 return priv->ppll_hz / (div + 1); in rk3576_ufs_ref_get_rate()
2062 if (!priv->ppll_hz) { in rk3576_clk_get_rate()
2063 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_get_rate()
2226 if (!priv->ppll_hz) { in rk3576_clk_set_rate()
2227 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_set_rate()
2263 priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], in rk3576_clk_set_rate()
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