| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 112 pll_rk3328, enumerator
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | 106 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3328_PLL_CON(0),
108 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3328_PLL_CON(8),
110 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3328_PLL_CON(16),
112 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3328_PLL_CON(24),
114 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3328_PLL_CON(40),
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| H A D | clk_rk3308.c | 76 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
80 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
82 [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
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| H A D | clk_rk3562.c | 47 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
49 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
51 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
53 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3562_PLL_CON(40),
55 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3562_PMU1_PLL_CON(0),
57 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3562_SUBDDR_PLL_CON(0),
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| H A D | clk_rv1106.c | 39 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1106_PLL_CON(0),
41 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1106_PLL_CON(16),
43 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1106_PLL_CON(8),
45 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1106_PLL_CON(24),
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| H A D | clk_rk3528.c | 66 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
72 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
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| H A D | clk_pll.c | 631 case pll_rk3328: in rockchip_pll_get_rate()
660 case pll_rk3328: in rockchip_pll_set_rate()
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| H A D | clk_rk3568.c | 68 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
70 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
72 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
74 [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
76 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
78 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
80 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
82 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
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| H A D | clk_rk3506.c | 67 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3506_PLL_CON(0),
69 [V0PLL] = PLL(pll_rk3328, PLL_V0PLL, RK3506_PLL_CON(8),
71 [V1PLL] = PLL(pll_rk3328, PLL_V1PLL, RK3506_PLL_CON(16),
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| H A D | clk_rv1126.c | 60 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0),
62 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8),
64 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
66 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24),
68 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),
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| H A D | clk_rv1126b.c | 44 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126B_PLL_CON(8),
46 [AUPLL] = PLL(pll_rk3328, PLL_AUPLL, RV1126B_PLL_CON(0),
48 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126B_PERIPLL_CON(0),
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| H A D | clk_rv1103b.c | 40 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1103B_PLL_CON(24),
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