| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | ftsdc010_mci.c | 165 uint32_t dcr; in ftsdc010_request() local
170 dcr = 0; in ftsdc010_request()
172 dcr |= FTSDC010_DCR_FIFO_RST; in ftsdc010_request()
174 writel(dcr, ®s->dcr); in ftsdc010_request()
187 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; in ftsdc010_request()
189 dcr |= FTSDC010_DCR_DATA_WRITE; in ftsdc010_request()
190 writel(dcr, ®s->dcr); in ftsdc010_request()
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| /rk3399_rockchip-uboot/drivers/rtc/ |
| H A D | imxdi.c | 33 u32 dcr; /* Control Reg */ member
170 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
171 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-stm32f7/ |
| H A D | gpt.h | 32 u32 dcr; member
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | stm32_qspi.c | 26 u32 dcr; /* 0x04 */ member
211 clrsetbits_le32(&priv->regs->dcr, in _stm32_qspi_set_flash_size()
570 clrsetbits_le32(&priv->regs->dcr, in stm32_qspi_set_speed()
587 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
589 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
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| /rk3399_rockchip-uboot/board/sysam/amcore/ |
| H A D | amcore.c | 83 out_be16(&dc->dcr, 0x8200 | RC); in dram_init()
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| /rk3399_rockchip-uboot/board/freescale/m5235evb/ |
| H A D | m5235evb.c | 57 out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | in dram_init()
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| /rk3399_rockchip-uboot/arch/nds32/lib/ |
| H A D | asm-offsets.c | 61 OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */ in main()
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| /rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/ |
| H A D | timer.c | 38 u32 dcr; member
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/ |
| H A D | immap_5307.h | 101 u16 dcr; member
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| H A D | immap_5235.h | 92 u16 dcr; /* 0x00 Control register */ member
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| H A D | immap_5275.h | 111 u32 dcr; member
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| /rk3399_rockchip-uboot/include/faraday/ |
| H A D | ftsdc010.h | 24 unsigned int dcr; /* 0x1c - data control reg */ member
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 103 writel(0x40b, &mctl_phy->dcr); in mctl_init()
105 writel(0x1000040b, &mctl_phy->dcr); in mctl_init()
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| H A D | dram_sun4i.c | 154 if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) == in mctl_get_number_of_lanes()
619 writel(reg_val, &dram->dcr); in dramc_init_helper()
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| /rk3399_rockchip-uboot/arch/m68k/include/asm/coldfire/ |
| H A D | lcd.h | 27 u32 dcr; /* 0x30 DMA Control Register */ member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun4i.h | 17 u32 dcr; /* 0x04 dram configuration register */ member
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| H A D | dram_sun9i.h | 106 u32 dcr; /* 0x88 DRAM configuration register */ member
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| H A D | dram_sun8i_a23.h | 181 u32 dcr; /* 0x44 */ member
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| H A D | dram_sun6i.h | 170 u32 dcr; /* 0x30 */ member
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3288.c | 328 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
344 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
584 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
587 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
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| H A D | sdram_rk3188.c | 286 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
527 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
530 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/ |
| H A D | sdram_rk3066.c | 275 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
514 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
517 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
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| /rk3399_rockchip-uboot/include/synopsys/ |
| H A D | dwcddr21mctl.h | 17 unsigned int dcr; /* DRAM Configuration */ member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | ddr_rk3288.h | 178 u32 dcr; member
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| /rk3399_rockchip-uboot/drivers/mtd/nand/raw/ |
| H A D | zynq_nand.c | 113 u32 dcr; /* 0x10 */ member
285 writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); in zynq_nand_init_nand_flash()
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