1e66c49faSVikas Manocha /* 2e66c49faSVikas Manocha * (C) Copyright 2016 3e66c49faSVikas Manocha * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4e66c49faSVikas Manocha * 5e66c49faSVikas Manocha * SPDX-License-Identifier: GPL-2.0+ 6e66c49faSVikas Manocha */ 7e66c49faSVikas Manocha 8e66c49faSVikas Manocha #ifndef _STM32_GPT_H 9e66c49faSVikas Manocha #define _STM32_GPT_H 10e66c49faSVikas Manocha 11e66c49faSVikas Manocha #include <asm/arch/stm32.h> 12e66c49faSVikas Manocha 13e66c49faSVikas Manocha struct gpt_regs { 14e66c49faSVikas Manocha u32 cr1; 15e66c49faSVikas Manocha u32 cr2; 16e66c49faSVikas Manocha u32 smcr; 17e66c49faSVikas Manocha u32 dier; 18e66c49faSVikas Manocha u32 sr; 19e66c49faSVikas Manocha u32 egr; 20e66c49faSVikas Manocha u32 ccmr1; 21e66c49faSVikas Manocha u32 ccmr2; 22e66c49faSVikas Manocha u32 ccer; 23e66c49faSVikas Manocha u32 cnt; 24e66c49faSVikas Manocha u32 psc; 25e66c49faSVikas Manocha u32 arr; 26e66c49faSVikas Manocha u32 reserved; 27e66c49faSVikas Manocha u32 ccr1; 28e66c49faSVikas Manocha u32 ccr2; 29e66c49faSVikas Manocha u32 ccr3; 30e66c49faSVikas Manocha u32 ccr4; 31e66c49faSVikas Manocha u32 reserved1; 32e66c49faSVikas Manocha u32 dcr; 33e66c49faSVikas Manocha u32 dmar; 34e66c49faSVikas Manocha u32 tim2_5_or; 35e66c49faSVikas Manocha }; 36e66c49faSVikas Manocha 37e66c49faSVikas Manocha struct gpt_regs *const gpt1_regs_ptr = 38e66c49faSVikas Manocha (struct gpt_regs *)TIM2_BASE; 39e66c49faSVikas Manocha 40e66c49faSVikas Manocha /* Timer control1 register */ 41*bad5188bSMichael Kurz #define GPT_CR1_CEN BIT(0) 42*bad5188bSMichael Kurz #define GPT_MODE_AUTO_RELOAD BIT(7) 43e66c49faSVikas Manocha 44e66c49faSVikas Manocha /* Auto reload register for free running config */ 45e66c49faSVikas Manocha #define GPT_FREE_RUNNING 0xFFFFFFFF 46e66c49faSVikas Manocha 47e66c49faSVikas Manocha /* Timer, HZ specific defines */ 48e66c49faSVikas Manocha #define CONFIG_STM32_HZ 1000 49e66c49faSVikas Manocha 50e66c49faSVikas Manocha /* Timer Event Generation registers */ 51*bad5188bSMichael Kurz #define TIM_EGR_UG BIT(0) 52e66c49faSVikas Manocha 53e66c49faSVikas Manocha #endif 54