Home
last modified time | relevance | path

Searched refs:ctrl (Results 1 – 25 of 302) sorted by relevance

12345678910>>...13

/rk3399_rockchip-uboot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c191 struct brcmnand_controller *ctrl; member
441 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) in nand_readreg() argument
443 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
446 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, in nand_writereg() argument
449 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
452 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) in brcmnand_revision_init() argument
458 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
461 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
462 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
463 ctrl->nand_version); in brcmnand_revision_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); in io_settings_lpddr2()
63 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); in io_settings_lpddr2()
64 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); in io_settings_lpddr2()
65 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); in io_settings_lpddr2()
66 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); in io_settings_lpddr2()
67 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); in io_settings_lpddr2()
68 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); in io_settings_lpddr2()
69 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); in io_settings_lpddr2()
70 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); in io_settings_lpddr2()
80 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); in io_settings_ddr3()
[all …]
H A Ddra7xx_iodelay.c22 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
24 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
36 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
39 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
150 cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET, in do_set_iodelay()
155 fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET, in do_set_iodelay()
180 writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_start()
183 ret = calibrate_iodelay((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
191 ret = update_delay_mechanism((*ctrl)->iodelay_config_base); in __recalibrate_iodelay_start()
210 writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + in __recalibrate_iodelay_end()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/microchip/
H A Dddr2.c67 static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, in ddr_set_arbiter() argument
74 writel(i * MIN_LIM_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
75 writel(param->min_limit, &ctrl->minlim); in ddr_set_arbiter()
78 writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
79 writel(param->req_period, &ctrl->reqprd); in ddr_set_arbiter()
82 writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
83 writel(param->min_cmd_acpt, &ctrl->mincmd); in ddr_set_arbiter()
101 static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, in host_load_cmd() argument
107 writel(hostcmd1, &ctrl->cmd10[cmd_idx]); in host_load_cmd()
108 writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); in host_load_cmd()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/
H A Dhwinit.c57 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); in do_io_settings()
58 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); in do_io_settings()
61 (*ctrl)->control_lpddr2io1_2); in do_io_settings()
62 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); in do_io_settings()
65 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); in do_io_settings()
66 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); in do_io_settings()
69 (*ctrl)->control_lpddr2io2_2); in do_io_settings()
70 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); in do_io_settings()
78 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { in do_io_settings()
81 (*ctrl)->control_ldosram_iva_voltage_ctrl); in do_io_settings()
[all …]
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dxhci-mem.c104 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl) in xhci_scratchpad_free() argument
106 if (!ctrl->scratchpad) in xhci_scratchpad_free()
109 ctrl->dcbaa->dev_context_ptrs[0] = 0; in xhci_scratchpad_free()
111 free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]); in xhci_scratchpad_free()
112 free(ctrl->scratchpad->sp_array); in xhci_scratchpad_free()
113 free(ctrl->scratchpad); in xhci_scratchpad_free()
114 ctrl->scratchpad = NULL; in xhci_scratchpad_free()
135 static void xhci_free_virt_devices(struct xhci_ctrl *ctrl) in xhci_free_virt_devices() argument
146 virt_dev = ctrl->devs[slot_id]; in xhci_free_virt_devices()
150 ctrl->dcbaa->dev_context_ptrs[slot_id] = 0; in xhci_free_virt_devices()
[all …]
H A Dxhci-ring.c36 static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, in last_trb() argument
39 if (ring == ctrl->event_ring) in last_trb()
55 static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl, in last_trb_on_last_seg() argument
60 if (ring == ctrl->event_ring) in last_trb_on_last_seg()
89 static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, in inc_enq() argument
102 while (last_trb(ctrl, ring, ring->enq_seg, next)) { in inc_enq()
103 if (ring != ctrl->event_ring) { in inc_enq()
129 if (last_trb_on_last_seg(ctrl, ring, in inc_enq()
147 static void inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring) in inc_deq() argument
155 if (last_trb(ctrl, ring, ring->deq_seg, ring->dequeue)) { in inc_deq()
[all …]
H A Dehci-hcd.c122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) in ehci_get_port_speed() argument
127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) in ehci_set_usbmode() argument
132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE); in ehci_set_usbmode()
143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, in ehci_powerup_fixup() argument
149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) in ehci_get_portsc_register() argument
151 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams)); in ehci_get_portsc_register()
160 return (uint32_t *)&ctrl->hcor->or_portsc[port]; in ehci_get_portsc_register()
179 static int ehci_reset(struct ehci_ctrl *ctrl) in ehci_reset() argument
184 cmd = ehci_readl(&ctrl->hcor->or_usbcmd); in ehci_reset()
186 ehci_writel(&ctrl->hcor->or_usbcmd, cmd); in ehci_reset()
[all …]
H A Dxhci.c454 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); in xhci_configure_endpoints() local
457 virt_dev = ctrl->devs[udev->slot_id]; in xhci_configure_endpoints()
461 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0, in xhci_configure_endpoints()
463 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); in xhci_configure_endpoints()
482 xhci_acknowledge_event(ctrl); in xhci_configure_endpoints()
505 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); in xhci_set_configuration() local
510 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; in xhci_set_configuration()
541 xhci_slot_copy(ctrl, in_ctx, out_ctx); in xhci_set_configuration()
542 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); in xhci_set_configuration()
546 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); in xhci_set_configuration()
[all …]
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dfsl_elbc_nand.c49 struct fsl_elbc_ctrl *ctrl; member
159 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in set_addr() local
160 fsl_lbc_t *lbc = ctrl->regs; in set_addr()
163 ctrl->page = page_addr; in set_addr()
179 ctrl->addr = priv->vbase + buf_num * 1024; in set_addr()
180 ctrl->index = column; in set_addr()
184 ctrl->index += priv->page_size ? 2048 : 512; in set_addr()
188 buf_num, ctrl->addr, priv->vbase, ctrl->index, in set_addr()
199 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_run_command() local
200 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_run_command()
[all …]
H A Dfsl_ifc_nand.c35 struct fsl_ifc_ctrl *ctrl; member
226 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in set_addr() local
227 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in set_addr()
230 ctrl->page = page_addr; in set_addr()
238 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); in set_addr()
239 ctrl->index = column; in set_addr()
243 ctrl->index += mtd->writesize; in set_addr()
247 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, in check_read_ecc() argument
260 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_run_command() local
261 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; in fsl_ifc_run_command()
[all …]
H A Dkirkwood_nand.c20 u32 ctrl; /* 0x10470 */ member
34 unsigned int ctrl) in kw_nand_hwcontrol() argument
42 if (ctrl & NAND_CLE) in kw_nand_hwcontrol()
44 else if (ctrl & NAND_ALE) in kw_nand_hwcontrol()
72 data = readl(&nf_reg->ctrl); in kw_nand_select_chip()
74 writel(data, &nf_reg->ctrl); in kw_nand_select_chip()
/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c24 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
26 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
27 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
44 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() local
48 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
49 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
55 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
68 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_mux_route() local
72 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
73 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-orion5x/
H A Dcpu.c95 writel(0, &winregs[0].ctrl); in orion5x_config_adr_windows()
101 ORION5X_WIN_ENABLE), &winregs[0].ctrl); in orion5x_config_adr_windows()
103 writel(0, &winregs[1].ctrl); in orion5x_config_adr_windows()
109 ORION5X_WIN_ENABLE), &winregs[1].ctrl); in orion5x_config_adr_windows()
111 writel(0, &winregs[2].ctrl); in orion5x_config_adr_windows()
115 ORION5X_WIN_ENABLE), &winregs[2].ctrl); in orion5x_config_adr_windows()
117 writel(0, &winregs[3].ctrl); in orion5x_config_adr_windows()
121 ORION5X_WIN_ENABLE), &winregs[3].ctrl); in orion5x_config_adr_windows()
123 writel(0, &winregs[4].ctrl); in orion5x_config_adr_windows()
127 ORION5X_WIN_ENABLE), &winregs[4].ctrl); in orion5x_config_adr_windows()
[all …]
/rk3399_rockchip-uboot/drivers/misc/
H A Drockchip-efuse.c92 u32 ctrl; /* 0x00 efuse control register */ member
191 sip_smc_secure_reg_write((ulong)&efuse->ctrl, in rockchip_rk3368_efuse_read()
195 res = sip_smc_secure_reg_read((ulong)&efuse->ctrl); in rockchip_rk3368_efuse_read()
196 sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 & in rockchip_rk3368_efuse_read()
199 res = sip_smc_secure_reg_read((ulong)&efuse->ctrl); in rockchip_rk3368_efuse_read()
200 sip_smc_secure_reg_write((ulong)&efuse->ctrl, res.a1 | in rockchip_rk3368_efuse_read()
205 res = sip_smc_secure_reg_read((ulong)&efuse->ctrl); in rockchip_rk3368_efuse_read()
206 sip_smc_secure_reg_write((ulong)&efuse->ctrl, in rockchip_rk3368_efuse_read()
213 res = sip_smc_secure_reg_read((ulong)&efuse->ctrl); in rockchip_rk3368_efuse_read()
214 sip_smc_secure_reg_write((ulong)&efuse->ctrl, in rockchip_rk3368_efuse_read()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/
H A Dtimer.c36 writel(GPT_CTRL_SWR, &gpt->ctrl); in timer_init()
41 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
44 writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR, in timer_init()
45 &gpt->ctrl); in timer_init()
46 writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl); in timer_init()
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx35/
H A Dtimer.c34 writel(GPTCR_SWR, &gpt->ctrl); in timer_init()
39 writel(0, &gpt->ctrl); /* We have no udelay by now */ in timer_init()
42 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, in timer_init()
43 &gpt->ctrl); in timer_init()
44 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); in timer_init()
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddevices.c18 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; variable
27 clrbits_le32(&ctrl->loop, in lpc32xx_uart_init()
37 clrsetbits_le32(&ctrl->clkmode, in lpc32xx_uart_init()
114 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); in lpc32xx_usb_init()
120 uint32_t ctrl = readl(&clk->i2cclk_ctrl); in lpc32xx_i2c_init() local
122 ctrl |= CLK_I2C1_ENABLE; in lpc32xx_i2c_init()
124 ctrl |= CLK_I2C2_ENABLE; in lpc32xx_i2c_init()
125 writel(ctrl, &clk->i2cclk_ctrl); in lpc32xx_i2c_init()
/rk3399_rockchip-uboot/drivers/fpga/
H A Dsocfpga_gen5.c27 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()
47 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
62 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
78 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
81 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()
84 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
99 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
117 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_init()
151 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
199 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/rk3399_rockchip-uboot/drivers/net/
H A Dftmac110.c215 chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK); in ftmac110_reset()
222 chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK); in ftmac110_reset()
223 chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER); in ftmac110_reset()
285 uint64_t ctrl; in ftmac110_send() local
298 ctrl = le64_to_cpu(txd->ctrl); in ftmac110_send()
299 if (ctrl & FTMAC110_TXD_OWNER) { in ftmac110_send()
310 ctrl &= FTMAC110_TXD_CLRMASK; in ftmac110_send()
312 ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS; in ftmac110_send()
314 ctrl |= FTMAC110_TXD_OWNER; in ftmac110_send()
316 txd->ctrl = cpu_to_le64(ctrl); in ftmac110_send()
[all …]
/rk3399_rockchip-uboot/drivers/pwm/
H A Drk_pwm.c162 u32 ctrl; in rk_pwm_set_config_v1() local
166 ctrl = readl(priv->base + regs->ctrl); in rk_pwm_set_config_v1()
169 ctrl |= RK_PWM_ENABLE; in rk_pwm_set_config_v1()
171 ctrl &= ~RK_PWM_ENABLE; in rk_pwm_set_config_v1()
179 ctrl |= PWM_LOCK; in rk_pwm_set_config_v1()
180 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config_v1()
192 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); in rk_pwm_set_config_v1()
193 ctrl |= priv->conf_polarity; in rk_pwm_set_config_v1()
202 ctrl &= ~PWM_LOCK; in rk_pwm_set_config_v1()
203 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config_v1()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-kirkwood/
H A Dcache.c14 u32 ctrl; in l2_cache_disable() local
16 ctrl = readfr_extra_feature_reg(); in l2_cache_disable()
17 ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN; in l2_cache_disable()
18 writefr_extra_feature_reg(ctrl); in l2_cache_disable()
/rk3399_rockchip-uboot/board/xes/common/
H A Dactl_nand.c17 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) in nand_addr_hwcontrol() argument
22 if (ctrl & NAND_CTRL_CHANGE) { in nand_addr_hwcontrol()
28 if (ctrl & NAND_CLE) in nand_addr_hwcontrol()
30 if (ctrl & NAND_ALE) in nand_addr_hwcontrol()
32 if (ctrl & NAND_NCE) in nand_addr_hwcontrol()
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c29 u32 ctrl; member
68 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
69 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
72 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
76 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
78 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
81 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
[all …]
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Df_dfu.c265 const struct usb_ctrlrequest *ctrl, in state_app_idle() argument
271 switch (ctrl->bRequest) { in state_app_idle()
292 const struct usb_ctrlrequest *ctrl, in state_app_detach() argument
298 switch (ctrl->bRequest) { in state_app_detach()
315 const struct usb_ctrlrequest *ctrl, in state_dfu_idle() argument
319 u16 w_value = le16_to_cpu(ctrl->wValue); in state_dfu_idle()
320 u16 len = le16_to_cpu(ctrl->wLength); in state_dfu_idle()
323 switch (ctrl->bRequest) { in state_dfu_idle()
375 const struct usb_ctrlrequest *ctrl, in state_dfu_dnload_sync() argument
381 switch (ctrl->bRequest) { in state_dfu_dnload_sync()
[all …]

12345678910>>...13