29 	u32 ctrl;  member
68 	writel(0, &phy->ctrl);  in sunxi_dw_hdmi_phy_init()
69 	setbits_le32(&phy->ctrl, BIT(0));  in sunxi_dw_hdmi_phy_init()
71 	setbits_le32(&phy->ctrl, BIT(16));  in sunxi_dw_hdmi_phy_init()
72 	setbits_le32(&phy->ctrl, BIT(1));  in sunxi_dw_hdmi_phy_init()
74 	setbits_le32(&phy->ctrl, BIT(2));  in sunxi_dw_hdmi_phy_init()
76 	setbits_le32(&phy->ctrl, BIT(3));  in sunxi_dw_hdmi_phy_init()
78 	setbits_le32(&phy->ctrl, BIT(19));  in sunxi_dw_hdmi_phy_init()
80 	setbits_le32(&phy->ctrl, BIT(18));  in sunxi_dw_hdmi_phy_init()
81 	setbits_le32(&phy->ctrl, 7 << 4);  in sunxi_dw_hdmi_phy_init()
92 	setbits_le32(&phy->ctrl, 0xf << 8);  in sunxi_dw_hdmi_phy_init()
93 	setbits_le32(&phy->ctrl, BIT(7));  in sunxi_dw_hdmi_phy_init()
104 	writel(0x01FF0F7F, &phy->ctrl);  in sunxi_dw_hdmi_phy_init()
162 		writel(0x01FFFF7F, &phy->ctrl);  in sunxi_dw_hdmi_phy_set()
176 		writel(0x01FFFF7F, &phy->ctrl);  in sunxi_dw_hdmi_phy_set()
190 		writel(0x01FFFF7F, &phy->ctrl);  in sunxi_dw_hdmi_phy_set()
204 		writel(0x01FFFF7F, &phy->ctrl);  in sunxi_dw_hdmi_phy_set()
317 	setbits_le32(&phy->ctrl, 0xf << 12);  in sunxi_dw_hdmi_enable()