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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dkeystone-k2hk-clocks.dtsi18 reg-names = "control";
26 reg-names = "control", "multiplier", "post-divider";
35 reg-names = "control";
44 reg-names = "control";
53 reg-names = "control";
62 reg-names = "control", "domain";
72 reg-names = "control", "domain";
82 reg-names = "control", "domain";
92 reg-names = "control", "domain";
102 reg-names = "control", "domain";
[all …]
H A Dkeystone-k2l-clocks.dtsi18 reg-names = "control";
26 reg-names = "control", "multiplier", "post-divider";
35 reg-names = "control";
44 reg-names = "control";
52 reg-names = "control", "domain";
63 reg-names = "control", "domain";
73 reg-names = "control", "domain";
83 reg-names = "control", "domain";
93 reg-names = "control", "domain";
103 reg-names = "control", "domain";
[all …]
H A Dkeystone-clocks.dtsi169 reg-names = "control", "domain";
180 reg-names = "control", "domain";
190 reg-names = "control", "domain";
201 reg-names = "control", "domain";
211 reg-names = "control", "domain";
221 reg-names = "control", "domain";
231 reg-names = "control", "domain";
241 reg-names = "control", "domain";
251 reg-names = "control", "domain";
261 reg-names = "control", "domain";
[all …]
H A Dkeystone-k2e-clocks.dtsi17 reg-names = "control", "multiplier", "post-divider";
26 reg-names = "control";
35 reg-names = "control";
44 reg-names = "control", "domain";
54 reg-names = "control", "domain";
64 reg-names = "control", "domain";
74 reg-names = "control", "domain";
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt13 All skew control options are specified in picoseconds. The minimum
19 - rxc-skew-ps : Skew control of RXC pad
20 - rxdv-skew-ps : Skew control of RX CTL pad
21 - txc-skew-ps : Skew control of TXC pad
22 - txen-skew-ps : Skew control of TX CTL pad
23 - rxd0-skew-ps : Skew control of RX data 0 pad
24 - rxd1-skew-ps : Skew control of RX data 1 pad
25 - rxd2-skew-ps : Skew control of RX data 2 pad
26 - rxd3-skew-ps : Skew control of RX data 3 pad
27 - txd0-skew-ps : Skew control of TX data 0 pad
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dzynq_i2c.c24 u32 control; member
87 (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); in zynq_i2c_init()
90 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS | in zynq_i2c_init()
165 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | in zynq_i2c_probe()
167 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_probe()
194 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | in zynq_i2c_read()
200 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
203 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); in zynq_i2c_read()
211 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
217 setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | in zynq_i2c_read()
[all …]
H A Dtegra_i2c.c38 struct i2c_control *control; member
156 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
161 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
174 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
178 static int wait_for_tx_fifo_empty(struct i2c_control *control) in wait_for_tx_fifo_empty() argument
184 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) in wait_for_tx_fifo_empty()
195 static int wait_for_rx_fifo_notempty(struct i2c_control *control) in wait_for_rx_fifo_notempty() argument
201 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) in wait_for_rx_fifo_notempty()
212 static int wait_for_transfer_complete(struct i2c_control *control) in wait_for_transfer_complete() argument
218 int_status = readl(&control->int_status); in wait_for_transfer_complete()
[all …]
H A Dmvtwsi.c57 u32 control; member
68 u32 control; member
265 int control, status; in twsi_wait() local
269 control = readl(&twsi->control); in twsi_wait()
270 if (control & MVTWSI_CONTROL_IFLG) { in twsi_wait()
277 control, status, expected_status); in twsi_wait()
282 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, in twsi_wait()
304 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); in twsi_start()
329 &twsi->control); in twsi_send()
350 int expected_status, status, control; in twsi_recv() local
[all …]
H A Di2c-cdns.c26 u32 control; member
220 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); in cdns_i2c_set_bus_speed()
223 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | in cdns_i2c_set_bus_speed()
236 setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO); in cdns_i2c_write_data()
237 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW); in cdns_i2c_write_data()
243 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); in cdns_i2c_write_data()
255 clrbits_le32(&regs->control, in cdns_i2c_write_data()
264 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); in cdns_i2c_write_data()
293 setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD); in cdns_i2c_read_data()
295 setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO | in cdns_i2c_read_data()
[all …]
/rk3399_rockchip-uboot/drivers/ata/
H A Dmvsata_ide.c138 u32 control; in mvsata_ide_initialize_port() local
148 control = readl(&port->scontrol); in mvsata_ide_initialize_port()
149 control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; in mvsata_ide_initialize_port()
150 writel(control, &port->scontrol); in mvsata_ide_initialize_port()
152 control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; in mvsata_ide_initialize_port()
153 writel(control, &port->scontrol); in mvsata_ide_initialize_port()
/rk3399_rockchip-uboot/drivers/ram/
H A Dstm32_sdram.c158 struct stm32_sdram_control *control; in stm32_sdram_init() local
171 control = params->bank_params[i].sdram_control; in stm32_sdram_init()
176 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
177 | control->cas_latency << FMC_SDCR_CAS_SHIFT in stm32_sdram_init()
178 | control->no_banks << FMC_SDCR_NB_SHIFT in stm32_sdram_init()
179 | control->memory_width << FMC_SDCR_MWID_SHIFT in stm32_sdram_init()
180 | control->no_rows << FMC_SDCR_NR_SHIFT in stm32_sdram_init()
181 | control->no_columns << FMC_SDCR_NC_SHIFT in stm32_sdram_init()
182 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT in stm32_sdram_init()
183 | control->rd_burst << FMC_SDCR_RBURST_SHIFT, in stm32_sdram_init()
[all …]
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_xuartlite.c32 unsigned int control; member
79 out_be32(&regs->control, 0); in uartlite_serial_probe()
80 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); in uartlite_serial_probe()
81 in_be32(&regs->control); in uartlite_serial_probe()
126 out_be32(&regs->control, 0); in _debug_uart_init()
127 out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); in _debug_uart_init()
128 in_be32(&regs->control); in _debug_uart_init()
H A Daltera_jtag_uart.c28 u32 control; /* Control register */ member
44 u32 st = readl(&regs->control); in altera_jtaguart_putc()
63 u32 st = readl(&regs->control); in altera_jtaguart_pending()
91 writel(ALTERA_JTAG_AC, &regs->control); /* clear AC flag */ in altera_jtaguart_probe()
143 u32 st = readl(&regs->control); in _debug_uart_putc()
H A Dserial_meson.c19 u32 control; member
51 val = readl(&uart->control); in meson_serial_init()
53 writel(val, &uart->control); in meson_serial_init()
55 writel(val, &uart->control); in meson_serial_init()
57 writel(val, &uart->control); in meson_serial_init()
H A Dserial_sti_asc.c32 u32 control; member
109 val = readl(&uart->control); in _sti_asc_serial_setbrg()
110 writel(val & ~RUN, &uart->control); in _sti_asc_serial_setbrg()
123 writel(val, &uart->control); in _sti_asc_serial_setbrg()
185 writel(val, &priv->regs->control); in sti_asc_serial_probe()
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dtimer.c19 unsigned int control; member
74 __raw_writel(GPTCR_SWR, &cur_gpt->control); in timer_init()
77 __raw_writel(0, &cur_gpt->control); in timer_init()
79 i = __raw_readl(&cur_gpt->control); in timer_init()
105 __raw_writel(i, &cur_gpt->control); in timer_init()
/rk3399_rockchip-uboot/drivers/pinctrl/mvebu/
H A DKconfig5 bool "Armada 37xx pin control driver"
7 Support pin multiplexing and pin configuration control on
12 bool "Armada 7k/8k pin control driver"
14 Support pin multiplexing and pin configuration control on
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c59 writel(0x00000193, &emc->control); in ddr_init()
62 writel(0x00000113, &emc->control); in ddr_init()
70 writel(0x00000093, &emc->control); in ddr_init()
73 writel(0x00000093, &emc->control); in ddr_init()
76 writel(0x00000010, &emc->control); in ddr_init()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dabb.c59 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, in abb_setup() argument
65 if (!setup || !control || !txdone) in abb_setup()
101 writel(0, control); in abb_setup()
113 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
/rk3399_rockchip-uboot/arch/microblaze/cpu/
H A Dtimer.c41 tmr->control = tmr->control | TIMER_INTERRUPT; in timer_isr()
81 tmr->control = TIMER_INTERRUPT | TIMER_RESET; in timer_init()
82 tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\ in timer_init()
/rk3399_rockchip-uboot/drivers/timer/
H A Daltera_timer.c26 u32 control; /* Timer control reg */ member
60 writel(0, &regs->control); in altera_timer_probe()
61 writel(ALTERA_TIMER_STOP, &regs->control); in altera_timer_probe()
65 writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control); in altera_timer_probe()
/rk3399_rockchip-uboot/drivers/net/
H A Dxilinx_axi_emac.c76 u32 control; /* DMACR */ member
339 temp = in_be32(&priv->dmatx->control); in axiemac_stop()
341 out_be32(&priv->dmatx->control, temp); in axiemac_stop()
343 temp = in_be32(&priv->dmarx->control); in axiemac_stop()
345 out_be32(&priv->dmarx->control, temp); in axiemac_stop()
422 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK); in axi_dma_init()
423 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK); in axi_dma_init()
429 if (!((in_be32(&priv->dmatx->control) | in axi_dma_init()
430 in_be32(&priv->dmarx->control)) in axi_dma_init()
459 temp = in_be32(&priv->dmarx->control); in axiemac_start()
[all …]
H A Dbcm-sf2-eth-gmac.c61 uint32_t control; in dma_ctrlflags() local
63 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()
64 writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()
70 writel(control, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()
400 uint32_t control, offset; in gmac_check_rx_done() local
455 control = readl(GMAC0_DMA_RX_CTRL_ADDR); in gmac_check_rx_done()
456 offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT; in gmac_check_rx_done()
527 uint32_t control; in gmac_enable_dma() local
540 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in gmac_enable_dma()
542 control |= D64_XC_XE; in gmac_enable_dma()
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/
H A DKconfig135 bool "QCA/Athores ar933x pin control driver"
138 Support pin multiplexing control on QCA/Athores ar933x SoCs.
140 both the GPIO definitions and pin control functions for each
156 can also control the multi-driver capability, pull-up and pull-down
181 bool "Microchip PIC32 pin-control and pin-mux driver"
188 contains both GPIO defintion and pin control functions.
191 bool "QCA/Athores qca953x pin control driver"
194 Support pin multiplexing control on QCA/Athores qca953x SoCs.
197 the GPIO definitions and pin control functions for each available
201 bool "Rockchip pin control driver"
[all …]
/rk3399_rockchip-uboot/board/gdsys/common/
H A Dihs_mdio.c22 FPGA_GET_REG(info->fpga, mdio.control, &val); in ihs_mdio_idle()
46 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_read()
65 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_write()

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