1d90a5a30SMasahiro Yamada# 2d90a5a30SMasahiro Yamada# PINCTRL infrastructure and drivers 3d90a5a30SMasahiro Yamada# 4d90a5a30SMasahiro Yamada 5d90a5a30SMasahiro Yamadamenu "Pin controllers" 6d90a5a30SMasahiro Yamada 7d90a5a30SMasahiro Yamadaconfig PINCTRL 8d90a5a30SMasahiro Yamada bool "Support pin controllers" 9d90a5a30SMasahiro Yamada depends on DM 10d90a5a30SMasahiro Yamada help 11d90a5a30SMasahiro Yamada This enables the basic support for pinctrl framework. You may want 12d90a5a30SMasahiro Yamada to enable some more options depending on what you want to do. 13d90a5a30SMasahiro Yamada 14d90a5a30SMasahiro Yamadaconfig PINCTRL_FULL 15d90a5a30SMasahiro Yamada bool "Support full pin controllers" 16d90a5a30SMasahiro Yamada depends on PINCTRL && OF_CONTROL 17d90a5a30SMasahiro Yamada default y 18d90a5a30SMasahiro Yamada help 19d90a5a30SMasahiro Yamada This provides Linux-compatible device tree interface for the pinctrl 20d90a5a30SMasahiro Yamada subsystem. This feature depends on device tree configuration because 21d90a5a30SMasahiro Yamada it parses a device tree to look for the pinctrl device which the 22d90a5a30SMasahiro Yamada peripheral device is associated with. 23d90a5a30SMasahiro Yamada 24d90a5a30SMasahiro Yamada If this option is disabled (it is the only possible choice for non-DT 25d90a5a30SMasahiro Yamada boards), the pinctrl core provides no systematic mechanism for 26d90a5a30SMasahiro Yamada identifying peripheral devices, applying needed pinctrl settings. 27d90a5a30SMasahiro Yamada It is totally up to the implementation of each low-level driver. 28d90a5a30SMasahiro Yamada You can save memory footprint in return for some limitations. 29d90a5a30SMasahiro Yamada 30d90a5a30SMasahiro Yamadaconfig PINCTRL_GENERIC 31d90a5a30SMasahiro Yamada bool "Support generic pin controllers" 32d90a5a30SMasahiro Yamada depends on PINCTRL_FULL 33d90a5a30SMasahiro Yamada default y 34d90a5a30SMasahiro Yamada help 35d90a5a30SMasahiro Yamada Say Y here if you want to use the pinctrl subsystem through the 36d90a5a30SMasahiro Yamada generic DT interface. If enabled, some functions become available 37d90a5a30SMasahiro Yamada to parse common properties such as "pins", "groups", "functions" and 38d90a5a30SMasahiro Yamada some pin configuration parameters. It would be easier if you only 39d90a5a30SMasahiro Yamada need the generic DT interface for pin muxing and pin configuration. 40d90a5a30SMasahiro Yamada If you need to handle vendor-specific DT properties, you can disable 41d90a5a30SMasahiro Yamada this option and implement your own set_state callback in the pinctrl 42d90a5a30SMasahiro Yamada operations. 43d90a5a30SMasahiro Yamada 44d90a5a30SMasahiro Yamadaconfig PINMUX 45d90a5a30SMasahiro Yamada bool "Support pin multiplexing controllers" 46d90a5a30SMasahiro Yamada depends on PINCTRL_GENERIC 47d90a5a30SMasahiro Yamada default y 48d90a5a30SMasahiro Yamada help 49d90a5a30SMasahiro Yamada This option enables pin multiplexing through the generic pinctrl 50458a0700SSimon Glass framework. Most SoCs have their own own multiplexing arrangement 51458a0700SSimon Glass where a single pin can be used for several functions. An SoC pinctrl 52458a0700SSimon Glass driver allows the required function to be selected for each pin. 53458a0700SSimon Glass The driver is typically controlled by the device tree. 54d90a5a30SMasahiro Yamada 55d90a5a30SMasahiro Yamadaconfig PINCONF 56d90a5a30SMasahiro Yamada bool "Support pin configuration controllers" 57d90a5a30SMasahiro Yamada depends on PINCTRL_GENERIC 58d90a5a30SMasahiro Yamada help 59d90a5a30SMasahiro Yamada This option enables pin configuration through the generic pinctrl 60d90a5a30SMasahiro Yamada framework. 61d90a5a30SMasahiro Yamada 62*fab50c1fSPatrick Delaunayconfig PINCONF_RECURSIVE 63*fab50c1fSPatrick Delaunay bool "Support recursive binding for pin configuration nodes" 64*fab50c1fSPatrick Delaunay depends on PINCTRL_FULL 65*fab50c1fSPatrick Delaunay default n if ARCH_STM32MP 66*fab50c1fSPatrick Delaunay default y 67*fab50c1fSPatrick Delaunay help 68*fab50c1fSPatrick Delaunay In the Linux pinctrl binding, the pin configuration nodes need not be 69*fab50c1fSPatrick Delaunay direct children of the pin controller device (may be grandchildren for 70*fab50c1fSPatrick Delaunay example). It is define is each individual pin controller device. 71*fab50c1fSPatrick Delaunay Say Y here if you want to keep this behavior with the pinconfig 72*fab50c1fSPatrick Delaunay u-class: all sub are recursivelly bounded. 73*fab50c1fSPatrick Delaunay If the option is disabled, this behavior is deactivated and only 74*fab50c1fSPatrick Delaunay the direct children of pin controller will be assumed as pin 75*fab50c1fSPatrick Delaunay configuration; you can save memory footprint when this feature is 76*fab50c1fSPatrick Delaunay no needed. 77*fab50c1fSPatrick Delaunay 78d90a5a30SMasahiro Yamadaconfig SPL_PINCTRL 790fa0abecSPhilipp Tomsich bool "Support pin controllers in SPL" 80d90a5a30SMasahiro Yamada depends on SPL && SPL_DM 81d90a5a30SMasahiro Yamada help 82d90a5a30SMasahiro Yamada This option is an SPL-variant of the PINCTRL option. 83d90a5a30SMasahiro Yamada See the help of PINCTRL for details. 84d90a5a30SMasahiro Yamada 85d90a5a30SMasahiro Yamadaconfig SPL_PINCTRL_FULL 86d90a5a30SMasahiro Yamada bool "Support full pin controllers in SPL" 87d90a5a30SMasahiro Yamada depends on SPL_PINCTRL && SPL_OF_CONTROL 88b9747696SVikas Manocha default n if TARGET_STM32F746_DISCO 89d90a5a30SMasahiro Yamada default y 90d90a5a30SMasahiro Yamada help 91d90a5a30SMasahiro Yamada This option is an SPL-variant of the PINCTRL_FULL option. 92d90a5a30SMasahiro Yamada See the help of PINCTRL_FULL for details. 93d90a5a30SMasahiro Yamada 94d90a5a30SMasahiro Yamadaconfig SPL_PINCTRL_GENERIC 95d90a5a30SMasahiro Yamada bool "Support generic pin controllers in SPL" 96d90a5a30SMasahiro Yamada depends on SPL_PINCTRL_FULL 97d90a5a30SMasahiro Yamada default y 98d90a5a30SMasahiro Yamada help 99d90a5a30SMasahiro Yamada This option is an SPL-variant of the PINCTRL_GENERIC option. 100d90a5a30SMasahiro Yamada See the help of PINCTRL_GENERIC for details. 101d90a5a30SMasahiro Yamada 102d90a5a30SMasahiro Yamadaconfig SPL_PINMUX 103d90a5a30SMasahiro Yamada bool "Support pin multiplexing controllers in SPL" 104d90a5a30SMasahiro Yamada depends on SPL_PINCTRL_GENERIC 105d90a5a30SMasahiro Yamada default y 106d90a5a30SMasahiro Yamada help 107d90a5a30SMasahiro Yamada This option is an SPL-variant of the PINMUX option. 108d90a5a30SMasahiro Yamada See the help of PINMUX for details. 109458a0700SSimon Glass The pinctrl subsystem can add a substantial overhead to the SPL 110458a0700SSimon Glass image since it typically requires quite a few tables either in the 111458a0700SSimon Glass driver or in the device tree. If this is acceptable and you need 112458a0700SSimon Glass to adjust pin multiplexing in SPL in order to boot into U-Boot, 113458a0700SSimon Glass enable this option. You will need to enable device tree in SPL 114458a0700SSimon Glass for this to work. 115d90a5a30SMasahiro Yamada 116d90a5a30SMasahiro Yamadaconfig SPL_PINCONF 117d90a5a30SMasahiro Yamada bool "Support pin configuration controllers in SPL" 118d90a5a30SMasahiro Yamada depends on SPL_PINCTRL_GENERIC 119d90a5a30SMasahiro Yamada help 120d90a5a30SMasahiro Yamada This option is an SPL-variant of the PINCONF option. 121d90a5a30SMasahiro Yamada See the help of PINCONF for details. 122d90a5a30SMasahiro Yamada 123*fab50c1fSPatrick Delaunayconfig SPL_PINCONF_RECURSIVE 124*fab50c1fSPatrick Delaunay bool "Support recursive binding for pin configuration nodes in SPL" 125*fab50c1fSPatrick Delaunay depends on SPL_PINCTRL_FULL 126*fab50c1fSPatrick Delaunay default n if ARCH_STM32MP 127*fab50c1fSPatrick Delaunay default y 128*fab50c1fSPatrick Delaunay help 129*fab50c1fSPatrick Delaunay This option is an SPL-variant of the PINCONF_RECURSIVE option. 130*fab50c1fSPatrick Delaunay See the help of PINCONF_RECURSIVE for details. 131*fab50c1fSPatrick Delaunay 132d90a5a30SMasahiro Yamadaif PINCTRL || SPL_PINCTRL 133d90a5a30SMasahiro Yamada 13451c7f348SPhilipp Tomsichconfig PINCTRL_AR933X 135a79d0643SWills Wang bool "QCA/Athores ar933x pin control driver" 136a79d0643SWills Wang depends on DM && SOC_AR933X 137a79d0643SWills Wang help 138a79d0643SWills Wang Support pin multiplexing control on QCA/Athores ar933x SoCs. 139a79d0643SWills Wang The driver is controlled by a device tree node which contains 140a79d0643SWills Wang both the GPIO definitions and pin control functions for each 141a79d0643SWills Wang available multiplex function. 142a79d0643SWills Wang 1439319a756SWenyou Yangconfig PINCTRL_AT91 1449319a756SWenyou Yang bool "AT91 pinctrl driver" 1459319a756SWenyou Yang depends on DM 1469319a756SWenyou Yang help 1479319a756SWenyou Yang This option is to enable the AT91 pinctrl driver for AT91 PIO 14851c7f348SPhilipp Tomsich controller. 14951c7f348SPhilipp Tomsich 15051c7f348SPhilipp Tomsich AT91 PIO controller is a combined gpio-controller, pin-mux and 15151c7f348SPhilipp Tomsich pin-config module. Each I/O pin may be dedicated as a general-purpose 15251c7f348SPhilipp Tomsich I/O or be assigned to a function of an embedded peripheral. Each I/O 15351c7f348SPhilipp Tomsich pin has a glitch filter providing rejection of glitches lower than 15451c7f348SPhilipp Tomsich one-half of peripheral clock cycle and a debouncing filter providing 15551c7f348SPhilipp Tomsich rejection of unwanted pulses from key or push button operations. You 15651c7f348SPhilipp Tomsich can also control the multi-driver capability, pull-up and pull-down 15751c7f348SPhilipp Tomsich feature on each I/O pin. 1589319a756SWenyou Yang 159ac72e174SWenyou Yangconfig PINCTRL_AT91PIO4 160ac72e174SWenyou Yang bool "AT91 PIO4 pinctrl driver" 161ac72e174SWenyou Yang depends on DM 162ac72e174SWenyou Yang help 163ac72e174SWenyou Yang This option is to enable the AT91 pinctrl driver for AT91 PIO4 164ac72e174SWenyou Yang controller which is available on SAMA5D2 SoC. 165ac72e174SWenyou Yang 1667530e4c6SWyon Biconfig PINCTRL_MAX96745 1677530e4c6SWyon Bi bool "Maxim MAX96745 pinctrl driver" 1687530e4c6SWyon Bi depends on DM && I2C_MUX_MAX96745 1697530e4c6SWyon Bi help 1707530e4c6SWyon Bi This option is to enable the pinctrl driver for Maxim 1717530e4c6SWyon Bi MAX96745. 1727530e4c6SWyon Bi 173f1563115SGuochun Huangconfig PINCTRL_MAX96755F 174f1563115SGuochun Huang bool "Maxim MAX96755F pinctrl driver" 175f1563115SGuochun Huang depends on DM && I2C_MUX_MAX96755F 176f1563115SGuochun Huang help 177f1563115SGuochun Huang This option is to enable the pinctrl driver for Maxim 178f1563115SGuochun Huang MAX96755F. 179f1563115SGuochun Huang 18051c7f348SPhilipp Tomsichconfig PINCTRL_PIC32 18151c7f348SPhilipp Tomsich bool "Microchip PIC32 pin-control and pin-mux driver" 18251c7f348SPhilipp Tomsich depends on DM && MACH_PIC32 18351c7f348SPhilipp Tomsich default y 18451c7f348SPhilipp Tomsich help 18551c7f348SPhilipp Tomsich Supports individual pin selection and configuration for each 18651c7f348SPhilipp Tomsich remappable peripheral available on Microchip PIC32 18751c7f348SPhilipp Tomsich SoCs. This driver is controlled by a device tree node which 18851c7f348SPhilipp Tomsich contains both GPIO defintion and pin control functions. 18951c7f348SPhilipp Tomsich 19051c7f348SPhilipp Tomsichconfig PINCTRL_QCA953X 19151c7f348SPhilipp Tomsich bool "QCA/Athores qca953x pin control driver" 19251c7f348SPhilipp Tomsich depends on DM && SOC_QCA953X 19351c7f348SPhilipp Tomsich help 19451c7f348SPhilipp Tomsich Support pin multiplexing control on QCA/Athores qca953x SoCs. 19551c7f348SPhilipp Tomsich 19651c7f348SPhilipp Tomsich The driver is controlled by a device tree node which contains both 19751c7f348SPhilipp Tomsich the GPIO definitions and pin control functions for each available 19851c7f348SPhilipp Tomsich multiplex function. 19951c7f348SPhilipp Tomsich 20049c55878SDavid Wuconfig PINCTRL_ROCKCHIP 20149c55878SDavid Wu bool "Rockchip pin control driver" 20249c55878SDavid Wu depends on PINCTRL_FULL && ARCH_ROCKCHIP 20349c55878SDavid Wu default y 20451c7f348SPhilipp Tomsich help 20549c55878SDavid Wu Support pin multiplexing control on Rockchip SoCs. 20651c7f348SPhilipp Tomsich 20751c7f348SPhilipp Tomsich The driver is controlled by a device tree node which contains both 20851c7f348SPhilipp Tomsich the GPIO definitions and pin control functions for each available 20951c7f348SPhilipp Tomsich multiplex function. 21051c7f348SPhilipp Tomsich 21149c55878SDavid Wuconfig SPL_PINCTRL_ROCKCHIP 21249c55878SDavid Wu bool "Support Rockchip pin controllers in SPL" 21349c55878SDavid Wu depends on SPL_PINCTRL_FULL && ARCH_ROCKCHIP 21449c55878SDavid Wu default y 2152241bfd6SKever Yang help 21649c55878SDavid Wu This option is an SPL-variant of the PINCTRL_ROCKCHIP option. 21749c55878SDavid Wu See the help of PINCTRL_ROCKCHIP for details. 21809aa7c46SAndy Yan 2199c6a3c67SMasahiro Yamadaconfig PINCTRL_SANDBOX 2209c6a3c67SMasahiro Yamada bool "Sandbox pinctrl driver" 2219c6a3c67SMasahiro Yamada depends on SANDBOX 2229c6a3c67SMasahiro Yamada help 22351c7f348SPhilipp Tomsich This enables pinctrl driver for sandbox. 2249c6a3c67SMasahiro Yamada 22551c7f348SPhilipp Tomsich Currently, this driver actually does nothing but print debug 22651c7f348SPhilipp Tomsich messages when pinctrl operations are invoked. 22794d53084SVikas Manocha 22844d5c371SFelix Brackconfig PINCTRL_SINGLE 22944d5c371SFelix Brack bool "Single register pin-control and pin-multiplex driver" 23044d5c371SFelix Brack depends on DM 23144d5c371SFelix Brack help 23244d5c371SFelix Brack This enables pinctrl driver for systems using a single register for 23344d5c371SFelix Brack pin configuration and multiplexing. TI's AM335X SoCs are examples of 23444d5c371SFelix Brack such systems. 23551c7f348SPhilipp Tomsich 23644d5c371SFelix Brack Depending on the platform make sure to also enable OF_TRANSLATE and 23744d5c371SFelix Brack eventually SPL_OF_TRANSLATE to get correct address translations. 23844d5c371SFelix Brack 23951c7f348SPhilipp Tomsichconfig PINCTRL_STI 24051c7f348SPhilipp Tomsich bool "STMicroelectronics STi pin-control and pin-mux driver" 24151c7f348SPhilipp Tomsich depends on DM && ARCH_STI 24251c7f348SPhilipp Tomsich default y 24351c7f348SPhilipp Tomsich help 24451c7f348SPhilipp Tomsich Support pin multiplexing control on STMicrolectronics STi SoCs. 24551c7f348SPhilipp Tomsich 24651c7f348SPhilipp Tomsich The driver is controlled by a device tree node which contains both 24751c7f348SPhilipp Tomsich the GPIO definitions and pin control functions for each available 24851c7f348SPhilipp Tomsich multiplex function. 24951c7f348SPhilipp Tomsich 25051c7f348SPhilipp Tomsichconfig PINCTRL_STM32 25151c7f348SPhilipp Tomsich bool "ST STM32 pin control driver" 25251c7f348SPhilipp Tomsich depends on DM 25351c7f348SPhilipp Tomsich help 25451c7f348SPhilipp Tomsich Supports pin multiplexing control on stm32 SoCs. 25551c7f348SPhilipp Tomsich 25651c7f348SPhilipp Tomsich The driver is controlled by a device tree node which contains both 25751c7f348SPhilipp Tomsich the GPIO definitions and pin control functions for each available 25851c7f348SPhilipp Tomsich multiplex function. 25951c7f348SPhilipp Tomsich 2604f0e44e4Smaxims@google.comconfig ASPEED_AST2500_PINCTRL 2614f0e44e4Smaxims@google.com bool "Aspeed AST2500 pin control driver" 2624f0e44e4Smaxims@google.com depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 2634f0e44e4Smaxims@google.com default y 2644f0e44e4Smaxims@google.com help 2654f0e44e4Smaxims@google.com Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses 2664f0e44e4Smaxims@google.com Generic Pinctrl framework and is compatible with the Linux driver, 2674f0e44e4Smaxims@google.com i.e. it uses the same device tree configuration. 2684f0e44e4Smaxims@google.com 269d90a5a30SMasahiro Yamadaendif 270d90a5a30SMasahiro Yamada 271677b5358SBeniamino Galvanisource "drivers/pinctrl/meson/Kconfig" 272745df68dSPeng Fansource "drivers/pinctrl/nxp/Kconfig" 2735dc626f8SMasahiro Yamadasource "drivers/pinctrl/uniphier/Kconfig" 27416ca80adSThomas Abrahamsource "drivers/pinctrl/exynos/Kconfig" 275656e6cc8SKonstantin Porotchkinsource "drivers/pinctrl/mvebu/Kconfig" 2765dc626f8SMasahiro Yamada 277d90a5a30SMasahiro Yamadaendmenu 278