xref: /rk3399_rockchip-uboot/drivers/serial/serial_meson.c (revision a821c4af79e4f5ce9b629b20473863397bbe9b10)
1bfcef28aSBeniamino Galvani /*
2bfcef28aSBeniamino Galvani  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3bfcef28aSBeniamino Galvani  *
4bfcef28aSBeniamino Galvani  * SPDX-License-Identifier:	GPL-2.0+
5bfcef28aSBeniamino Galvani  */
6bfcef28aSBeniamino Galvani 
7bfcef28aSBeniamino Galvani #include <common.h>
8bfcef28aSBeniamino Galvani #include <dm.h>
9bfcef28aSBeniamino Galvani #include <errno.h>
10bfcef28aSBeniamino Galvani #include <fdtdec.h>
11bfcef28aSBeniamino Galvani #include <linux/compiler.h>
12bfcef28aSBeniamino Galvani #include <serial.h>
13bfcef28aSBeniamino Galvani 
14bfcef28aSBeniamino Galvani DECLARE_GLOBAL_DATA_PTR;
15bfcef28aSBeniamino Galvani 
16bfcef28aSBeniamino Galvani struct meson_uart {
17bfcef28aSBeniamino Galvani 	u32 wfifo;
18bfcef28aSBeniamino Galvani 	u32 rfifo;
19bfcef28aSBeniamino Galvani 	u32 control;
20bfcef28aSBeniamino Galvani 	u32 status;
21bfcef28aSBeniamino Galvani 	u32 misc;
22bfcef28aSBeniamino Galvani };
23bfcef28aSBeniamino Galvani 
24bfcef28aSBeniamino Galvani struct meson_serial_platdata {
25bfcef28aSBeniamino Galvani 	struct meson_uart *reg;
26bfcef28aSBeniamino Galvani };
27bfcef28aSBeniamino Galvani 
28bfcef28aSBeniamino Galvani /* AML_UART_STATUS bits */
29bfcef28aSBeniamino Galvani #define AML_UART_PARITY_ERR		BIT(16)
30bfcef28aSBeniamino Galvani #define AML_UART_FRAME_ERR		BIT(17)
31bfcef28aSBeniamino Galvani #define AML_UART_TX_FIFO_WERR		BIT(18)
32bfcef28aSBeniamino Galvani #define AML_UART_RX_EMPTY		BIT(20)
33bfcef28aSBeniamino Galvani #define AML_UART_TX_FULL		BIT(21)
34bfcef28aSBeniamino Galvani #define AML_UART_TX_EMPTY		BIT(22)
35bfcef28aSBeniamino Galvani #define AML_UART_XMIT_BUSY		BIT(25)
36bfcef28aSBeniamino Galvani #define AML_UART_ERR			(AML_UART_PARITY_ERR | \
37bfcef28aSBeniamino Galvani 					 AML_UART_FRAME_ERR  | \
38bfcef28aSBeniamino Galvani 					 AML_UART_TX_FIFO_WERR)
39bfcef28aSBeniamino Galvani 
40bfcef28aSBeniamino Galvani /* AML_UART_CONTROL bits */
41bfcef28aSBeniamino Galvani #define AML_UART_TX_EN			BIT(12)
42bfcef28aSBeniamino Galvani #define AML_UART_RX_EN			BIT(13)
43bfcef28aSBeniamino Galvani #define AML_UART_TX_RST			BIT(22)
44bfcef28aSBeniamino Galvani #define AML_UART_RX_RST			BIT(23)
45bfcef28aSBeniamino Galvani #define AML_UART_CLR_ERR		BIT(24)
46bfcef28aSBeniamino Galvani 
meson_serial_init(struct meson_uart * uart)47bfcef28aSBeniamino Galvani static void meson_serial_init(struct meson_uart *uart)
48bfcef28aSBeniamino Galvani {
49bfcef28aSBeniamino Galvani 	u32 val;
50bfcef28aSBeniamino Galvani 
51bfcef28aSBeniamino Galvani 	val = readl(&uart->control);
52bfcef28aSBeniamino Galvani 	val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
53bfcef28aSBeniamino Galvani 	writel(val, &uart->control);
54bfcef28aSBeniamino Galvani 	val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
55bfcef28aSBeniamino Galvani 	writel(val, &uart->control);
56bfcef28aSBeniamino Galvani 	val |= (AML_UART_RX_EN | AML_UART_TX_EN);
57bfcef28aSBeniamino Galvani 	writel(val, &uart->control);
58bfcef28aSBeniamino Galvani }
59bfcef28aSBeniamino Galvani 
meson_serial_probe(struct udevice * dev)60bfcef28aSBeniamino Galvani static int meson_serial_probe(struct udevice *dev)
61bfcef28aSBeniamino Galvani {
62bfcef28aSBeniamino Galvani 	struct meson_serial_platdata *plat = dev->platdata;
63bfcef28aSBeniamino Galvani 	struct meson_uart *const uart = plat->reg;
64bfcef28aSBeniamino Galvani 
65bfcef28aSBeniamino Galvani 	meson_serial_init(uart);
66bfcef28aSBeniamino Galvani 
67bfcef28aSBeniamino Galvani 	return 0;
68bfcef28aSBeniamino Galvani }
69bfcef28aSBeniamino Galvani 
meson_serial_getc(struct udevice * dev)70bfcef28aSBeniamino Galvani static int meson_serial_getc(struct udevice *dev)
71bfcef28aSBeniamino Galvani {
72bfcef28aSBeniamino Galvani 	struct meson_serial_platdata *plat = dev->platdata;
73bfcef28aSBeniamino Galvani 	struct meson_uart *const uart = plat->reg;
74bfcef28aSBeniamino Galvani 
75bfcef28aSBeniamino Galvani 	if (readl(&uart->status) & AML_UART_RX_EMPTY)
76bfcef28aSBeniamino Galvani 		return -EAGAIN;
77bfcef28aSBeniamino Galvani 
78bfcef28aSBeniamino Galvani 	return readl(&uart->rfifo) & 0xff;
79bfcef28aSBeniamino Galvani }
80bfcef28aSBeniamino Galvani 
meson_serial_putc(struct udevice * dev,const char ch)81bfcef28aSBeniamino Galvani static int meson_serial_putc(struct udevice *dev, const char ch)
82bfcef28aSBeniamino Galvani {
83bfcef28aSBeniamino Galvani 	struct meson_serial_platdata *plat = dev->platdata;
84bfcef28aSBeniamino Galvani 	struct meson_uart *const uart = plat->reg;
85bfcef28aSBeniamino Galvani 
86bfcef28aSBeniamino Galvani 	if (readl(&uart->status) & AML_UART_TX_FULL)
87bfcef28aSBeniamino Galvani 		return -EAGAIN;
88bfcef28aSBeniamino Galvani 
89bfcef28aSBeniamino Galvani 	writel(ch, &uart->wfifo);
90bfcef28aSBeniamino Galvani 
91bfcef28aSBeniamino Galvani 	return 0;
92bfcef28aSBeniamino Galvani }
93bfcef28aSBeniamino Galvani 
meson_serial_pending(struct udevice * dev,bool input)94bfcef28aSBeniamino Galvani static int meson_serial_pending(struct udevice *dev, bool input)
95bfcef28aSBeniamino Galvani {
96bfcef28aSBeniamino Galvani 	struct meson_serial_platdata *plat = dev->platdata;
97bfcef28aSBeniamino Galvani 	struct meson_uart *const uart = plat->reg;
98bfcef28aSBeniamino Galvani 	uint32_t status = readl(&uart->status);
99bfcef28aSBeniamino Galvani 
100bfcef28aSBeniamino Galvani 	if (input)
101bfcef28aSBeniamino Galvani 		return !(status & AML_UART_RX_EMPTY);
102bfcef28aSBeniamino Galvani 	else
103bfcef28aSBeniamino Galvani 		return !(status & AML_UART_TX_FULL);
104bfcef28aSBeniamino Galvani }
105bfcef28aSBeniamino Galvani 
meson_serial_ofdata_to_platdata(struct udevice * dev)106bfcef28aSBeniamino Galvani static int meson_serial_ofdata_to_platdata(struct udevice *dev)
107bfcef28aSBeniamino Galvani {
108bfcef28aSBeniamino Galvani 	struct meson_serial_platdata *plat = dev->platdata;
109bfcef28aSBeniamino Galvani 	fdt_addr_t addr;
110bfcef28aSBeniamino Galvani 
111*a821c4afSSimon Glass 	addr = devfdt_get_addr(dev);
112bfcef28aSBeniamino Galvani 	if (addr == FDT_ADDR_T_NONE)
113bfcef28aSBeniamino Galvani 		return -EINVAL;
114bfcef28aSBeniamino Galvani 
115bfcef28aSBeniamino Galvani 	plat->reg = (struct meson_uart *)addr;
116bfcef28aSBeniamino Galvani 
117bfcef28aSBeniamino Galvani 	return 0;
118bfcef28aSBeniamino Galvani }
119bfcef28aSBeniamino Galvani 
120bfcef28aSBeniamino Galvani static const struct dm_serial_ops meson_serial_ops = {
121bfcef28aSBeniamino Galvani 	.putc = meson_serial_putc,
122bfcef28aSBeniamino Galvani 	.pending = meson_serial_pending,
123bfcef28aSBeniamino Galvani 	.getc = meson_serial_getc,
124bfcef28aSBeniamino Galvani };
125bfcef28aSBeniamino Galvani 
126bfcef28aSBeniamino Galvani static const struct udevice_id meson_serial_ids[] = {
127bfcef28aSBeniamino Galvani 	{ .compatible = "amlogic,meson-uart" },
128bfcef28aSBeniamino Galvani 	{ }
129bfcef28aSBeniamino Galvani };
130bfcef28aSBeniamino Galvani 
131bfcef28aSBeniamino Galvani U_BOOT_DRIVER(serial_meson) = {
132bfcef28aSBeniamino Galvani 	.name		= "serial_meson",
133bfcef28aSBeniamino Galvani 	.id		= UCLASS_SERIAL,
134bfcef28aSBeniamino Galvani 	.of_match	= meson_serial_ids,
135bfcef28aSBeniamino Galvani 	.probe		= meson_serial_probe,
136bfcef28aSBeniamino Galvani 	.ops		= &meson_serial_ops,
137bfcef28aSBeniamino Galvani 	.flags		= DM_FLAG_PRE_RELOC,
138bfcef28aSBeniamino Galvani 	.ofdata_to_platdata = meson_serial_ofdata_to_platdata,
139bfcef28aSBeniamino Galvani 	.platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
140bfcef28aSBeniamino Galvani };
141bfcef28aSBeniamino Galvani 
142bfcef28aSBeniamino Galvani #ifdef CONFIG_DEBUG_UART_MESON
143bfcef28aSBeniamino Galvani 
144bfcef28aSBeniamino Galvani #include <debug_uart.h>
145bfcef28aSBeniamino Galvani 
_debug_uart_init(void)146bfcef28aSBeniamino Galvani static inline void _debug_uart_init(void)
147bfcef28aSBeniamino Galvani {
148bfcef28aSBeniamino Galvani }
149bfcef28aSBeniamino Galvani 
_debug_uart_putc(int ch)150bfcef28aSBeniamino Galvani static inline void _debug_uart_putc(int ch)
151bfcef28aSBeniamino Galvani {
152bfcef28aSBeniamino Galvani 	struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
153bfcef28aSBeniamino Galvani 
154bfcef28aSBeniamino Galvani 	while (readl(&regs->status) & AML_UART_TX_FULL)
155bfcef28aSBeniamino Galvani 		;
156bfcef28aSBeniamino Galvani 
157bfcef28aSBeniamino Galvani 	writel(ch, &regs->wfifo);
158bfcef28aSBeniamino Galvani }
159bfcef28aSBeniamino Galvani 
160bfcef28aSBeniamino Galvani DEBUG_UART_FUNCS
161bfcef28aSBeniamino Galvani 
162bfcef28aSBeniamino Galvani #endif
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