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Searched refs:channel (Results 1 – 25 of 208) sorted by relevance

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/rk3399_rockchip-uboot/drivers/dma/
H A DMCD_dmaApi.c47 static void MCD_resmActions(int channel);
309 int MCD_dmaStatus(int channel) in MCD_dmaStatus() argument
313 if ((channel < 0) || (channel >= NCHANNELS)) in MCD_dmaStatus()
316 tcrValue = MCD_dmaBar->taskControl[channel]; in MCD_dmaStatus()
319 if (MCD_chStatus[channel] == MCD_RUNNING in MCD_dmaStatus()
320 || MCD_chStatus[channel] == MCD_IDLE) in MCD_dmaStatus()
321 MCD_chStatus[channel] = MCD_DONE; in MCD_dmaStatus()
325 if (MCD_chStatus[channel] == MCD_RUNNING in MCD_dmaStatus()
326 || MCD_chStatus[channel] == MCD_IDLE) { in MCD_dmaStatus()
330 if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) in MCD_dmaStatus()
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H A Dapbh_dma.c30 int mxs_dma_validate_chan(int channel) in mxs_dma_validate_chan() argument
34 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) in mxs_dma_validate_chan()
37 pchan = mxs_dma_channels + channel; in mxs_dma_validate_chan()
66 static int mxs_dma_read_semaphore(int channel) in mxs_dma_read_semaphore() argument
73 ret = mxs_dma_validate_chan(channel); in mxs_dma_read_semaphore()
77 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); in mxs_dma_read_semaphore()
109 static int mxs_dma_enable(int channel) in mxs_dma_enable() argument
118 ret = mxs_dma_validate_chan(channel); in mxs_dma_enable()
122 pchan = mxs_dma_channels + channel; in mxs_dma_enable()
137 sem = mxs_dma_read_semaphore(channel); in mxs_dma_enable()
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H A Dlpc32xx_dma.c94 int lpc32xx_dma_start_xfer(unsigned int channel, in lpc32xx_dma_start_xfer() argument
97 if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) || in lpc32xx_dma_start_xfer()
98 (channel >= DMA_NO_OF_CHANNELS))) { in lpc32xx_dma_start_xfer()
99 pr_err("Request for xfer on unallocated channel %d", channel); in lpc32xx_dma_start_xfer()
102 writel(BIT_MASK(channel), &dma->int_tc_clear); in lpc32xx_dma_start_xfer()
103 writel(BIT_MASK(channel), &dma->int_err_clear); in lpc32xx_dma_start_xfer()
104 writel(desc->dma_src, &dma->dma_chan[channel].src_addr); in lpc32xx_dma_start_xfer()
105 writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); in lpc32xx_dma_start_xfer()
106 writel(desc->next_lli, &dma->dma_chan[channel].lli); in lpc32xx_dma_start_xfer()
107 writel(desc->next_ctrl, &dma->dma_chan[channel].control); in lpc32xx_dma_start_xfer()
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H A DMCD_tasksInit.c23 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainNoEu() argument
25 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainNoEu()
53 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainNoEu()
61 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleNoEu() argument
63 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaSingleNoEu()
84 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaSingleNoEu()
91 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaChainEu() argument
93 volatile TaskTableEntry *taskChan = taskTable + channel; in MCD_startDmaChainEu()
124 MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; in MCD_startDmaChainEu()
132 volatile TaskTableEntry * taskTable, int channel) in MCD_startDmaSingleEu() argument
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/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dmrc_util.c127 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane) in training_message() argument
130 DPF(D_INFO, "CH%01X RK%01X BL%01X\n", channel, rank, byte_lane); in training_message()
138 void set_rcvn(uint8_t channel, uint8_t rank, in set_rcvn() argument
148 channel, rank, byte_lane, pi_count); in set_rcvn()
156 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
172 channel * DDRIODQ_CH_OFFSET); in set_rcvn()
183 channel * DDRIODQ_CH_OFFSET; in set_rcvn()
201 training_message(channel, rank, byte_lane); in set_rcvn()
214 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) in get_rcvn() argument
228 channel * DDRIODQ_CH_OFFSET; in get_rcvn()
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H A Dmrc_util.h84 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
86 void set_rcvn(uint8_t channel, uint8_t rank,
88 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
89 void set_rdqs(uint8_t channel, uint8_t rank,
91 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
92 void set_wdqs(uint8_t channel, uint8_t rank,
94 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
95 void set_wdq(uint8_t channel, uint8_t rank,
97 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
98 void set_wcmd(uint8_t channel, uint32_t pi_count);
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/rk3399_rockchip-uboot/drivers/pwm/
H A Dexynos_pwm.c21 static int exynos_pwm_set_config(struct udevice *dev, uint channel, in exynos_pwm_set_config() argument
31 if (channel >= 5) in exynos_pwm_set_config()
34 __func__, dev->name, channel, period_ns, duty_ns); in exynos_pwm_set_config()
37 prescaler = (channel < 2 ? val : (val >> 8)) & 0xff; in exynos_pwm_set_config()
38 div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf; in exynos_pwm_set_config()
43 if (channel < 4) { in exynos_pwm_set_config()
48 offset = channel * 3; in exynos_pwm_set_config()
54 tcon |= TCON_UPDATE(channel); in exynos_pwm_set_config()
55 if (channel < 4) in exynos_pwm_set_config()
56 tcon |= TCON_AUTO_RELOAD(channel); in exynos_pwm_set_config()
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H A Dsandbox_pwm.c31 static int sandbox_pwm_set_config(struct udevice *dev, uint channel, in sandbox_pwm_set_config() argument
37 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()
39 chan = &priv->chan[channel]; in sandbox_pwm_set_config()
46 static int sandbox_pwm_set_enable(struct udevice *dev, uint channel, in sandbox_pwm_set_enable() argument
52 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()
54 chan = &priv->chan[channel]; in sandbox_pwm_set_enable()
60 static int sandbox_pwm_set_invert(struct udevice *dev, uint channel, in sandbox_pwm_set_invert() argument
66 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
68 chan = &priv->chan[channel]; in sandbox_pwm_set_invert()
H A Dtegra_pwm.c20 static int tegra_pwm_set_config(struct udevice *dev, uint channel, in tegra_pwm_set_config() argument
28 if (channel >= 4) in tegra_pwm_set_config()
30 debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); in tegra_pwm_set_config()
38 writel(reg, &regs[channel].control); in tegra_pwm_set_config()
44 static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable) in tegra_pwm_set_enable() argument
49 if (channel >= 4) in tegra_pwm_set_enable()
51 debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel); in tegra_pwm_set_enable()
52 clrsetbits_le32(&regs[channel].control, PWM_ENABLE_MASK, in tegra_pwm_set_enable()
H A Dpwm-uclass.c12 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity) in pwm_set_invert() argument
19 return ops->set_invert(dev, channel, polarity); in pwm_set_invert()
22 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns, in pwm_set_config() argument
30 return ops->set_config(dev, channel, period_ns, duty_ns); in pwm_set_config()
33 int pwm_set_enable(struct udevice *dev, uint channel, bool enable) in pwm_set_enable() argument
40 return ops->set_enable(dev, channel, enable); in pwm_set_enable()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3399.c86 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, in rkclk_ddr_reset() argument
89 channel &= 0x1; in rkclk_ddr_reset()
92 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
93 CRU_SFTRST_DDR_PHY(channel, phy), in rkclk_ddr_reset()
98 u32 channel) in phy_pctrl_reset() argument
100 rkclk_ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
102 rkclk_ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
104 rkclk_ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
139 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
143 &sdram_params->ch[channel]; in set_memory_map()
[all …]
H A Dsdram_rk3288.c124 int channel) in phy_pctrl_reset() argument
128 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
140 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
199 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable) in ddr_set_enable() argument
204 val = 1 << (channel ? DDR1_16BIT_EN_SHIFT : in ddr_set_enable()
208 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT), in ddr_set_enable()
212 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel, in ddr_set_ddr3_mode() argument
217 mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT); in ddr_set_ddr3_mode()
218 val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT : in ddr_set_ddr3_mode()
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H A Dsdram_rk3188.c125 int channel) in phy_pctrl_reset() argument
129 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
141 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
143 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
200 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) in ddr_set_enable() argument
210 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, in ddr_set_ddr3_mode() argument
229 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
250 ddr_set_ddr3_mode(grf, channel, true); in pctl_cfg()
251 ddr_set_enable(grf, channel, true); in pctl_cfg()
258 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
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H A Dsdram_common.c183 u32 *p_os_reg2, u32 *p_os_reg3, u32 channel) in sdram_org_config() argument
188 *p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel); in sdram_org_config()
189 *p_os_reg2 |= SYS_REG_ENC_CHINFO(channel); in sdram_org_config()
190 *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel); in sdram_org_config()
191 *p_os_reg2 |= SYS_REG_ENC_COL(cap_info->col, channel); in sdram_org_config()
192 *p_os_reg2 |= SYS_REG_ENC_BK(cap_info->bk, channel); in sdram_org_config()
193 *p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel); in sdram_org_config()
194 *p_os_reg2 |= SYS_REG_ENC_DBW(cap_info->dbw, channel); in sdram_org_config()
196 SYS_REG_ENC_CS0_ROW(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel); in sdram_org_config()
199 *p_os_reg3, channel); in sdram_org_config()
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/rk3399_rockchip-uboot/include/
H A DMCD_tasksInit.h17 volatile TaskTableEntry * taskTable, int channel);
23 volatile TaskTableEntry * taskTable, int channel);
28 volatile TaskTableEntry * taskTable, int channel);
34 volatile TaskTableEntry * taskTable, int channel);
38 volatile TaskTableEntry * taskTable, int channel);
42 volatile TaskTableEntry * taskTable, int channel);
H A Dpwm.h25 int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
36 int (*set_enable)(struct udevice *dev, uint channel, bool enable);
45 int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
59 int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
70 int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
80 int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
H A Dadc.h101 int (*start_channel)(struct udevice *dev, int channel);
132 int (*channel_data)(struct udevice *dev, int channel,
170 int adc_start_channel(struct udevice *dev, int channel);
193 int adc_channel_data(struct udevice *dev, int channel, unsigned int *data);
236 int adc_channel_single_shot(const char *name, int channel, unsigned int *data);
/rk3399_rockchip-uboot/drivers/spmi/
H A Dspmi-msm.c56 unsigned channel; in msm_spmi_write() local
64 channel = priv->channel_map[usid][pid]; in msm_spmi_write()
67 writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
71 writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA); in msm_spmi_write()
81 writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); in msm_spmi_write()
86 reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) + in msm_spmi_write()
101 unsigned channel; in msm_spmi_read() local
109 channel = priv->channel_map[usid][pid]; in msm_spmi_read()
112 writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG); in msm_spmi_read()
122 writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0); in msm_spmi_read()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Ddmc_common.c98 int channel, chip; in dmc_config_mrs() local
100 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_mrs()
103 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_mrs()
139 int channel, chip; in dmc_config_prech() local
141 for (channel = 0; channel < mem->dmc_channels; channel++) { in dmc_config_prech()
144 mask = channel << DIRECT_CMD_CHANNEL_SHIFT; in dmc_config_prech()
/rk3399_rockchip-uboot/drivers/video/
H A Dipu.h210 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
211 void ipu_uninit_channel(ipu_channel_t channel);
213 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
220 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
223 int32_t ipu_is_channel_busy(ipu_channel_t channel);
224 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
226 int32_t ipu_enable_channel(ipu_channel_t channel);
227 int32_t ipu_disable_channel(ipu_channel_t channel);
238 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
240 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
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H A Dipu_common.c562 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) in ipu_init_channel() argument
567 debug("init channel = %d\n", IPU_CHAN_ID(channel)); in ipu_init_channel()
575 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { in ipu_init_channel()
577 IPU_CHAN_ID(channel)); in ipu_init_channel()
582 switch (channel) { in ipu_init_channel()
603 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, in ipu_init_channel()
613 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, in ipu_init_channel()
626 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); in ipu_init_channel()
651 void ipu_uninit_channel(ipu_channel_t channel) in ipu_uninit_channel() argument
657 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { in ipu_uninit_channel()
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/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c125 int channel) in phy_pctrl_reset() argument
129 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
141 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
143 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
200 static void ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel, in ddr_set_ddr3_mode() argument
219 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, in pctl_cfg() argument
240 ddr_set_ddr3_mode(grf, channel, true); in pctl_cfg()
247 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
368 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, in set_bandwidth_ratio() argument
404 static int data_training(const struct chan_info *chan, int channel, in data_training() argument
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/rk3399_rockchip-uboot/drivers/adc/
H A Dadc-uclass.c97 int adc_start_channel(struct udevice *dev, int channel) in adc_start_channel() argument
105 ret = check_channel(dev, channel, CHECK_NUMBER, __func__); in adc_start_channel()
113 return ops->start_channel(dev, channel); in adc_start_channel()
135 int adc_channel_data(struct udevice *dev, int channel, unsigned int *data) in adc_channel_data() argument
145 ret = check_channel(dev, channel, CHECK_NUMBER, __func__); in adc_channel_data()
150 ret = ops->channel_data(dev, channel, data); in adc_channel_data()
188 int adc_channel_single_shot(const char *name, int channel, unsigned int *data) in adc_channel_single_shot() argument
197 ret = adc_start_channel(dev, channel); in adc_channel_single_shot()
201 ret = adc_channel_data(dev, channel, data); in adc_channel_single_shot()
213 int channel, ret; in _adc_channels_single_shot() local
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/rk3399_rockchip-uboot/drivers/i2c/
H A Di2c_core.c60 int channel) in i2c_mux_set() argument
66 if (channel < 0) { in i2c_mux_set()
77 if (channel > 1) in i2c_mux_set()
79 buf = (uint8_t)((channel & 0x01) | (1 << 2)); in i2c_mux_set()
82 if (channel > 3) in i2c_mux_set()
84 buf = (uint8_t)((channel & 0x03) | (1 << 2)); in i2c_mux_set()
87 if (channel > 7) in i2c_mux_set()
89 buf = (uint8_t)((channel & 0x07) | (1 << 3)); in i2c_mux_set()
92 if (channel > 7) in i2c_mux_set()
94 buf = (uint8_t)(0x01 << channel); in i2c_mux_set()
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/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_mipi_dsi.c145 if (msg->channel > 3) in mipi_dsi_create_packet()
149 packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); in mipi_dsi_create_packet()
177 .channel = dsi->channel, in mipi_dsi_shutdown_peripheral()
196 .channel = dsi->channel, in mipi_dsi_turn_on_peripheral()
220 .channel = dsi->channel, in mipi_dsi_set_maximum_return_packet_size()
245 .channel = dsi->channel, in mipi_dsi_compression_mode()
268 .channel = dsi->channel, in mipi_dsi_picture_parameter_set()
294 .channel = dsi->channel, in mipi_dsi_generic_write()
335 .channel = dsi->channel, in mipi_dsi_generic_read()
378 .channel = dsi->channel, in mipi_dsi_dcs_write_buffer()
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