Lines Matching refs:channel
86 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, in rkclk_ddr_reset() argument
89 channel &= 0x1; in rkclk_ddr_reset()
92 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
93 CRU_SFTRST_DDR_PHY(channel, phy), in rkclk_ddr_reset()
98 u32 channel) in phy_pctrl_reset() argument
100 rkclk_ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
102 rkclk_ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
104 rkclk_ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
139 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
143 &sdram_params->ch[channel]; in set_memory_map()
197 u32 b_reg, u32 channel) in phy_io_config() argument
537 u32 channel, u32 mr5) in set_ds_odt() argument
768 phy_io_config(chan, sdram_params, io->rd_vref, b_reg, channel); in set_ds_odt()
770 phy_io_config(chan, sdram_params, 0, b_reg, channel); in set_ds_odt()
896 u32 en, u32 b_reg, u32 channel, u32 mr5) in set_lp4_dq_odt() argument
955 u32 en, u32 b_reg, u32 channel, u32 mr5) in set_lp4_ca_odt() argument
1014 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR3() argument
1072 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR12() argument
1132 u32 b_reg, u32 channel, u32 mr5) in set_lp4_MR14() argument
1241 static int pctl_cfg(const struct chan_info *chan, u32 channel, in pctl_cfg() argument
1268 if (sdram_params->base.dramtype == LPDDR4 && channel == 1) { in pctl_cfg()
1278 set_memory_map(chan, channel, sdram_params); in pctl_cfg()
1291 g_pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & in pctl_cfg()
1373 if (channel == 1) in pctl_cfg()
1429 static int data_training_ca(const struct chan_info *chan, u32 channel, in data_training_ca() argument
1436 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_ca()
1490 static int data_training_wl(const struct chan_info *chan, u32 channel, in data_training_wl() argument
1497 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wl()
1549 static int data_training_rg(const struct chan_info *chan, u32 channel, in data_training_rg() argument
1556 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rg()
1609 static int data_training_rl(const struct chan_info *chan, u32 channel, in data_training_rl() argument
1614 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rl()
1653 static int data_training_wdql(const struct chan_info *chan, u32 channel, in data_training_wdql() argument
1658 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wdql()
1705 static int data_training(const struct chan_info *chan, u32 channel, in data_training() argument
1732 ret = data_training_ca(chan, channel, sdram_params); in data_training()
1739 ret = data_training_wl(chan, channel, sdram_params); in data_training()
1746 ret = data_training_rg(chan, channel, sdram_params); in data_training()
1753 ret = data_training_rl(chan, channel, sdram_params); in data_training()
1760 ret = data_training_wdql(chan, channel, sdram_params); in data_training()
1774 unsigned char channel, u32 ddrconfig) in set_ddrconfig() argument
1781 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1782 + sdram_params->ch[channel].cap_info.col in set_ddrconfig()
1783 + sdram_params->ch[channel].cap_info.bk in set_ddrconfig()
1784 + sdram_params->ch[channel].cap_info.bw - 20)); in set_ddrconfig()
1785 if (sdram_params->ch[channel].cap_info.rank > 1) in set_ddrconfig()
1786 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1787 - sdram_params->ch[channel].cap_info.cs1_row); in set_ddrconfig()
1788 if (sdram_params->ch[channel].cap_info.row_3_4) { in set_ddrconfig()
1818 unsigned int channel, idx; in dram_all_config() local
1820 for (channel = 0, idx = 0; in dram_all_config()
1821 (idx < sdram_params->base.num_channels) && (channel < 2); in dram_all_config()
1822 channel++) { in dram_all_config()
1826 if (sdram_params->ch[channel].cap_info.col == 0) in dram_all_config()
1829 sdram_org_config(&sdram_params->ch[channel].cap_info, in dram_all_config()
1831 &sys_reg3, channel); in dram_all_config()
1832 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
1833 noc_timing = &sdram_params->ch[channel].noc_timings; in dram_all_config()
1837 if (sdram_params->ch[channel].cap_info.rank == 1) in dram_all_config()
1838 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
1857 u32 channel; in switch_to_phy_index1() local
1885 for (channel = 0; channel < ch_count; channel++) { in switch_to_phy_index1()
1886 denali_phy = dram->chan[channel].publ->denali_phy; in switch_to_phy_index1()
1888 ret = data_training(&dram->chan[channel], channel, in switch_to_phy_index1()
1919 u32 channel) in calculate_ddrconfig() argument
1922 unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in calculate_ddrconfig()
1923 unsigned int col = sdram_params->ch[channel].cap_info.col; in calculate_ddrconfig()
1924 unsigned int bw = sdram_params->ch[channel].cap_info.bw; in calculate_ddrconfig()
1944 unsigned int channel; in calculate_stride() local
1952 for (channel = 0; channel < 2; channel++) { in calculate_stride()
1956 &sdram_params->ch[channel].cap_info; in calculate_stride()
1970 ch_cap[channel] = cs0_cap + cs1_cap; in calculate_stride()
1971 chinfo |= 1 << channel; in calculate_stride()
2109 unsigned int channel) in set_cap_relate_config() argument
2116 tmp = (8 << sdram_params->ch[channel].cap_info.bw) / in set_cap_relate_config()
2117 (8 << sdram_params->ch[channel].cap_info.dbw); in set_cap_relate_config()
2126 noc_timing = &sdram_params->ch[channel].noc_timings; in set_cap_relate_config()
2131 if (sdram_params->ch[channel].cap_info.bw == 16 && in set_cap_relate_config()
2142 unsigned int channel) in clear_channel_params() argument
2144 sdram_params->ch[channel].cap_info.rank = 0; in clear_channel_params()
2145 sdram_params->ch[channel].cap_info.col = 0; in clear_channel_params()
2146 sdram_params->ch[channel].cap_info.bk = 0; in clear_channel_params()
2147 sdram_params->ch[channel].cap_info.bw = 32; in clear_channel_params()
2148 sdram_params->ch[channel].cap_info.dbw = 32; in clear_channel_params()
2149 sdram_params->ch[channel].cap_info.row_3_4 = 0; in clear_channel_params()
2150 sdram_params->ch[channel].cap_info.cs0_row = 0; in clear_channel_params()
2151 sdram_params->ch[channel].cap_info.cs1_row = 0; in clear_channel_params()
2152 sdram_params->ch[channel].cap_info.ddrconfig = 0; in clear_channel_params()
2265 unsigned char channel) in dram_detect_cap() argument
2267 const struct chan_info *chan = &dram->chan[channel]; in dram_detect_cap()
2268 struct sdram_cap_info *cap_info = &sdram_params->ch[channel].cap_info; in dram_detect_cap()
2282 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2287 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2304 if (data_training(chan, channel, sdram_params, training_flag)) { in dram_detect_cap()
2334 set_memory_map(chan, channel, sdram_params); in dram_detect_cap()
2335 ddrconfig = calculate_ddrconfig(sdram_params, channel); in dram_detect_cap()
2338 set_ddrconfig(chan, sdram_params, channel, in dram_detect_cap()
2387 static int read_mr_for_detect(struct dram_info *dram, u32 channel, u32 rank, in read_mr_for_detect() argument
2396 &dram->chan[channel]; in read_mr_for_detect()
2404 if (sdram_params->ch[channel].cap_info.col == 0) { in read_mr_for_detect()
2409 cs = sdram_params->ch[channel].cap_info.rank; in read_mr_for_detect()
2410 col = sdram_params->ch[channel].cap_info.col; in read_mr_for_detect()
2411 bk = sdram_params->ch[channel].cap_info.bk; in read_mr_for_detect()
2412 bw = sdram_params->ch[channel].cap_info.bw; in read_mr_for_detect()
2413 row_3_4 = sdram_params->ch[channel].cap_info.row_3_4; in read_mr_for_detect()
2414 cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in read_mr_for_detect()
2415 cs1_row = sdram_params->ch[channel].cap_info.cs1_row; in read_mr_for_detect()
2416 ddrconfig = sdram_params->ch[channel].cap_info.ddrconfig; in read_mr_for_detect()
2419 sdram_params->ch[channel].cap_info.rank = 2; in read_mr_for_detect()
2420 sdram_params->ch[channel].cap_info.col = 10; in read_mr_for_detect()
2421 sdram_params->ch[channel].cap_info.bk = 3; in read_mr_for_detect()
2422 sdram_params->ch[channel].cap_info.bw = 2; in read_mr_for_detect()
2423 sdram_params->ch[channel].cap_info.row_3_4 = 0; in read_mr_for_detect()
2424 sdram_params->ch[channel].cap_info.cs0_row = 15; in read_mr_for_detect()
2425 sdram_params->ch[channel].cap_info.cs1_row = 15; in read_mr_for_detect()
2426 sdram_params->ch[channel].cap_info.ddrconfig = 1; in read_mr_for_detect()
2428 set_memory_map(chan, channel, sdram_params); in read_mr_for_detect()
2429 sdram_params->ch[channel].cap_info.ddrconfig = in read_mr_for_detect()
2430 calculate_ddrconfig(sdram_params, channel); in read_mr_for_detect()
2431 set_ddrconfig(chan, sdram_params, channel, in read_mr_for_detect()
2432 sdram_params->ch[channel].cap_info.ddrconfig); in read_mr_for_detect()
2433 set_cap_relate_config(chan, sdram_params, channel); in read_mr_for_detect()
2435 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.bw in read_mr_for_detect()
2436 + sdram_params->ch[channel].cap_info.col in read_mr_for_detect()
2437 + sdram_params->ch[channel].cap_info.bk in read_mr_for_detect()
2438 + sdram_params->ch[channel].cap_info.cs0_row)); in read_mr_for_detect()
2440 if (sdram_params->ch[channel].cap_info.row_3_4) in read_mr_for_detect()
2443 if (channel == 0) in read_mr_for_detect()
2468 sdram_params->ch[channel].cap_info.rank = cs; in read_mr_for_detect()
2469 sdram_params->ch[channel].cap_info.col = col; in read_mr_for_detect()
2470 sdram_params->ch[channel].cap_info.bk = bk; in read_mr_for_detect()
2471 sdram_params->ch[channel].cap_info.bw = bw; in read_mr_for_detect()
2472 sdram_params->ch[channel].cap_info.row_3_4 = row_3_4; in read_mr_for_detect()
2473 sdram_params->ch[channel].cap_info.cs0_row = cs0_row; in read_mr_for_detect()
2474 sdram_params->ch[channel].cap_info.cs1_row = cs1_row; in read_mr_for_detect()
2475 sdram_params->ch[channel].cap_info.ddrconfig = ddrconfig; in read_mr_for_detect()
2504 u32 channel) in dram_copy_phy_fn() argument
2513 denali_ctl = dram->chan[channel].pctl->denali_ctl; in dram_copy_phy_fn()
2514 denali_phy = dram->chan[channel].publ->denali_phy; in dram_copy_phy_fn()
2766 read_mr(dram->chan[channel].pctl, 1, 5, &mr5); in dram_copy_phy_fn()
2767 set_ds_odt(&dram->chan[channel], f1_sdram_params, 1, 0, mr5); in dram_copy_phy_fn()
2768 set_ds_odt(&dram->chan[channel], f1_sdram_params, 1, 1, mr5); in dram_copy_phy_fn()
2771 set_lp4_dq_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2773 set_lp4_ca_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2775 set_lp4_MR3(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2777 set_lp4_MR12(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2779 set_lp4_MR14(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2782 set_lp4_dq_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2784 set_lp4_ca_odt(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2786 set_lp4_MR3(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2788 set_lp4_MR12(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2790 set_lp4_MR14(&dram->chan[channel], f1_sdram_params, in dram_copy_phy_fn()
2825 u32 channel; in dram_set_phy_fn() local
2827 for (channel = 0; channel < 2; channel++) in dram_set_phy_fn()
2829 channel); in dram_set_phy_fn()
2836 u32 channel; in dram_set_rate() local
2875 for (channel = 0; channel < 2; channel++) { in dram_set_rate()
2876 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2878 ret[channel] = data_training(&dram->chan[channel], in dram_set_rate()
2879 channel, sdram_params, in dram_set_rate()
2882 for (channel = 0; channel < 2; channel++) { in dram_set_rate()
2883 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2885 if (ret[channel]) in dram_set_rate()
2887 channel); in dram_set_rate()
2889 printf("channel %d training pass\n", channel); in dram_set_rate()
2930 int channel; in sdram_init() local
2949 for (channel = 0; channel < 2; channel++) { in sdram_init()
2951 &dram->chan[channel]; in sdram_init()
2955 phy_pctrl_reset(cru, channel); in sdram_init()
2957 pctl_cfg(chan, channel, sdram_params); in sdram_init()
3000 for (channel = 0; channel < 2; channel++) { in sdram_init()
3001 const struct chan_info *chan = &dram->chan[channel]; in sdram_init()
3003 &sdram_params->ch[channel].cap_info; in sdram_init()
3013 printf(channel ? "1: " : "0: "); in sdram_init()
3015 if (channel == 0) in sdram_init()
3020 if (dram_detect_cap(dram, sdram_params, channel)) { in sdram_init()
3026 set_memory_map(chan, channel, sdram_params); in sdram_init()
3028 calculate_ddrconfig(sdram_params, channel); in sdram_init()
3033 set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig); in sdram_init()
3034 set_cap_relate_config(chan, sdram_params, channel); in sdram_init()