30 int mxs_dma_validate_chan(int channel)  in mxs_dma_validate_chan()  argument
34 	if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))  in mxs_dma_validate_chan()
37 	pchan = mxs_dma_channels + channel;  in mxs_dma_validate_chan()
66 static int mxs_dma_read_semaphore(int channel)  in mxs_dma_read_semaphore()  argument
73 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_read_semaphore()
77 	tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_read_semaphore()
109 static int mxs_dma_enable(int channel)  in mxs_dma_enable()  argument
118 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_enable()
122 	pchan = mxs_dma_channels + channel;  in mxs_dma_enable()
137 		sem = mxs_dma_read_semaphore(channel);  in mxs_dma_enable()
145 				&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
148 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
155 			&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
157 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
158 		writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),  in mxs_dma_enable()
180 static int mxs_dma_disable(int channel)  in mxs_dma_disable()  argument
187 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_disable()
191 	pchan = mxs_dma_channels + channel;  in mxs_dma_disable()
196 	writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),  in mxs_dma_disable()
210 static int mxs_dma_reset(int channel)  in mxs_dma_reset()  argument
223 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_reset()
227 	writel(1 << (channel + offset), setreg);  in mxs_dma_reset()
237 static int mxs_dma_enable_irq(int channel, int enable)  in mxs_dma_enable_irq()  argument
243 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_enable_irq()
248 		writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),  in mxs_dma_enable_irq()
251 		writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),  in mxs_dma_enable_irq()
263 static int mxs_dma_ack_irq(int channel)  in mxs_dma_ack_irq()  argument
269 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_ack_irq()
273 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_ack_irq()
274 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);  in mxs_dma_ack_irq()
282 static int mxs_dma_request(int channel)  in mxs_dma_request()  argument
286 	if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))  in mxs_dma_request()
289 	pchan = mxs_dma_channels + channel;  in mxs_dma_request()
314 int mxs_dma_release(int channel)  in mxs_dma_release()  argument
319 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_release()
323 	pchan = mxs_dma_channels + channel;  in mxs_dma_release()
406 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)  in mxs_dma_desc_append()  argument
412 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_desc_append()
416 	pchan = mxs_dma_channels + channel;  in mxs_dma_desc_append()
454 static int mxs_dma_finish(int channel, struct list_head *head)  in mxs_dma_finish()  argument
462 	ret = mxs_dma_validate_chan(channel);  in mxs_dma_finish()
466 	pchan = mxs_dma_channels + channel;  in mxs_dma_finish()
468 	sem = mxs_dma_read_semaphore(channel);  in mxs_dma_finish()
596 int mxs_dma_init_channel(int channel)  in mxs_dma_init_channel()  argument
601 	pchan = mxs_dma_channels + channel;  in mxs_dma_init_channel()
604 	ret = mxs_dma_request(channel);  in mxs_dma_init_channel()
608 			channel);  in mxs_dma_init_channel()
612 	mxs_dma_reset(channel);  in mxs_dma_init_channel()
613 	mxs_dma_ack_irq(channel);  in mxs_dma_init_channel()