1*38ad43e4SBin Meng /* 2*38ad43e4SBin Meng * Copyright (C) 2013, Intel Corporation 3*38ad43e4SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4*38ad43e4SBin Meng * 5*38ad43e4SBin Meng * Ported from Intel released Quark UEFI BIOS 6*38ad43e4SBin Meng * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei 7*38ad43e4SBin Meng * 8*38ad43e4SBin Meng * SPDX-License-Identifier: Intel 9*38ad43e4SBin Meng */ 10*38ad43e4SBin Meng 11*38ad43e4SBin Meng #ifndef _MRC_UTIL_H_ 12*38ad43e4SBin Meng #define _MRC_UTIL_H_ 13*38ad43e4SBin Meng 14*38ad43e4SBin Meng /* Turn on this macro to enable MRC debugging output */ 15*38ad43e4SBin Meng #undef MRC_DEBUG 16*38ad43e4SBin Meng 17*38ad43e4SBin Meng /* MRC Debug Support */ 18*38ad43e4SBin Meng #define DPF debug_cond 19*38ad43e4SBin Meng 20*38ad43e4SBin Meng /* debug print type */ 21*38ad43e4SBin Meng 22*38ad43e4SBin Meng #ifdef MRC_DEBUG 23*38ad43e4SBin Meng #define D_ERROR 0x0001 24*38ad43e4SBin Meng #define D_INFO 0x0002 25*38ad43e4SBin Meng #define D_REGRD 0x0004 26*38ad43e4SBin Meng #define D_REGWR 0x0008 27*38ad43e4SBin Meng #define D_FCALL 0x0010 28*38ad43e4SBin Meng #define D_TRN 0x0020 29*38ad43e4SBin Meng #define D_TIME 0x0040 30*38ad43e4SBin Meng #else 31*38ad43e4SBin Meng #define D_ERROR 0 32*38ad43e4SBin Meng #define D_INFO 0 33*38ad43e4SBin Meng #define D_REGRD 0 34*38ad43e4SBin Meng #define D_REGWR 0 35*38ad43e4SBin Meng #define D_FCALL 0 36*38ad43e4SBin Meng #define D_TRN 0 37*38ad43e4SBin Meng #define D_TIME 0 38*38ad43e4SBin Meng #endif 39*38ad43e4SBin Meng 40*38ad43e4SBin Meng #define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__) 41*38ad43e4SBin Meng #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) 42*38ad43e4SBin Meng #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) 43*38ad43e4SBin Meng 44*38ad43e4SBin Meng /* Message Bus Port */ 45*38ad43e4SBin Meng #define MEM_CTLR 0x01 46*38ad43e4SBin Meng #define HOST_BRIDGE 0x03 47*38ad43e4SBin Meng #define MEM_MGR 0x05 48*38ad43e4SBin Meng #define HTE 0x11 49*38ad43e4SBin Meng #define DDRPHY 0x12 50*38ad43e4SBin Meng 51*38ad43e4SBin Meng /* number of sample points */ 52*38ad43e4SBin Meng #define SAMPLE_CNT 3 53*38ad43e4SBin Meng /* number of PIs to increment per sample */ 54*38ad43e4SBin Meng #define SAMPLE_DLY 26 55*38ad43e4SBin Meng 56*38ad43e4SBin Meng enum { 57*38ad43e4SBin Meng /* indicates to decrease delays when looking for edge */ 58*38ad43e4SBin Meng BACKWARD, 59*38ad43e4SBin Meng /* indicates to increase delays when looking for edge */ 60*38ad43e4SBin Meng FORWARD 61*38ad43e4SBin Meng }; 62*38ad43e4SBin Meng 63*38ad43e4SBin Meng enum { 64*38ad43e4SBin Meng RCVN, 65*38ad43e4SBin Meng WDQS, 66*38ad43e4SBin Meng WDQX, 67*38ad43e4SBin Meng RDQS, 68*38ad43e4SBin Meng VREF, 69*38ad43e4SBin Meng WCMD, 70*38ad43e4SBin Meng WCTL, 71*38ad43e4SBin Meng WCLK, 72*38ad43e4SBin Meng MAX_ALGOS, 73*38ad43e4SBin Meng }; 74*38ad43e4SBin Meng 75*38ad43e4SBin Meng void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 76*38ad43e4SBin Meng void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask); 77*38ad43e4SBin Meng void mrc_post_code(uint8_t major, uint8_t minor); 78*38ad43e4SBin Meng void delay_n(uint32_t ns); 79*38ad43e4SBin Meng void delay_u(uint32_t ms); 80*38ad43e4SBin Meng void select_mem_mgr(void); 81*38ad43e4SBin Meng void select_hte(void); 82*38ad43e4SBin Meng void dram_init_command(uint32_t data); 83*38ad43e4SBin Meng void dram_wake_command(void); 84*38ad43e4SBin Meng void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane); 85*38ad43e4SBin Meng 86*38ad43e4SBin Meng void set_rcvn(uint8_t channel, uint8_t rank, 87*38ad43e4SBin Meng uint8_t byte_lane, uint32_t pi_count); 88*38ad43e4SBin Meng uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane); 89*38ad43e4SBin Meng void set_rdqs(uint8_t channel, uint8_t rank, 90*38ad43e4SBin Meng uint8_t byte_lane, uint32_t pi_count); 91*38ad43e4SBin Meng uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 92*38ad43e4SBin Meng void set_wdqs(uint8_t channel, uint8_t rank, 93*38ad43e4SBin Meng uint8_t byte_lane, uint32_t pi_count); 94*38ad43e4SBin Meng uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); 95*38ad43e4SBin Meng void set_wdq(uint8_t channel, uint8_t rank, 96*38ad43e4SBin Meng uint8_t byte_lane, uint32_t pi_count); 97*38ad43e4SBin Meng uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane); 98*38ad43e4SBin Meng void set_wcmd(uint8_t channel, uint32_t pi_count); 99*38ad43e4SBin Meng uint32_t get_wcmd(uint8_t channel); 100*38ad43e4SBin Meng void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count); 101*38ad43e4SBin Meng uint32_t get_wclk(uint8_t channel, uint8_t rank); 102*38ad43e4SBin Meng void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count); 103*38ad43e4SBin Meng uint32_t get_wctl(uint8_t channel, uint8_t rank); 104*38ad43e4SBin Meng void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting); 105*38ad43e4SBin Meng uint32_t get_vref(uint8_t channel, uint8_t byte_lane); 106*38ad43e4SBin Meng 107*38ad43e4SBin Meng uint32_t get_addr(uint8_t channel, uint8_t rank); 108*38ad43e4SBin Meng uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, 109*38ad43e4SBin Meng uint8_t rank, bool rcvn); 110*38ad43e4SBin Meng void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], 111*38ad43e4SBin Meng uint8_t channel, uint8_t rank, bool rcvn); 112*38ad43e4SBin Meng uint32_t byte_lane_mask(struct mrc_params *mrc_params); 113*38ad43e4SBin Meng uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address); 114*38ad43e4SBin Meng uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address); 115*38ad43e4SBin Meng void lfsr32(uint32_t *lfsr_ptr); 116*38ad43e4SBin Meng void clear_pointers(void); 117*38ad43e4SBin Meng void print_timings(struct mrc_params *mrc_params); 118*38ad43e4SBin Meng 119*38ad43e4SBin Meng #endif /* _MRC_UTIL_H_ */ 120