125 			    int channel)  in phy_pctrl_reset()  argument
129 	ddr_reset(cru, channel, 1, 1);  in phy_pctrl_reset()
141 	ddr_reset(cru, channel, 1, 0);  in phy_pctrl_reset()
143 	ddr_reset(cru, channel, 0, 0);  in phy_pctrl_reset()
200 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)  in ddr_set_enable()  argument
210 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,  in ddr_set_ddr3_mode()  argument
229 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,  in pctl_cfg()  argument
250 		ddr_set_ddr3_mode(grf, channel, true);  in pctl_cfg()
251 		ddr_set_enable(grf, channel, true);  in pctl_cfg()
258 static void phy_cfg(const struct chan_info *chan, int channel,  in phy_cfg()  argument
379 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,  in set_bandwidth_ratio()  argument
388 		ddr_set_enable(grf, channel, 1);  in set_bandwidth_ratio()
398 		ddr_set_enable(grf, channel, 0);  in set_bandwidth_ratio()
417 static int data_training(const struct chan_info *chan, int channel,  in data_training()  argument
433 	rank = sdram_params->ch[channel].rank | 1;  in data_training()
567 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,  in sdram_rank_bw_detect()  argument
572 	const struct chan_info *chan = &dram->chan[channel];  in sdram_rank_bw_detect()
577 	if (data_training(chan, channel, sdram_params) < 0) {  in sdram_rank_bw_detect()
581 		if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {  in sdram_rank_bw_detect()
588 			sdram_params->ch[channel].rank = 1;  in sdram_rank_bw_detect()
590 					sdram_params->ch[channel].rank << 18);  in sdram_rank_bw_detect()
595 			sdram_params->ch[channel].bw = 1;  in sdram_rank_bw_detect()
596 			set_bandwidth_ratio(chan, channel,  in sdram_rank_bw_detect()
597 					    sdram_params->ch[channel].bw,  in sdram_rank_bw_detect()
603 	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;  in sdram_rank_bw_detect()
606 	    (data_training(chan, channel, sdram_params) < 0)) {  in sdram_rank_bw_detect()
608 			ddr_phy_ctl_reset(dram->cru, channel, 1);  in sdram_rank_bw_detect()
610 			ddr_phy_ctl_reset(dram->cru, channel, 0);  in sdram_rank_bw_detect()
628 static int sdram_col_row_detect(struct dram_info *dram, int channel,  in sdram_col_row_detect()  argument
633 	const struct chan_info *chan = &dram->chan[channel];  in sdram_col_row_detect()
642 			(1 << (col + sdram_params->ch[channel].bw - 1));  in sdram_col_row_detect()
653 		sdram_params->ch[channel].col = col;  in sdram_col_row_detect()
673 		sdram_params->ch[channel].cs1_row = row;  in sdram_col_row_detect()
674 		sdram_params->ch[channel].row_3_4 = 0;  in sdram_col_row_detect()
675 		debug("chn %d col %d, row %d\n", channel, col, row);  in sdram_col_row_detect()
676 		sdram_params->ch[channel].cs0_row = row;  in sdram_col_row_detect()
715 	int channel;  in sdram_init()  local
731 	for (channel = 0; channel < 1; channel++) {  in sdram_init()
732 		const struct chan_info *chan = &dram->chan[channel];  in sdram_init()
736 		phy_pctrl_reset(dram->cru, publ, channel);  in sdram_init()
741 		pctl_cfg(channel, pctl, sdram_params, dram->grf);  in sdram_init()
743 		phy_cfg(chan, channel, sdram_params);  in sdram_init()
755 		sdram_params->ch[channel].bw = 2;  in sdram_init()
756 		set_bandwidth_ratio(chan, channel,  in sdram_init()
757 				    sdram_params->ch[channel].bw, dram->grf);  in sdram_init()
764 		sdram_params->ch[channel].rank = 2,  in sdram_init()
766 				(sdram_params->ch[channel].rank | 1) << 18);  in sdram_init()
777 		sdram_rank_bw_detect(dram, channel, sdram_params);  in sdram_init()
788 		sdram_params->ch[channel].bk = 3;  in sdram_init()
790 		ret = sdram_col_row_detect(dram, channel, sdram_params);  in sdram_init()