Home
last modified time | relevance | path

Searched refs:bw (Results 1 – 25 of 72) sorted by relevance

123

/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_common.c68 printdec(8 << cap_info->bw); in sdram_print_ddr_info()
143 cap[0] = 1llu << (cap_info->bw + cap_info->col + in sdram_get_cs_cap()
147 cap[1] = 1llu << (cap_info->bw + cap_info->col + in sdram_get_cs_cap()
153 cap[2] = 1llu << (cap_info->bw + cap_info->col + in sdram_get_cs_cap()
155 cap[3] = 1llu << (cap_info->bw + cap_info->col + in sdram_get_cs_cap()
193 *p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel); in sdram_org_config()
223 *p_os_reg2 |= SYS_REG_ENC_BW_V3(cap_info->bw, channel); in sdram_org_config_v3()
261 u32 bw = cap_info->bw; in sdram_detect_col() local
266 (1ul << (col + bw - 1ul))); in sdram_detect_col()
287 u32 bw = cap_info->bw; in sdram_detect_bank() local
[all …]
H A Dsdram_px30.c135 u32 bw, die_bw, col, bank; in calculate_ddrconfig() local
139 bw = cap_info->bw; in calculate_ddrconfig()
146 ddrconf = 7 + bw; in calculate_ddrconfig()
148 ddrconf = 12 - bw; in calculate_ddrconfig()
151 tmp = ((bank - 2) << 3) | (col + bw - 10); in calculate_ddrconfig()
186 cs_pst = cap_info->bw + cap_info->col + in set_ctl_address_map()
220 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) in set_ctl_address_map()
246 u32 i, bw; in check_rd_gate() local
248 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
249 switch (bw) { in check_rd_gate()
[all …]
H A Dsdram_phy_px30.c96 void phy_dram_set_bw(void __iomem *phy_base, u32 bw) in phy_dram_set_bw() argument
98 if (bw == 2) { in phy_dram_set_bw()
102 } else if (bw == 1) { in phy_dram_set_bw()
106 } else if (bw == 0) { in phy_dram_set_bw()
172 struct sdram_base_params *base, u32 bw) in phy_cfg() argument
181 if (bw == 2) { in phy_cfg()
183 } else if (bw == 1) { in phy_cfg()
H A Dsdram_rk322x.c235 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; in data_training() local
264 ret = (ret & 0xf) ^ bw; in data_training()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
384 if (bw == 1) { in set_bw()
405 u32 bw; in pctl_cfg() local
408 if (sdram_params->ch[0].bw == 2) in pctl_cfg()
409 bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN; in pctl_cfg()
411 bw = GRF_MSCH_NOC_16BIT_EN; in pctl_cfg()
436 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); in pctl_cfg()
463 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); in pctl_cfg()
[all …]
H A Dsdram_rk3328.c141 u32 cs, bw, die_bw, col, row, bank; in calculate_ddrconfig() local
147 bw = cap_info->bw; in calculate_ddrconfig()
158 tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) | in calculate_ddrconfig()
171 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; in calculate_ddrconfig()
190 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
198 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0); in calculate_ddrconfig()
229 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
370 &sdram_params->base, cap_info->bw); in sdram_init()
420 u32 bw = 1; in dram_detect_cap() local
460 bw = 2; in dram_detect_cap()
[all …]
H A Dsdram_rk3399.c161 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; in set_memory_map()
1784 + sdram_params->ch[channel].cap_info.bw - 20)); in set_ddrconfig()
1924 unsigned int bw = sdram_params->ch[channel].cap_info.bw; in calculate_ddrconfig() local
1926 col -= (bw == 2) ? 0 : 1; in calculate_ddrconfig()
1962 cap_info->bk + cap_info->bw - 20)); in calculate_stride()
2116 tmp = (8 << sdram_params->ch[channel].cap_info.bw) / in set_cap_relate_config()
2131 if (sdram_params->ch[channel].cap_info.bw == 16 && in set_cap_relate_config()
2147 sdram_params->ch[channel].cap_info.bw = 32; in clear_channel_params()
2185 static void dram_set_bw(const struct chan_info *chan, u32 bw) in dram_set_bw() argument
2189 if (bw == 2) in dram_set_bw()
[all …]
H A Dsdram_rv1126.c400 u32 cs, bw, die_bw, col, row, bank; in calculate_ddrconfig() local
407 bw = cap_info->bw; in calculate_ddrconfig()
417 tmp = ((row - 13) << 4) | (1 << 3) | (bw << 1) | in calculate_ddrconfig()
430 tmp = ((cs - 1) << 7) | ((row - 13) << 4) | (bw << 1) | die_bw; in calculate_ddrconfig()
442 if (((bw + col - 10) == (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
453 ((bw + col - 10) << 0); in calculate_ddrconfig()
478 (col + bw) == 12) in calculate_ddrconfig()
557 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
1279 if (cap_info->bw == 2) in phy_cfg()
1281 else if (cap_info->bw == 1) in phy_cfg()
[all …]
H A Dsdram_rv1108_pctl_phy.c453 u32 bw = 1; in sdram_detect() local
470 (1ul << (col + bw - 1ul))); in sdram_detect()
486 bw - 1ul))); in sdram_detect()
506 col_max + bw - 1ul))); in sdram_detect()
533 u32 bw = 1; in sdram_all_config() local
551 (bw & SYS_REG_BW_MASK) << in sdram_all_config()
589 size = 1llu << (bw + in sdram_all_config()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dsdram.c23 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
78 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & in rockchip_sdram_size()
87 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
99 cs1_row, bw, row_3_4); in rockchip_sdram_size()
104 bw, row_3_4); in rockchip_sdram_size()
146 u32 col, bw; in get_page_size() local
154 bw = (2 >> ((os_reg >> SYS_REG_BW_SHIFT(0)) & SYS_REG_BW_MASK)); in get_page_size()
155 page_size = 1u << (col + bw); in get_page_size()
163 u32 bw = 2; in get_ddr_bw() local
167 bw = 2 >> ((os_reg >> SYS_REG_BW_SHIFT(0)) & SYS_REG_BW_MASK); in get_ddr_bw()
[all …]
/rk3399_rockchip-uboot/cmd/ddr_tool/
H A Dio_map.c60 u32 bw; in data_cpu_2_io_init()
62 bw = get_ddr_bw(); in data_cpu_2_io_init()
63 if (bw == 2) in data_cpu_2_io_init()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/s5p-common/
H A Dsromc.c26 tmp = srom->bw; in s5p_config_sromc()
29 srom->bw = tmp; in s5p_config_sromc()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
59 struct sdram_base_params *base, u32 bw);
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-samsung-hdptx.c882 u32 bw, status; in rockchip_hdptx_phy_set_rate() local
898 bw = DP_BW_RBR; in rockchip_hdptx_phy_set_rate()
902 bw = DP_BW_HBR; in rockchip_hdptx_phy_set_rate()
906 bw = DP_BW_HBR; in rockchip_hdptx_phy_set_rate()
909 bw = DP_BW_HBR; in rockchip_hdptx_phy_set_rate()
913 bw = DP_BW_HBR2; in rockchip_hdptx_phy_set_rate()
917 bw = DP_BW_HBR2; in rockchip_hdptx_phy_set_rate()
920 bw = DP_BW_HBR2; in rockchip_hdptx_phy_set_rate()
929 regmap_write(hdptx->regmap, 0x0144 + bw * 0x4, in rockchip_hdptx_phy_set_rate()
931 regmap_write(hdptx->regmap, 0x0180 + bw * 0x4, in rockchip_hdptx_phy_set_rate()
[all …]
H A Dphy-rockchip-usbdp.c191 u8 bw; /* dp bandwidth */ member
1059 udphy->bw = DP_BW_RBR; in dp_phy_set_rate()
1062 udphy->bw = DP_BW_HBR; in dp_phy_set_rate()
1065 udphy->bw = DP_BW_HBR2; in dp_phy_set_rate()
1068 udphy->bw = DP_BW_HBR3; in dp_phy_set_rate()
1075 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); in dp_phy_set_rate()
1093 static void dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, in dp_phy_set_voltage() argument
1101 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; in dp_phy_set_voltage()
1138 dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); in dp_phy_set_voltages()
/rk3399_rockchip-uboot/board/rockchip/evb_rk3036/
H A Devb_rk3036.c28 config->bw = 1; in get_ddr_config()
/rk3399_rockchip-uboot/board/rockchip/kylin_rk3036/
H A Dkylin_rk3036.c29 config->bw = 1; in get_ddr_config()
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/
H A Dsromc.h32 unsigned int bw; member
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dsromc.h29 unsigned int bw; member
/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rk3308/
H A Dsdram-rk3308-ddr2-detect-393.inc15 .bw = 0x1
H A Dsdram-rk3308-ddr3-detect-393.inc15 .bw = 0x1
H A Dsdram-rk3308-lpddr2-detect-393.inc15 .bw = 0x1
H A Dsdram-rk3308-ddr3-detect-589.inc15 .bw = 0x1
H A Dsdram-rk3308-lpddr2-detect-451.inc15 .bw = 0x1
H A Dsdram-rk3308-ddr3-detect-451.inc15 .bw = 0x1
H A Dsdram-rk3308-ddr2-detect-451.inc15 .bw = 0x1

123