141 	u32 cs, bw, die_bw, col, row, bank;  in calculate_ddrconfig()  local
147 	bw = cap_info->bw;  in calculate_ddrconfig()
158 			tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |  in calculate_ddrconfig()
171 		tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;  in calculate_ddrconfig()
190 				if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &  in calculate_ddrconfig()
198 		tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);  in calculate_ddrconfig()
229 	if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)  in set_ctl_address_map()
370 		&sdram_params->base, cap_info->bw);  in sdram_init()
420 	u32 bw = 1;  in dram_detect_cap()  local
460 	bw = 2;  in dram_detect_cap()
461 	cap_info->bw = bw;  in dram_detect_cap()
496 	if (cap_info->bw == 2)  in sdram_init_detect()