1*225f5eecSMinkyu Kang /* 2*225f5eecSMinkyu Kang * (C) Copyright 2010 Samsung Electronics 3*225f5eecSMinkyu Kang * Naveen Krishna Ch <ch.naveen@samsung.com> 4*225f5eecSMinkyu Kang * 5*225f5eecSMinkyu Kang * SPDX-License-Identifier: GPL-2.0+ 6*225f5eecSMinkyu Kang * 7*225f5eecSMinkyu Kang * Note: This file contains the register description for Memory subsystem 8*225f5eecSMinkyu Kang * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. 9*225f5eecSMinkyu Kang * 10*225f5eecSMinkyu Kang * Only SROMC is defined as of now 11*225f5eecSMinkyu Kang */ 12*225f5eecSMinkyu Kang 13*225f5eecSMinkyu Kang #ifndef __ASM_ARCH_SROMC_H_ 14*225f5eecSMinkyu Kang #define __ASM_ARCH_SROMC_H_ 15*225f5eecSMinkyu Kang 16*225f5eecSMinkyu Kang #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) 17*225f5eecSMinkyu Kang #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 18*225f5eecSMinkyu Kang /* 1-> Byte base address*/ 19*225f5eecSMinkyu Kang #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) 20*225f5eecSMinkyu Kang #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) 21*225f5eecSMinkyu Kang 22*225f5eecSMinkyu Kang #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ 23*225f5eecSMinkyu Kang #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ 24*225f5eecSMinkyu Kang #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ 25*225f5eecSMinkyu Kang #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ 26*225f5eecSMinkyu Kang #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ 27*225f5eecSMinkyu Kang #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ 28*225f5eecSMinkyu Kang #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ 29*225f5eecSMinkyu Kang 30*225f5eecSMinkyu Kang #ifndef __ASSEMBLY__ 31*225f5eecSMinkyu Kang struct s5p_sromc { 32*225f5eecSMinkyu Kang unsigned int bw; 33*225f5eecSMinkyu Kang unsigned int bc[6]; 34*225f5eecSMinkyu Kang }; 35*225f5eecSMinkyu Kang #endif /* __ASSEMBLY__ */ 36*225f5eecSMinkyu Kang 37*225f5eecSMinkyu Kang /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 38*225f5eecSMinkyu Kang void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); 39*225f5eecSMinkyu Kang 40*225f5eecSMinkyu Kang #endif /* __ASM_ARCH_SMC_H_ */ 41