xref: /rk3399_rockchip-uboot/board/rockchip/evb_rk3036/evb_rk3036.c (revision 51b4a639e45bfb592d7019b4e2a8cc72ad206c9b) 
1*c418addfSKever Yang /*
2*c418addfSKever Yang  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
3*c418addfSKever Yang  *
4*c418addfSKever Yang  * SPDX-License-Identifier:     GPL-2.0+
5*c418addfSKever Yang  */
6*c418addfSKever Yang 
7*c418addfSKever Yang #include <common.h>
8*c418addfSKever Yang #include <dm.h>
9*c418addfSKever Yang #include <asm/io.h>
10*c418addfSKever Yang #include <asm/arch/uart.h>
11*c418addfSKever Yang #include <asm/arch/sdram_rk3036.h>
12*c418addfSKever Yang 
13*c418addfSKever Yang DECLARE_GLOBAL_DATA_PTR;
14*c418addfSKever Yang 
get_ddr_config(struct rk3036_ddr_config * config)15*c418addfSKever Yang void get_ddr_config(struct rk3036_ddr_config *config)
16*c418addfSKever Yang {
17*c418addfSKever Yang 	/* K4B4G1646Q config */
18*c418addfSKever Yang 	config->ddr_type = 3;
19*c418addfSKever Yang 	config->rank = 2;
20*c418addfSKever Yang 	config->cs0_row = 15;
21*c418addfSKever Yang 	config->cs1_row = 15;
22*c418addfSKever Yang 
23*c418addfSKever Yang 	/* 8bank */
24*c418addfSKever Yang 	config->bank = 3;
25*c418addfSKever Yang 	config->col = 10;
26*c418addfSKever Yang 
27*c418addfSKever Yang 	/* 16bit bw */
28*c418addfSKever Yang 	config->bw = 1;
29*c418addfSKever Yang }
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