Lines Matching refs:bw
400 u32 cs, bw, die_bw, col, row, bank; in calculate_ddrconfig() local
407 bw = cap_info->bw; in calculate_ddrconfig()
417 tmp = ((row - 13) << 4) | (1 << 3) | (bw << 1) | in calculate_ddrconfig()
430 tmp = ((cs - 1) << 7) | ((row - 13) << 4) | (bw << 1) | die_bw; in calculate_ddrconfig()
442 if (((bw + col - 10) == (ddr_cfg_2_rbc[i] & in calculate_ddrconfig()
453 ((bw + col - 10) << 0); in calculate_ddrconfig()
478 (col + bw) == 12) in calculate_ddrconfig()
557 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
1279 if (cap_info->bw == 2) in phy_cfg()
1281 else if (cap_info->bw == 1) in phy_cfg()
2119 (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw)); in high_freq_training()
2223 u32 bw, bl; in update_noc_timing() local
2225 bw = 8 << sdram_params->ch.cap_info.bw; in update_noc_timing()
2229 if ((bw / 8 * bl) <= 16) in update_noc_timing()
2231 else if ((bw / 8 * bl) == 32) in update_noc_timing()
2233 else if ((bw / 8 * bl) == 64) in update_noc_timing()
2239 (bl * bw / 8) > 16 ? (bl / 4) : (16 / (bl * bw / 8)) * bl / 4; in update_noc_timing()
2244 (bw == 16) ? 0x1 : 0x2; in update_noc_timing()
2292 if (cap_info->bw == 2) in split_setup()
2549 cap_info->bw = byte / 2; in modify_ddr34_bw_byte_map()
2590 if (sdram_params->ch.cap_info.bw == 2) { in sdram_init_()
2798 cap_info->bw = 2; in dram_detect_cap()
2810 cap_info->bw = 1; in dram_detect_cap()
2812 cap_info->bw = 0; in dram_detect_cap()
2843 u32 row, bktmp, coltmp, bw; in dram_detect_cs1_row() local
2866 bw = cap_info->bw; in dram_detect_cs1_row()
2869 if (bw == 2) in dram_detect_cs1_row()
2876 max_row = max_row - bktmp - coltmp - bw - cs_add + 1; in dram_detect_cs1_row()
2885 cs_add + bw - 1ul))); in dram_detect_cs1_row()
3272 die_cap = (u32)(cs0_cap >> (20 + (cap_info->bw - cap_info->dbw))); in pctl_modify_trfc()
3397 sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw; in ddr_set_rate()