Lines Matching refs:bw
135 u32 bw, die_bw, col, bank; in calculate_ddrconfig() local
139 bw = cap_info->bw; in calculate_ddrconfig()
146 ddrconf = 7 + bw; in calculate_ddrconfig()
148 ddrconf = 12 - bw; in calculate_ddrconfig()
151 tmp = ((bank - 2) << 3) | (col + bw - 10); in calculate_ddrconfig()
186 cs_pst = cap_info->bw + cap_info->col + in set_ctl_address_map()
220 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) in set_ctl_address_map()
246 u32 i, bw; in check_rd_gate() local
248 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
249 switch (bw) { in check_rd_gate()
251 bw = 1; in check_rd_gate()
254 bw = 2; in check_rd_gate()
258 bw = 4; in check_rd_gate()
262 for (i = 0; i < bw; i++) { in check_rd_gate()
297 static void dram_set_bw(struct dram_info *dram, u32 bw) in dram_set_bw() argument
299 phy_dram_set_bw(dram->phy, bw); in dram_set_bw()
433 &sdram_params->base, cap_info->bw); in sdram_init_()
505 u32 bw = 1; in dram_detect_cap() local
550 bw = 2; in dram_detect_cap()
552 bw = 1; in dram_detect_cap()
553 cap_info->bw = bw; in dram_detect_cap()